membar_ops man page on SmartOS

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       membar_ops, membar_enter, membar_exit, membar_producer, membar_consumer
       - memory access synchronization barrier operations

       #include <atomic.h>

       void membar_enter(void);

       void membar_exit(void);

       void membar_producer(void);

       void membar_consumer(void);

       The membar_enter() function is a generic	 memory	 barrier  used	during
       lock  entry.  It is placed after the memory operation that acquires the
       lock to guarantee that the lock protects its data. No stores from after
       the  memory  barrier  will reach visibility and no loads from after the
       barrier will be resolved before the  lock  acquisition  reaches	global

       The membar_exit() function is a generic memory barrier used during lock
       exit. It is placed before the	  memory operation that	 releases  the
       lock to guarantee that the lock protects its data. All loads and stores
       issued before the barrier      will be resolved before  the  subsequent
       lock update reaches visibility.

       The  membar_enter()  and	 membar_exit()	functions are used together to
       allow regions of code to be in relaxed store order and then ensure that
       the  load or store order is maintained at a higher level. They are use‐
       ful in the implementation of mutex exclusion locks.

       The membar_producer() function arranges for all	stores	issued	before
       this  point  in	the  code to reach global visibility before any stores
       that follow.  This is useful in producer modules	 that  update  a  data
       item,  then set a flag that it is available. The memory barrier guaran‐
       tees that the available flag is not visible earlier  than  the  updated
       data, thereby imposing store ordering.

       The  membar_consumer()  function	 arranges  for all loads issued before
       this point in the code to be completed  before  any  subsequent	loads.
       This  is useful in consumer modules that check if data is available and
       read the data. The memory barrier guarantees that the data is not  sam‐
       pled  until  after  the	available flag has been seen, thereby imposing
       load ordering.

       No values are returned.

       No errors are defined.

       See attributes(5) for descriptions of the following attributes:

       │Interface Stability │ Stable	      │
       │MT-Level	    │ MT-Safe	      │

       atomic_add(3C),	 atomic_and(3C),   atomic_bits(3C),    atomic_cas(3C),
       atomic_dec(3C),	  atomic_inc(3C),    atomic_ops(3C),	atomic_or(3C),
       atomic_swap(3C), attributes(5), atomic_ops(9F)

       Atomic instructions (see atomic_ops(3C)) ensure	global	visibility  of
       atomically-modified  variables  on completion. In a relaxed store order
       system, this does not guarantee that the visibility of other  variables
       will  be synchronized with the completion of the atomic instruction. If
       such synchronization is required, memory barrier instructions  must  be

				 Feb 14, 2005			MEMBAR_OPS(3C)

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