eisa_dma_cb man page on IRIX

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eisa_dma_cb(D4)						       eisa_dma_cb(D4)

NAME
     eisa_dma_cb - DMA command block structure

SYNOPSIS
     #include <sys/types.h>
     #include <sys/eisa.h>

DESCRIPTION
     The EISA DMA command block structure is used to control a DMA operation.

USAGE
     Each DMA operation requested by a driver is controlled by a command block
     structure whose fields specify the operation to occur.

     The DMA control block specifies the parameters to be programmed for a
     requestor and a target.  The requestor is the hardware device that is
     requesting the DMA operation, while the target is the target of the
     operation.	 The typical case is one in which the requestor is an I/O
     device and the target is memory.

     EISA DMA command block structures should only be allocated via
     eisa_dma_get_cb(D3X).  Although drivers may access the structure members
     listed below, they should not make any assumptions about the size of the
     structure or the contents of other fields in the structure.

   Structure Definitions
     The eisa_dma_cb structure contains the following members:

     struct eisa_dma_buf  *reqrbufs;   /* requestor data buffer list */
     uchar_t		  trans_type;  /* Single/Demand/Block/Cascade */
     uchar_t		  reqr_path;   /* 8/16/32 */
     uchar_t		  bufprocess;  /* Single/Chain/Auto-Init */
     uchar_t		  reqr_bswap;  /* byte swap data on/off */
     char		  *procparam;  /* parameter buffer for appl call */
     int		  (*proc)();   /* address of application call routines */

     The following bit-fields defined in the eisa_dma_cb structure should be
     initialized using the appropriate EISA defines described below:

     cb_cmd;	     /* Read/Write/Translate/Verify */
     targ_step;	     /* Inc/Dec/Hold  */
     trans_type;     /* Single/Demand/Block/Cascade */
     reqr_path;	     /* 8/16/32 */
     reqr_timing;    /* A, B, C, ISA compatible */
     reqr_ringstop;  /* use channel's stop registers */
     reqr_eop:	     /* is EOP input/output */

     The members of the eisa_dma_cb structure are:

     reqrbufs is a pointer to a list of DMA buffer structures [see
     eisa_dma_buf(D4)] that describes the requestor of the DMA operation.

									Page 1

eisa_dma_cb(D4)						       eisa_dma_cb(D4)

     bufprocess specifies how the DMA target buffer structures are to be
     processed.	 It may have the following values:

	  EISA_DMA_BUF_SNGL Specifies that the target consists of a single DMA
			    Buffer.

	  EISA_DMA_BUF_CHAIN
			    Specifies that the target consists of a chain of
			    DMA Buffers.

     reqr_bswap specifies whether data should be byte-swapped between the EISA
     bus and the host memory bus.  It may have one of the following values:

	  EISA_DMA_BSWAP_ON Specifies that byte swapping should be performed.

	  EISA_DMA_BSWAP_OFF
			    Specifies that byte swapping should not be
			    performed.

     procparam is the parameter to be passed to the subroutine specified by
     the proc field.

     proc specifies the address of a routine to be called when a DMA operation
     is enabled by eisa_dma_enable(D3X).  Typically, this is used to program
     the hardware commands that initiate the DMA operation.  The value in the
     procparam field is passed as an argument to this routine.	This field may
     be set to NULL if no procedure is to be called.

     cb_cmd specifies the command for the DMA operation.  It may be one of the
     following values:

	  EISA_DMA_CMD_READ Specifies a DMA read from the target to the
			    requestor.

	  EISA_DMA_CMD_WRITE
			    Specifies a DMA write from the requestor to the
			    target.

     targ_step specifies how the target addresses are to be modified after
     each transfer.  They each may have one of the following values:

	  EISA_DMA_STEP_INC Specifies that the target address is to be
			    incremented following each data transfer.

	  EISA_DMA_STEP_DEC Specifies that the target address is to be
			    decremented following each data transfer

     trans_type specifies the transfer type of the operation.  It can have one
     of the following values:

									Page 2

eisa_dma_cb(D4)						       eisa_dma_cb(D4)

	  EISA_DMA_TRANS_SNGL
			    Specifies that a single transfer is to occur.

	  EISA_DMA_TRANS_BLCK
			    Specifies that a block transfer is to occur.  This
			    is the only acceptable value for software-
			    initiated transfers.

	  EISA_DMA_TRANS_DMND
			    Specifies demand transfer mode, which is a
			    variation on block transfer in which the requestor
			    may provide additional control flow on the
			    transfer.

     reqr_path species the size of the data path for the requestor.  It may
     have one of the following values:

	  EISA_DMA_PATH_8   Specifies that the requestor uses an 8-bit data
			    path.

	  EISA_DMA_PATH_16  Specifies that the requestor uses a 16-bit data
			    path.

	  EISA_DMA_PATH_32  Specifies that the requestor uses a 32-bit data
			    path.

     reqr_timing specifies the timing mode that requestor hardware uses.  Its
     values can be:

	  EISA_DMA_TIME_ISA Specifies that ISA compatibility timing is being
			    used.

	  EISA_DMA_TIME_A   Specifies that EISA type A timing is being used.

	  EISA_DMA_TIME_B   Specifies that EISA type B timing is being used.

	  EISA_DMA_TIME_C   Specifies that EISA type C timing is being used.

     reqr_ringstop indicates whether or not the EISA ring buffer feature
     should be enabled or disabled.  It may have one of the following values:

	  EISA_DMA_RING_OFF Disable the EISA ring buffer feature.

	  EISA_DMA_RING_ON  Enable the EISA ring buffer feature.

     reqr_eop indicates whether EOP acts as a hardware input or output.
     Typically EOP operates as an output to generate interrupts.  It may have
     one of the following values:

     EISA_DMA_EOP_OUTPUT
		       EOP is an output.

									Page 3

eisa_dma_cb(D4)						       eisa_dma_cb(D4)

     EISA_DMA_EOP_INPUT
		       EOP is an input.

REFERENCES
     eisa_dma_buf(D4), eisa_dma_free_cb(D3X), eisa_dma_get_cb(D3X),
     eisa_dma_prog(D3X), eisa_dma_swstart(D3X)

									Page 4

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