VMS Help MACRO, VAX MACRO Assembler, Instructions, MFPR  *Conan The Librarian (sorry for the slow response - running on an old VAX)

    Purpose:        Move from processor register - access
                    internal privileged registers
    Format:         opcode procreg.rl,dst.wl
    Operation:      if {PSL<current-mode> NEQ 0} then {reserved
                    instruction fault}; dst = PRS[procreg]
    C. Codes:       N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C

                    C. Codes not affected if destination is not
                    replaced.
    Exceptions:     Reserved operand, privileged instruction
    Opcode:         DB    MFPR     Move from processor register
    Description:    The specified register is stored in dst. The first
                    operand procreg is a longword that contains the
                    register number. Execution may have register
                    specific side effects. A reserved operand fault
                    can occur if the register does not exist. A
                    reserved instruction fault will occur if MFPR
                    is executed in other than kernel mode.

1 - Processor Registers

    The following table is a summary of the registers accessible in
    the privileged register space. Each mnemonic can be used to form
    a symbol by prefixing it with "PR$_". The number of a register,
    once assigned, will not change across implementations of the VAX
    or within an implementation. All unsigned positive number are
    reserved to Digital, all negative number are reserved for
    customers.

    The type column indicates whether the register is read-only,
    write-only, or may be both read and written. The scope column
    indicates whether the register is maintained on a per-process
    basis or a per-CPU basis. The init column indicates whether the
    register is set to some predefined initial value. The dashes
    mean initialization is optional.

    Register Name              Mnemonic  Number  Type  Scope Init
    Kernel stack pointer        KSP         0     R/W   PROC  ---
    Executive stack pointer     ESP         1     R/W   PROC  ---
    Supervisor stack pointer    SSP         2     R/W   PROC  ---
    User stack pointer          USP         3     R/W   PROC  ---
    Interrupt stack pointer     ISP         4     R/W   CPU   ---
    P0 base register            P0BR        8     R/W   PROC  ---
    P0 length register          P0LR        9     R/W   PROC  ---
    P1 base register            P1BR       10     R/W   PROC  ---
    P1 length register          P1LR       11     R/W   PROC  ---
    System base register        SBR        12     R/W   CPU   ---
    System length register      SLR        13     R/W   CPU   ---
    Process control block base  PCBB       16     R/W   PROC  ---
    System block base           SCBB       17     R/W   CPU   ---
    Interrupt level             IPL        18     R/W   CPU   yes
    AST level                   ASTLVL     19     R/W   PROC  yes
    Software interrupt request  SIRR       20     W     CPU   ---
    Software interrupt summary  SISR       21     R/W   CPU   yes
    Interval clock control      ICCS       24     R/W   CPU   yes
    Next interval count         NICR       25     W     CPU   ---
    Interval count              ICR        26     R     CPU   ---
    Time of year                TODR       27     R/W   CPU   no
    Console receiver C/S        RXCS       32     R/W   CPU   yes
    Console receiver D/B        RXDB       33     R     CPU   ---
    Console transmit C/S        TXCS       34     R/W   CPU   yes
    Console transmit D/B        TXDB       35     W     CPU   ---
    Memory management enable    MAPEN      56     R/W   CPU   yes
    Trans. buf. inval. all      TBIA       57     W     CPU   ---
    Trans. buf. inval. single   TBIS       58     W     CPU   ---
    Performance monitor enable  PMR        61     R/W   PROC  yes
    System identification       SID        62     R     CPU   no