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MACRO, VAX MACRO Assembler, Instructions
*Conan The Librarian (sorry for the slow response - running on an old VAX)
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Purpose: Add compare and branch - maintain loop count
and loop
Format: opcode limit.rx,add.rx,index.rx,displ.bw
Operation: index = index + add; if {{add GEQ 0} AND {index LEQ
limit}} OR {{add LSS 0} AND {index GEQ limit}} then
PC = PC + SEXT (displ)
C. Codes: N = {index LSS 0}, Z = {index EQL 0}, C = C,
V = {integer or floating overflow}
Exceptions: Integer or floating overflow, floating
underflow, reserved operand
Opcodes: 9D ACBB Add compare and branch byte
3D ACBW Add compare and branch word
F1 ACBL Add compare and branch long
4F ACBF Add compare and branch F_floating
6F ACBD Add compare and branch D_floating
4FFD ACBG Add compare and branch G_floating
6FFD ACBH Add compare and branch H_floating
Description: add is added to index and index is replaced by the
result. index is compared with limit. If add is
greater than or equal to zero and the comparison is
less than or equal to zero or if add is less than
zero and the comparison is greater than or equal,
the branch is taken. The condition codes are
unpredictable on a reserved operand fault.
Purpose: Add aligned word interlocked - maintain operating
system resource usage counts
Format: opcode add.rw,sum.mw
Operation: tmp = add; {set interlock}; sum = sum + tmp;
{release interlock}
C. Codes: N = {sum LSS 0}, Z = {sum EQL 0},
V = {integer overflow}, C = {carry from MSB}
Exceptions: Reserved operand fault, integer overflow
Opcode: 58 ADAWI Add aligned word interlocked
Description: The add operand is added to sum and sum is replaced
by the result. The operation is interlocked against
ADAWI operations by other processors or devices in
the system. The destination must be aligned on a
word boundary, i.e. bit zero of sum's address must
be zero. A reserved operand fault is taken if it
is not.
Purpose: Perform arithmetic addition
Format: opcode add.rx,sum.mx ;2 operand
opcode add1.rx,add2.rx,sum.wx ;3 operand
Operation: sum = sum + add ;2 operand
sum = add1 + add2 ;3 operand
C. Codes: N = {sum LSS 0}, Z = {sum EQL 0}, V = {overflow},
C = 0 (floating), C = {carry from MSB} (integer)
Exceptions: Integer or floating overflow, floating
underflow, reserved operand
Opcodes: 80 ADDB2 Add byte 2 operand
81 ADDB3 Add byte 3 operand
A0 ADDW2 Add word 2 operand
A1 ADDW3 Add word 3 operand
C0 ADDL2 Add long 2 operand
C1 ADDL3 Add long 3 operand
40 ADDF2 Add F_floating 2 operand
41 ADDF3 Add F_floating 3 operand
60 ADDD2 Add D_floating 2 operand
61 ADDD3 Add D_floating 3 operand
40FD ADDG2 Add G_floating 2 operand
41FD ADDG3 Add G_floating 3 operand
60FD ADDH2 Add H_floating 2 operand
61FD ADDH3 Add H_floating 3 operand
Purpose: Add one packed decimal string to another
Format: opcode addlen.rw,addaddr.ab,
sumlen.rw, sumaddr.ab ;4 operand
opcode add1len.rw,add1addr.ab,add2len.rw,
add2addr.ab,sumlen.rw,sumaddr.ab ;6 operand
Operation: {sum string} = {sum string} +
{add string} ;4 operand
{sum string} = {add1 string} +
{add2 string} ;6 operand
C. Codes: N = {{sum string} LSS 0}, Z = {{sum string} EQL 0},
V = {decimal overflow}, C = 0
Exceptions: Reserved operand, decimal overflow
Opcodes: 80 ADDP4 Add packed 4 operand
81 ADDP6 Add packed 6 operand
Description: In 4 operand format, the addend string as specified
by addlen and addaddr is added to the sum string
specified by sumlen and sumaddr, and sum is replaced
by the result. In 6 operand format, the addend 1
string specified by add1len and add1addr is added to
the addend 2 string specified by add2len and
add2addr, and the sum string is replaced by the
result.
Notes: After execution of ADDP4:
R0 = 0
R1 = address of the byte containing the
most-significant digit of the addend string
R2 = 0
R3 = address of the byte containing the
most-significant digit of the sum string
After execution of ADDP6:
R0 = 0
R1 = address of the byte containing the
most-significant digit of the addend 1 string
R2 = 0
R3 = address of the byte containing the
most-significant digit of the addend 2 string
R4 = 0
R5 = address of the byte containing the
most-significant digit of the sum string
Purpose: Add with carry - perform extended-precision addition
Format: opcode add.rl,sum.ml
Operation: sum = sum + add + C
C. Codes: N = {sum LSS 0}, Z = {sum EQL 0},
V = {integer overflow}, C = {carry from MSB}
Exceptions: Integer overflow
Opcode: D8 ADWC Add with carry
Purpose: Add one and branch - increment integer loop count
and loop
Format: opcode limit.rl,index.ml,displ.bb
Operation: index = index + 1; if {{AOBLSS} and {index LSS
limit}} or {{AOBLEQ} and {index LEQ limit}} then
PC = PC + SEXT (displ)
C. Codes: N = {index LSS 0}, Z = {index EQL 0},
V = {integer overflow}, C = C
Exceptions: Integer overflow
Opcodes: F2 AOBLSS Add one, branch less than
F3 AOBLEQ Add one, branch less or equal
Purpose: Shift of integer
Format: opcode cnt.rb,src.rx,dst.wx
Operation: dst = src shifted cnt bits
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0},
V = {integer overflow}, C = 0
Exceptions: Integer overflow
Opcodes: 78 ASHL Arithmetic shift long
79 ASHQ Arithmetic shift quad
Description: src is arithmetically shifted by the number of bits
specified by cnt and the result is placed in dst.
Positive cnt shifts left bringing 0's into the LSB.
Negative cnt shifts right bringing copies of the MSB
into the MSB. Zero cnt copies dst to src unaffected.
ASHP
Purpose: Arithmetic shift and round packed - scale numeric
content of a packed decimal string by a power of ten
Format: opcode cnt.rb,srclen.rw,srcaddr.ab,round.rb,
dstlen.rw,dstaddr.ab
Operation: {dst string} = {{src string} + {round <3:0>*
(10**(-cnt-1))}} * (10**cnt);
C. Codes: N = {{dst string} LSS 0}, Z = {{dst string} EQL 0},
V = {decimal overflow}, C = 0
Exceptions: Reserved operand, decimal overflow
Opcodes: F8 ASHP Arithmetic shift packed
Description: src as specified by srclen and srcaddr is scaled by
a power of 10 specified by cnt. dst is replaced by
the result. A positive cnt effectively multiplies,
a negative cnt effectively divides and a zero cnt
just moves src to dst while affecting the condition
codes. If cnt is negative the result is rounded
using round.
Notes: After execution:
R0 = 0
R1 = address of the byte containing the
most-significant digit of the source string
R2 = 0
R3 = address of the byte containing the
most-significant digit of the destination string
Purpose: Branch - test condition code(s)
Format: opcode displ.bb
Operation: if {condition} then PC = {PC + SEXT (displ)}
C. Codes: Not affected
Exceptions: None
Opcodes: 12 {Z EQL 0} BNEQ Branch not equal (s)
BNEQU Branch not equal (u)
13 {Z EQL 1} BEQL Branch equal (s)
BEQLU Branch equal (u)
14 {(N OR Z) EQL 0} BGTR Branch greater than (s)
15 {(N OR Z) EQL 1} BLEQ Branch less or equal (s)
18 {N EQL 0} BGEQ Branch greater, equal (s)
19 {N EQL 1} BLSS Branch less than (s)
1A {(C OR Z) EQL 0} BGTRU Branch greater than (u)
1B {(C OR Z) EQL 1} BLEQU Branch less or equal (u)
1C {V EQL 0} BVC Branch overflow clear
1D {V EQL 1} BVS Branch overflow set
1E {C EQL 0} BGEQU Branch greater, equal (u)
BCC Branch carry clear
1F {C EQL 1} BLSSU Branch less than (u)
BCS Branch carry set
legend: s - signed, u - unsigned
Description: The condition codes are tested and if the condition
indicated by the instruction is met, the sign
extended branch displacement is added to the PC.
Purpose: Branch on bit - test selected bit
Format: opcode pos.rl,base.ab,displ.bb
Operation: teststate = {if {BBS} then 1 else 0}; if {FIELD
(pos, 1, base) EQL teststate} then PC = {PC +
SEXT (displ)}
C. Codes: Unaffected
Exceptions: Reserved operand
Opcodes: E0 BBS Branch on bit set
E1 BBC Branch on bit clear
Description: The single bit field specified by pos and base is
tested. If it is in the test state indicated by the
instruction, the sign extended branch displacement
is added to PC and the result is placed in PC.
Purpose: Branch on bit - test and modify selected bit
Format: opcode pos.rl,base.ab,displ.bb
Operation: teststate = if {BBSS or BBSC} then 1 else 0;
newstate = if {BBSS or BBCS} then 1 else 0; temp =
FIELD (pos, 1, base); FIELD (pos, 1, base) =
newstate; if temp EQL teststate then PC = {PC +
SEXT (displ)}
C. Codes: Unaffected
Exceptions: Reserved operand
Opcodes: E2 BBSS Branch on bit set and set
E3 BBCS Branch on bit clear and set
E4 BBSC Branch on bit set and clear
E5 BBCC Branch on bit clear and clear
Description: The single bit field specified by pos and base is
tested. If it is in the test state indicated by the
instruction, the sign extended branch displacement
is added to PC and placed in PC. Regardless of
whether the branch is taken or not, the tested bit
is put in the new state as indicated by the
instruction.
Purpose: Branch on bit interlocked - test and modify selected
bit under memory interlock.
Format: opcode pos.rl,base.ab,displ.bb
Operation: teststate = if {BBSSI} then 1 else 0; newstate =
teststate; {set interlock}; temp = FIELD (pos,
1, base); FIELD (pos, 1, base) = newstate; {release
interlock}; if temp EQL teststate then PC =
{PC + SEXT(displ)}
C. Codes: Not affected
Exceptions: Reserved operand
Opcodes: E6 BBSSI Branch bit set, set interlocked
E7 BBCCI Branch bit clear, clear interlocked
Description: The single bit field specified by pos and base is
tested. If it is in the state indicated by the
instruction, the sign extended branch displacement
displ is added to PC. The bit is set to the state
indicated by the instruction. The operation is
interlocked against other processors or devices in
the system.
Purpose: Bit clear - perform complemented AND of two integers
Format: opcode mask.rx,dst.mx ;2 operand
opcode mask.rx,src.rx,dst.rx ;3 operand
Operation: dst = dst AND {NOT mask} ;2 operand
dst = src AND {NOT mask} ;3 operand
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C
Exceptions: None
Opcodes: 8A BICB2 Bit clear byte, 2 operand
8B BICB3 Bit clear byte, 3 operand
AA BICW2 Bit clear word, 2 operand
AB BICW3 Bit clear word, 3 operand
CA BICL2 Bit clear long, 2 operand
CB BICL3 Bit clear long, 3 operand
Description: In 2 operand format, dst is ANDed with the ones
complement of mask and dst is replaced by the result.
In 3 operand format, src is ANDed with the ones
complement of mask and dst is replaced by the result.
Purpose: Bit clear PSW - clear trap enables
Format: opcode mask.rw
Operation: PSW = {PSW AND {NOT mask}}
C. Codes: N = N AND {NOT mask<3>}; Z = Z AND {NOT mask<2>}
V = V AND {NOT mask<1>}; C = C AND {NOT mask<0>}
Exceptions: Reserved operand
Opcode: B8 BICPSW Bit clear PSW
Description: The PSW is ANDed with the complement of mask and PSW
is replaced by the result.
Purpose: Bit set - perform logical inclusive OR of two
integers
Format: opcode mask.rx,dst.mx ;2 operand
opcode mask.rx,src.rx,dst.rx ;3 operand
Operation: dst = dst OR mask ;2 operand
dst = src OR mask ;3 operand
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C
Exceptions: None
Opcodes: 88 BISB2 Bit set byte, 2 operand
89 BISB3 Bit set byte, 3 operand
A8 BISW2 Bit set word, 2 operand
A9 BISW3 Bit set word, 3 operand
C8 BISL2 Bit set long, 2 operand
C9 BISL3 Bit set long, 3 operand
Description: In 2 operand format, dst is ORed with mask and dst
is replaced by the result. In 3 operand format, src
is ORed with mask and dst is replaced by the result.
Purpose: Bit set PSW - set trap enables
Format: opcode mask.rw
Operation: PSW = PSW OR mask
C. Codes: N = N OR mask<3>; Z = Z OR mask<2>
V = V OR mask<1>; C = C OR mask<0>
Exceptions: Reserved operand
Opcode: B8 BISPSW Bit set PSW
Description: The PSW is ORed with mask and PSW is replaced by the
result.
Purpose: Test a set of bits for all zero
Format: opcode mask.rx,src.rx
Operation: tmp = {src AND mask}
C. Codes: N = {tmp LSS 0}, Z = {tmp EQL 0}, V = 0, C = C
Exceptions: None
Opcodes: 93 BITB Bit test byte
B3 BITW Bit test word
D3 BITL Bit test long
Description: mask is ANDed with src. Both operands are unaffected.
The only action is to affect the condition codes.
Purpose: Branch on low bit - test bit
Format: opcode src.rl,displ.bb
Operation: teststate = if {BLBS} then 1 else 0; if src<0>
EQL teststate then PC = {PC + SEXT (displ)}
C. Codes: Not affected
Exceptions: None
Opcodes: E8 BLBS Branch on low bit set
E9 BLBC Branch on low bit clear
Description: The LSB of src is tested and if it is equal to the
test state indicated by the instruction, the branch
is taken.
Purpose: Breakpoint trap - stop for debugging
Format: opcode
Operation: PSL<TP> = 0; {breakpoint fault}
C. Codes: N = 0, Z = 0, V = 0, C = 0
Exceptions: None
Opcode: 03 BPT Breakpoint fault
Description: This instruction is used, together with the T-bit,
to implement debugging facilities.
Purpose: Transfer control (branch)
Format: opcode displ.bx
Operation: PC = PC + SEXT (displ)
C. Codes: Not affected
Exceptions: None
Opcodes: 11 BRB Branch with byte displacement
31 BRW Branch with word displacement
Purpose: Branch to subroutine - transfer control to subroutine
Format: opcode displ.bx
Operation: -(SP) = PC; PC = {PC + SEXT (displ)}
C. Codes: Not affected
Exceptions: None
Opcodes: 10 BSBB Branch to sub., byte displ.
30 BSBW Branch to sub., word displ.
Description: PC is pushed onto the stack as a longword and the
branch is taken.
Purpose: bugcheck
Operation: {fault to report error}
C. Codes: not affected
Exceptions: Reserved instruction
Opcodes: FEFF BUGW Bugcheck with word message identifier
FDFF BUGL Bugcheck with longword message id
Description: The hardware treats these opcodes as RESERVED to
Digital and faults. The VAX/VMS operating system
treats these as requests to report software-detected
errors. The in-line message identifier is zero
extended to a longword and interpreted as a
condition value. If the process is privileged to
report bugs, a log entry is made. If the process is
not privileged, a reserved instruction is signalled.
Purpose: Call with general argument list - invoke a procedure
with actual arguments from anywhere in memory
Format: opcode arglist.ab,dst.ab
Operation: {align stack}; {create stack frame}; {set arithmetic
trap enables}; {set new values of AP, FP, PC}
C. Codes: N = 0, Z = 0, V = 0, C = 0
Exceptions: Reserved operand
Opcode: FA CALLG Call proc., general arglist
Description: SP is saved in a temporary (tmp) and then bits 1:0
of SP are cleared so the stack is longword aligned.
The procedure entry mask (pointed to by dst) is
scanned from bit 11 to bit 0 and the contents of the
registers whose numbers correspond to set bits in
the mask are pushed on the stack as longwords. Next
AP, FP and the current PC are pushed onto the stack
as longwords. The condition codes are cleared. A
longword containing the saved two low bits of SP in
bits 31:30 (tmp), 0 in bits 29:28, the low 12 bits
of the entry mask in bits 27:16 and the PSW in bits
15:0 with T cleared is pushed on the stack. A
longword 0 is pushed on the stack (for the condition
handler). FP is replaced by SP, AP is replaced by
arglist. The trap enables in PSW are set to a known
state. Integer and decimal overflow are set
according to bits 14 and 15 of the entry mask
respectively. The floating underflow bit is cleared
and the T-bit is unaffected. PC is replaced by dst +
2, skipping the entry mask and transferring control
to the byte beyond the mask.
Purpose: Call with stack argument list - invoke a procedure
with actual arguments on the stack
Format: opcode numarg.rl,dst.ab
Operation: {push arg count}; {align stack}; {create stack
frame}; {set arithmetic trap enables}; {set new
values of AP, FP, PC}
C. Codes: N = 0, Z = 0, V = 0, C = 0
Exceptions: Reserved operand
Opcode: FB CALLS Call proc. with stack arglist
Description: numarg is pushed on the stack as a longword (byte 0
contains the number of arguments, the high-order 24
bits are used by Digital software), SP is saved in a
temporary (tmp) and then bits 1:0 of SP are cleared
so the stack is longword aligned. The procedure
entry mask (pointed to by dst) is scanned from bit
11 to bit 0 and the contents of the registers whose
numbers correspond to set bits in the mask are
pushed on the stack as longwords. AP, FP and the
current PC are pushed onto the stack as longwords.
The condition codes are cleared. A longword
containing the saved two low bits of SP in bits
31:30 (tmp), 1 in bit 29, a 0 in bit 28, the low 12
bits of the entry mask in bits 27:16 and the PSW in
bits 15:0 with T cleared is pushed on the stack. A
longword 0 is pushed on the stack (for the condition
handler address within the procedure). FP is
replaced by SP, AP is set to the saved SP (value of
SP after numarg was pushed. The trap enables in PSW
are set to a known state. Integer and decimal
overflow are set according to bits 14 and 15 of the
entry mask respectively. The floating underflow bit
is cleared and the T-bit is unaffected. PC is
replaced by dst + 2, skipping the entry mask and
transferring control to the byte beyond the mask.
Purpose: Perform multi-way branching depending on arithmetic
input
Format: opcode selector.rx,base.rx,limit.rx,disp[0].bw,...,
disp[limit].bw
Operation: tmp = selector - base; PC = PC + if tmp LEQU limit
then SEXT (displ[tmp]) else {2 + 2*ZEXT (limit)}
C. Codes: N = {tmp LSS limit}, Z = {tmp EQL limit}, V = 0,
C = {tmp LSSU limit}
Exceptions: None
Opcodes: 8F CASEB Case byte
AF CASEW Case word
CF CASEL Case long
Description: base is subtracted from selector and tmp is replaced
by the result. The temporary tmp is compared with
limit and if it is less than or equal (unsigned) a
branch displacement is selected by tmp added to PC
and PC is replaced by the result. Otherwise 2 *
(limit+1) is added to PC and the result is placed
in PC. This causes PC to be moved past the table of
branch displacements. The condition codes are always
affected by the comparison of tmp with limit.
Purpose: Request the services of more privileged software
by changing the process mode
Format: opcode code.rw
Operation: tmp1 = {mode selected by opcode (K = 0, E = 1,
S = 2, U = 3)}; tmp2 = MINU(tmp1,PSL<CUR_MOD>);
{maximize privilege}; tmp3 = SEXT(code); if
{PSL<IS> EQLU 1} then HALT; PSL<CUR_MOD>_SP = SP
tmp4 = tmp2_sp; PROBEW (from tmp4 - 1 to tmp4 - 12
with mode = tmp2); if {access violation} then
{initiate access violation fault}; if {translation
not valid} then {initiate translation not valid};
{initiate CHMx exception with new_mode = tmp2
and parameter = tmp3 using 40 + tmp1*4 as SCB offset
using tmp4 as the new SP and not storing SP again}
C. Codes: N = 0, Z = 0, V = 0, C = 0
Exceptions: Halt
Opcodes: BC CHMK Change mode to kernel
BD CHME Change mode to executive
BE CHMS Change mode to supervisor
BF CHMU Change mode to user
Description: Change mode instructions allow processes to change
their access mode in a controlled manner. The
instructions only increase privilege. A change in
mode also results in a change of stack pointers;
the old pointer is saved, the new pointer is loaded.
The PSL, PC and any code passed by the instruction
are pushed on the new stack. The code is sign
extended. The destination mode selected by the
opcode is used to select a vector from the System
Control Block. Software convention reserves the
negative code values to customers, positive
code values to Digital.
Purpose: Clear or zero a scalar quantity
Format: opcode dst.wx
Operation: dst = 0
C. Codes: N = 0, Z = 1, V = 0, C = 0
Exceptions: None
Opcodes: 94 CLRB Clear byte
B4 CLRW Clear word
D4 CLRL Clear long
7C CLRQ Clear quad
7CFD CLRO Clear octa
D4 CLRF Clear F_floating
7C CLRD Clear D_floating
7C CLRG Clear G_floating
7CFD CLRH Clear H_floating
Description: The destination operand is replaced by 0.
Purpose: Arithmetic comparison between two scalar quantities
Format: opcode scr1.rx,src2.rx
Operation: src1 - src2
C. Codes: N = {src1 LSS src2}, Z = {src1 EQL src2},
V = 0, C = {src1 LSSU src2} (integer),
C = 0 (floating)
Exceptions: None (integer), reserved operand (floating)
Opcodes: 91 CMPB Compare byte
B1 CMPW Compare word
D1 CMPL Compare long
51 CMPF Compare F_floating
71 CMPD Compare D_floating
51FD CMPG Compare G_floating
71FD CMPH Compare H_floating
Description: src1 is compared with src2. The only action is to
affect the condition codes.
Purpose: Compare two character strings
Format: opcode len.rw,src1addr.ab,src2addr.ab ;3 operand
opcode src1len.rw,src1addr.ab,fill.rb ;5 operand
src2len.rw,src2addr.ab
Operation: {compare two strings with optional filling}
C. Codes: [final codes reflect last affecting of codes
in the operation.]
N = {{first byte} LSS {second byte}}, Z =
{{first byte} EQL {second byte}}, V = 0,
C = {{first byte} LSSU {second byte}}
Exceptions: None
Opcodes: 29 CMPC3 Compare character 3 operand
2D CMPC5 Compare character 5 operand
Description: In 3-operand format the bytes of string 1 specified
by len and src1addr are compared with string 2
specified by len and src2addr. In 5-operand format
the bytes of string 1 specified by src1len and
src1addr are compared with string 2 specified by
src2len and src2addr. If one string is longer than
the other the shorter string is conceptually
extended by appending bytes with the value of fill
to the end. Comparison proceeds until all the bytes
have been examined or inequality is detected.
Condition codes are affected by the last character
comparison.
Notes: After execution of CMPC3:
R0 = number of bytes remaining in string 1 (including
byte that terminated comparison); R0 is 0
only is strings are equal
R1 = address of the byte in string 1 that
terminated comparison; if strings are equal,
address of one byte beyond string 1
R2 = R0
R3 = address of the byte in string 2 that
terminated comparison; if strings are equal,
address of one byte beyond string 2
After execution of CMPC5:
R0 = number of bytes remaining in string 1 (including
byte that terminated comparison); R0 is 0
only if string1 and string 2 are of equal length
or string 1 was exhausted before comparison
terminated
R1 = address of the byte in string 1 that
terminated comparison; if comparison did not
terminate before string 1 exhausted,
address of one byte beyond string 1
R2 = number of bytes remaining in string 2 (including
byte that terminated comparison); R2 is 0 only
if string 1 and string 2 are of equal length or
string 2 was exhausted before comparison terminated
R3 = address of the byte in string 2 that
terminated comparison; if conmparison did not
terminate before string 2 was exhausted,
address of one byte beyond string 2
Purpose: Compare two packed decimal strings and set the
condition codes
Format: opcode len.rw,scr1addr.ab,src2addr.ab ;3 operand
opcode src1len.rw,src1addr.ab,
src2len.rw,src2addr.ab ;4 operand
Operation: ({src1addr + ZEXT(len/2)}:src1addr) =
({src2addr + ZEXT(len/2)}:src2addr) ;3 operand
({src1addr + ZEXT(src1len/2)}:src1addr =
({arc2addr + ZEXT(src2len/2)}:src2addr ;4 operand
C. Codes: N = {{src1 string} LSS {src2 string}}, V = 0,
Z = {{src1 string} EQL {src2 string}}, C = 0
Exceptions: Reserved operand
Opcodes: 35 CMPP3 Compare packed 3 operand
37 CMPP4 Compare packed 4 operand
Description: In 3-operand format, the source 1 string specified
by src1addr and len is compared with the source 2
string specified by the src2addr and len. In
4-operand format, the source 1 string is specified
by src1addr and src1len, the source 2 string by
src2addr and src2len. The only action in either
case is to affect the condition codes.
Notes: After execution of CMPP3 or CMPP4:
R0 = 0
R1 = address of the byte containing the
most-significant digit of string 1
R2 = 0
R3 = address of the byte containing the
most-significant digit of string 2
Purpose: Compare field - compare bit field to integer
Format: opcode pos.rl,size.rb,base.rb,src.rl
Operation: FIELD (pos, size, base) - src
C. Codes: N = {field LSS src}, Z = {field EQL src},
V = 0, C = {field LSSU src}
Exceptions: Reserved operand
Opcodes: EC CMPV Compare field
ED CMPZV Compare zero-extended field
Description: The field specified by pos, base and size is
compared with the source operand. For CMPV, src is
compared with the sign extended field. For CMPZV,
src is compared with the zero extended field. The
only action is to affect the condition codes.
Purpose: Calculate cyclic redundancy check for software
or communications checking
Format: opcode tbl.ab,inicrc.rl,strlen.rw,stream.ab
Operation: R0 = CRC_accumulation (initial value - inicrc,
polynomial table - tbl, data stream - (stream,
strlen))
C. Codes: N = {R0 LSS 0}, Z = {R0 EQL 0}, V = 0, C = C
Exceptions: None
Opcodes: 0B CRC Cyclic redundancy check
Description: The CRC of the data stream pointed to by stream
and of length strlen is calculated. The initial
CRC is given by inicrc and is normally 0 or -1
unless the CRC is calculated in several steps.
R0 is replaced by the result. If the polynomial
is less than order -32, the result must be
extracted from R0. The CRC polynomial is expressed
by the contents of the 16-longword table.
Purpose: Convert a signed quantity to a different signed
data type
Format: opcode src.rx,dst.wy
Operation: dst = conversion or src
C. Codes: N = dst LSS 0, Z = dst EQL 0, C = 0
V = {src cannot be represented in dst}
Exceptions: Integer/floating overflow, reserved operand
Opcodes: See table below:
from/to |Byte |Word |Long |F_float|D_float|G_float|H_float|
--------|------|------|------|------|------|-------|-------|
Byte | |99 x|98 x|4C e|6C e|4CFD e|6CFD e|
Word |33 t| |32 x|4D e|6D e|4DFD e|6DFD e|
Long |F6 t|F7 t| |4E r|6E e|4EFD e|6EFD e|
F_float |48 t|49 t|4A t| |56 e|99FD e|98FD e|
D_float |68 t|69 t|6A t|76 r| | |32FD e|
G_float |48FD t|49FD t|4AFD t|33FD r| | |56FD e|
H_float |68FD t|69FD t|6AFD t|F6FD r|F7FD r|76FD r| |
--------|------|------|------|------|------|-------|-------|
legend: t - truncate, x - sign extend, e - exact, r - rounded,
4B CVTRFL Convert and round F_floating to long
6B CVTRDL Convert and round D_floating to long
4BFD CVTRGL Convert and round G_floating to long
6BFD CVTRHL Convert and round H_floating to long
Purpose: Convert longword to a packed decimal string
Format: opcode src.rl,dstlen.rw,dstaddr.ab
Operation: {dst string} = conversion of src
C. Codes: N = {{dst string} LSS 0}, V = {decimal overflow},
Z = {{dst string} EQL 0}, C = 0
Exceptions: Reserved operand, decimal overflow
Opcode: F9 CVTLP Convert long to packed
Description: src is converted to a packed decimal string and the
destination string operand specified by dstlen and
dstaddr is replaced by the result. dst
and R0-R3 are unpredictable on a reserved operand
abort. Overlapping operands will produce correct
results.
Notes: After execution:
R0 = 0
R1 = 0
R2 = 0
R3 = address of the byte containing the
most-significant digit of the destination string
Purpose: Convert a packed decimal string to a longword
Format: opcode srclen.rw,srcaddr.ab,dst.wl
Operation: dst = conversion of {src string}
C. Codes: N = {dst LSS 0}, V = {integer overflow},
Z = {dst EQL 0}, C = 0
Exceptions: Reserved operand, integer overflow
Opcode: 36 CVTPL Convert packed to long
Description: The packed decimal source string src specified by
srclen and srcaddr is converted to a longword and
the result is placed in dst. dst is stored after all
the registers are updated. This means that dst can
be a register. Integer overflow can occur if the
decimal string converts to a value outside a
longword integer range. If this happens dst is
replaced by the low order bits of the correct
result. Overlapping operands will produce correct
results.
Notes: After execution:
R0 = 0
R1 = address of the byte containing the
most-significant digit of the source string
R2 = 0
R3 = 0
Purpose: Convert a packed decimal string to leading separate
numeric
Format: opcode srclen.rw,srcaddr.ab,dstlen.rw,dstaddr.ab
Operation: {dst string} = conversion of {src string}
C. Codes: N = {{src string} LSS 0}, V = {decimal overflow},
Z = {{src string} EQL 0}, C = 0
Exceptions: Reserved operand, decimal overflow
Opcode: 08 CVTPS Convert packed to leading separate
Description: The packed decimal source string src specified by
srclen and srcaddr is changed to a leading separate
numeric string and the result is placed in dst as
specified by dstlen and dstaddr. Conversion is
effected by replacing the lowest addressed byte of
dst by the ASCII character "+" or "-", determined by
the sign of the source string. The remaining bytes of
dst are replaced by the ASCII characters that
correspond to the digits in src.
Notes: After execution:
R0 = 0
R1 = address of the byte containing the
most-significant digit of the source string
R2 = 0
R3 = address of the sign byte of the destination
string
Purpose: Convert a packed decimal string to trailing numeric
Format: opcode srclen.rw,srcaddr.ab,tbladdr.ab,
dstlen.rw,dstaddr.ab
Operation: {dst string} = conversion of {src string}
C. Codes: N = {{src string} LSS 0}, V = {decimal overflow},
Z = {{src string} EQL 0}, C = 0
Exceptions: Reserved operand, decimal overflow
Opcode: 24 CVTPT Convert packed to trailing numeric
Description: The packed decimal source string src specified by
srclen and srcaddr is converted to a trailing
numeric string and the result is placed in dst as
specified by dstlen and dstaddr. Conversion is
effected by using the highest addressed byte of src
(i.e. the byte containing the sign and least
significant digit) as an unsigned index into a 256
byte table whose 0th entry is specified by tbladdr.
The byte read out of the table replaces the least
significant byte of dst. The remaining bytes of dst
are replaced by the ASCII representations of the
digits in src.
Notes: After execution:
R0 = 0
R1 = address of the byte containing the
most-significant digit of the source string
R2 = 0
R3 = address of the most-significant digit of
the destination string
Purpose: Convert a leading separate numeric string to packed
decimal
Format: opcode srclen.rw,srcaddr.ab,dstlen.rw,dstaddr.ab
Operation: {dst string} = conversion of {src string}
C. Codes: N = {{dst string} LSS 0}, V = {decimal overflow},
Z = {{dst string} EQL 0}, C = 0
Exceptions: Reserved operand, decimal overflow
Opcode: 09 CVTSP Convert leading separate to packed
Description: The source leading separate numeric string src
specified by srclen and srcaddr is converted to
a packed decimal string and the result is placed
in dst as specified by dstlen and dstaddr.
Notes: After execution:
R0 = 0
R1 = address of the sign byte of the source string
R2 = 0
R3 = address of the byte containing the
most-significant digit of the destination string
Purpose: Convert a trailing numeric string to packed decimal
Format: opcode srclen.rw,srcaddr.ab,tbladdr.ab,
dstlen.rw,dstaddr.ab
Operation: {dst string} = conversion of {src string}
C. Codes: N = {{dst string} LSS 0}, V = {decimal overflow},
Z = {{dst string} EQL 0}, C = 0
Exceptions: Reserved operand, decimal overflow
Opcode: 26 CVTTP Convert trailing numeric to packed
Description: The trailing numeric source string src specified by
srclen and srcaddr is converted to a packed
decimal string and the result is placed in dst as
specified by dstlen and dstaddr. Conversion is
effected by using the highest addressed byte of src
(i.e. the byte containing the sign and least
significant digit) as an unsigned index into a 256
byte table whose 0th entry is specified by tbladdr.
The byte read out of the table replaces the highest
addressed byte of dst. The packed digits of dst
are replaced by the low order four bits of each
ASCII character in src.
Notes: After execution:
R0 = 0
R1 = address of the most-significant digit of
the source string
R2 = 0
R3 = address of the byte containing the
most-significant digit of the destination string
Purpose: Decrement - subtract 1 from an integer
Format: opcode dif.mx
Operation: dif = dif - 1
C. Codes: N = dif LSS 0, Z = dif EQL 0
V = {integer overflow}, C = {borrow from MSB}
Exceptions: Integer overflow
Opcodes: 97 DECB Decrement byte
B7 DECW Decrement word
D7 DECL Decrement long
Description: One is subtracted from the dif operand and the
dif operand is replaced by the result.
Purpose: Perform arithmetic division
Format: opcode divr.rx,quo.mx ;2 operand
opcode divr.rx,divd.rx,quo.wx ;3 operand
Operation: quo = quo / divr ;2 operand
quo = divd / divr ;3 operand
C. Codes: N = {quo LSS 0}, Z = {quo EQL 0}, C = 0,
V = {overflow or {divr EQL 0}}
Exceptions: Integer or floating overflow, divide by zero
Floating underflow, reserved operand
Opcodes: 86 DIVB2 Divide byte 2 operand
87 DIVB3 Divide byte 3 operand
A6 DIVW2 Divide word 2 operand
A7 DIVW3 Divide word 3 operand
C6 DIVL2 Divide long 2 operand
C7 DIVL3 Divide long 3 operand
46 DIVF2 Divide F_floating 2 operand
47 DIVF3 Divide F_floating 3 operand
66 DIVD2 Divide D_floating 2 operand
67 DIVD3 Divide D_floating 3 operand
46FD DIVG2 Divide G_floating 2 operand
47FD DIVG3 Divide G_floating 3 operand
66FD DIVH2 Divide H_floating 2 operand
67FD DIVH3 Divide H_floating 3 operand
Purpose: Divide one packed decimal string by a second
decimal string
Format: opcode divrlen.rw,divraddr.ab,divdlen.rw,
divdaddr.ab,quolen.rw,quoaddr.ab
Operation: {quo string} = {divd string} / {divr string}
C. Codes: N = {{quo string} LSS 0}, V = {decimal overflow},
Z = {{quo string} EQL 0}, C = 0
Exceptions: Reserved operand, decimal overflow, divide by zero
Opcode: 27 DIVP Divide packed
Description: The dividend string specified by divdlen and divdaddr
is divided by the divisor string specified by divrlen
and divraddr. The result of the division is placed in
the quotient string specified by quolen and quoaddr.
Notes: After execution:
R0 = 0
R1 = address of the byte containing the
most-significant digit of the divisor string
R2 = 0
R3 = address of the byte containing the
most-significant digit of the dividend string
R4 = 0
R5 = address of the byte containing the
most-significant digit of the quotient string
Purpose: Perform extended-precision division
Format: opcode divr.rl,divd.rq,quo.wl,rem.wl
Operation: quo = divd/divr; rem = REM (divd, divr)
C. Codes: N = {quo LSS 0}, Z = {quo EQL 0}, C = 0,
V = {{integer overflow} OR {divr EQL 0}}
Exceptions: Integer overflow, divide by zero
Opcode: 7B EDIV Extended divide
Purpose: Edit Packed to Character String
Format: opcode srclen.rw,srcaddr.ab,pattern.ab,dstaddr.ab
Operation:
C. Codes: N = {src string} LSS 0; !N <- 0 if src is -0
Z = {src string} EQL 0; C = {significance}
V = {decimal overflow}; !nonzero digits lost
Exceptions: reserved operand, decimal overflow
Opcode: 38 EDITPC Edit Packed to Character String
Description: The destination string specified by the pattern and
destination address operands is replaced by the edited
version of the source string specified by the source
length and source address operands. The editing is
performed according to the pattern string, starting at
the address pattern and extending until a pattern end
pattern operator (EO$END) is encountered.
The pattern string consists of 1-byte pattern operators.
Some pattern operators take no operands. Some take a
repeat count that is contained in the rightmost nibble
of the pattern operator itself. The rest take a 1-byte
operand that immediately follows the pattern operator.
This operand is either an unsigned integer length or
a byte character.
Notes: After execution:
R0 = length of source string
R1 = address of the byte containing the
most-significant digit of the source string
R2 = 0
R3 = address of the byte containing the EO$END
pattern operator
R4 = 0
R5 = address of one byte beyond the last byte of
teh destination string
Purpose: Extended multiply and integerize - perform accurate
range reduction of math function arguments
Format: opcode mulr.rx,mulrx.rb,muld.rx,int.wl,fract.wx
Operation: int = {integer part of muld * {mulr'mulrx}};
frac = {fractional part of muld * {mulr'mulrx}}
C. Codes: N = {fract LSS 0}, Z = {fract EQL 0},
V = {integer overflow}, C = 0
Exceptions: Integer or floating overflow, divide by zero
Opcodes: 54 EMODF Ext. mul., integerize F_floating
74 EMODD Ext. mul., integerize D_floating
54FD EMODG Ext. mul., integerize G_floating
74FD EMODH Ext. mul., integerize H_floating
Description: The floating multiplier extension mulrx is concatenated
with the floating point multiplier (mulr) to gain eight
additional low order fraction bits. This is then
multiplied by muld. After multiplication, the integer
portion is extracted and a floating point number is
formed from the fractional part by truncating extra
bits. The integer part is placed in int and the
fractional part in frac.
Purpose: Perform extended-precision multiplication
Format: opcode mulr.rl,muld.rl,add.rl,prod.wq
Operation: prod = {{muld * mulr} + SEXT (add)}
C. Codes: N = {prod LSS 0}, Z = {prod EQL 0}, V = 0, C = 0
Exceptions: None
Opcode: 7A EMUL Extended multiply
Description: mulr is multiplied by muld to give a double length
is then stored in prod.
Purpose: Extract field - moves bit field to integer
Format: opcode pos.rl,size.rb,base.vb,dst.wl
Operation: EXTV: dst = if size NEQU 0 then SEXT (
FIELD (pos, size, base)) else 0
EXTZV: dst = if size NEQU 0 then ZEXT (
FIELD (pos, size, base)) else 0
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C
Exceptions: Reserved operand
Opcodes: EE EXTV Extract field, sign extend
EF EXTZV Extract field, zero extend
Description: For EXTV, dst is replaced by the sign-extended field
specified by pos, size and base. For EXTZV, dst is
replaced by the zero-extended field specified by pos,
size and base. If size is 0 dst is replaced by 0.
Purpose: Find first - locate first bit in bit field
Format: opcode startpos.rl,size.rb,base.vb,findpos.wl
Operation: Find first set or clear bit searching left
across field
C. Codes: N = 0, Z = {bit not found}, V = 0, C = 0
Exceptions: Reserved operand
Opcodes: EB FFC Find first clear
EA FFS Find first set
Description: A field specified by the startpos, size and base
operands is extracted. The field is tested for a
bit in the indicated state starting at bit 0 and
extending to the highest bit in the field. If a
bit in the desired state is found, the findpos
operand is replaced with the bit position and the
Z condition bit is cleared. If no bit in the
indicated state is found, findpos is replaced by
the position relative to base of a bit one to the
left of the specified field and the Z condition
bit is set. If size = 0, findpos is replaced by
startpos and Z is set.
Purpose: Stop processor operation
Format: opcode
Operation: If PSL<current_mode> NEQU kernel then
{reserved to Digital opcode fault}
else
{halt the processor}
C. Codes: N = 0, Z = 0, V = 0, C = 0 (fault)
Unaffected (processor halt)
Exceptions: Reserved to Digital opcode
Opcode: 00 HALT Halt
Description: If process is running in kernel mode, the processor
is halted. Otherwise, an opcode reserved to Digital
fault occurs. This opcode is 0 to trap many branches
to data.
Purpose: Increment - add 1 to an integer
Format: opcode sum.mx
Operation: sum = sum + 1
C. Codes: N = {sum LSS 0}, Z = {sum EQL 0},
V = {integer overflow}, C = {carry from MSB}
Exceptions: Integer overflow
Opcodes: 96 INCB Increment byte
B6 INCW Increment word
D6 INCL Increment long
Description: One is added to the sum operand and the
sum operand is replaced by the result.
Purpose: Index calculation of arrays of fixed length data, bit
fields and strings
Format: opcode subscript.rl,low.rl,high.rl,size.rl,indexin.rl,
indexout.rl
Operation: indexout = {indexin + subscript}*size; if {subscript
LSS low} or {subscript GTR high} then {subscript
range trap}
C. Codes: N = {indexout LSS 0}, Z = {indexout EQL 0},
V = 0, C = 0
Exceptions: Subscript range
Opcode: 0A INDEX Index
Description: indexin is added to subscript and the sum is multiplied
by size. The result is placed in indexout. If subscript
is less than low or greater than high a subscript range
trap is taken.
Purpose: Insert entry into queue at head, interlocked
Format: opcode entry.ab,header.aq
Operation: if {insertion succeded} then
begin
N <- 0;
Z <- (entry) EQL (entry+4); ! First entry in queue
V <- 0;
C <- 0;
end;
else
begin
N <- 0;
Z <- 0;
V <- 0;
C <- 1; ! Secondary interlock failed
end;
Exceptions: Reserved operand
Opcode: 5C INSQHI Insert entry into queue at head, interlocked
Description: The entry specified by the operand entry is
inserted into the queue following the header
specified by pred. If the entry inserted is the
first one in the queue, the Z bit is set; otherwise
it is cleared. The insertion is a noninterruptable
operation. The entire operation is validated before
any portion of it is attempted. The queue will be
left in a consistent state if a memory management
violation occurs.
Purpose: Insert entry into queue at tail, interlocked
Format: opcode entry.ab,header.aq
Operation: if {insertion succeded} then
begin
N <- 0;
Z <- (entry) EQL (entry+4); ! First entry in queue
V <- 0;
C <- 0;
end;
else
begin
N <- 0;
Z <- 0;
V <- 0;
C <- 1; ! Secondary interlock failed
end;
Exceptions: Reserved operand
Opcode: 5D INSQTI Insert entry into queue at tail, interlocked
Description: The entry specified by the operand entry is
inserted into the queue preceding the header
specified by pred. If the entry inserted is the
first one in the queue, the Z bit is set; otherwise
it is cleared. The insertion is a noninterruptable
operation. The entire operation is validated before
any portion of it is attempted. The queue will be
left in a consistent state if a memory management
violation occurs.
Purpose: Add entry to head or tail of queue
Format: opcode entry.ab,pred.ab
Operation: if {all memory accesses can be completed} then
begin
(entry) = (pred); ;forward link
(entry+4) = pred; ;backward link
((pred)+4) = entry; ;backward successor
(pred) = entry; ;forward predessor
end;
else
begin
{backup instruction};
{initiate fault};
end;
C. Codes: N = {(entry) LSS (entry + 4)}, V = 0,
C = {(entry) LSSU (entry + 4)},
Z = {(entry) EQL (entry + 4)}
Exceptions: None
Opcode: 0E INSQUE Insert entry in queue
Description: The queue entry specified by the operand entry is
inserted into the queue following the entry
specified by pred. If the entry inserted is the
first one in the queue, the Z bit is set; otherwise
it is cleared. The insertion is a noninterruptable
operation. The entire operation is validated before
any portion of it is attempted. The queue will be
left in a consistent state if a memory management
violation occurs.
Purpose: Insert field - moves integer to bit field
Format: opcode src.rl,pos.rl,size.rb,base.vb
Operation: if size NEQU 0 then FIELD (pos, size, base) =
src <{size -1 }>
C. Codes: Not affected
Exceptions: Reserved operand
Opcode: F0 INSV Insert field
Description: The field specified by pos, size and base is
replaced by bits {size-1}:0 of src. If size is 0
no action occurs.
Purpose: Transfer control
Format: opcode dst.ab
Operation: PC = dst
C. Codes: Not affected
Exceptions: None
Opcode: 17 JMP Jump
Purpose: Jump to subroutine - transfer control to subroutine
Format: opcode dst.ab
Operation: -(SP) = PC; PC = dst
C. Codes: Not affected
Exceptions: None
Opcode: 16 JSB Jump to subroutine
Description: PC is pushed onto the stack as a longword and the
jump is taken.
Purpose: Load processor context - restore register and
memory management context
Format: opcode
Operation: if PSL<current-mode> NEQU 0 then {opcode reserved
to Digital fault}; {invalidate per-process
translation buffer entries}; {load process general
registers from process control block}; {load process
map, ASTLVL and PME from PCB}; {save PSL and PC on
stack for subsequent REI}
C. Codes: Not affected
Exceptions: Reserved operand, privileged instruction
Opcodes: 06 LDPCTX Load process context
Description: The process control block is specified by the
internal processor register PCBB (process control
block base). The general registers are loaded from
the PCB, along with the memory management registers
describing the address space. The process entries
in the translation buffer are cleared. Execution is
switched to the kernel stack. The PC and PSL are
moved from the PCB to the stack, suitable for use
by a REI instruction.
Purpose: To locate a character in a string
Format: opcode char.rb,len.rw,addr.ab
Operation: {compare each character until equal}
C. Codes: N = 0, Z = {R0 EQL 0}, Z = 0, C = 0
Exceptions: None
Opcode: 3A LOCC Locate character
Description: char is compared with the bytes of the string
specified by addr and len. Comparison continues
until char equals the character in the string or
until the string is exhausted. If equality is
detected the Z bit is cleared, otherwise it is set.
Notes: After execution:
R0 = number of bytes remaining in the string
(including located one) if byte located;
otherwise 0
R1 = address of the byte located if located;
otherwise address of one byte beyond the
string
Purpose: To find a substring (object) in a character string
Format: opcode objlen.rw,objaddr.ab,srclen.rw,srcaddr.ab
Operation: {compare object substring with srcstring until match}
C. Codes: N = 0, Z = {R0 EQL 0}, Z = 0, C = 0
Exceptions: None
Opcode: 39 MATCHC Match characters
Description: src as specified by srclen and srcaddr is searched
for a substring which matches the object string as
specified by objlen and objaddr. If the substring
is found the Z bit is set, otherwise it is cleared.
The search continues until src is exhausted or
until a match is found.
Notes: After execution:
R0 = if a match occurred, 0; otherwise the number
of bytes in the object string
R1 = if a match occurred, the address of one byte
beyond the object string; that is,
objaddr + objlen; otherwise, the address of
the object string
R2 = if a match occurred, the number of bytes
remaining in the source string; otherwise 0
R3 = if a match occurred, the address of one byte
beyond the last byte matched; otherwise, the
address of one byte beyond the source string;
that is, srcaddr + srclen
For zero-length source and object strings, R3 and R1
contain the source and object addresses, respectively.
If both strings have 0 length or if the object string
has length 0, condition code Z is set and registers
R0-R3 are left just as though the substring were
found.
If the source has 0 length and the object string
has nonzero length, condition code Z is cleared
and registers R0-R3 are left just as though the
substring were not found.
Purpose: Move the logical complement of an integer
Format: opcode src.rx,dst.wx
Operation: dst = NOT src
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C
Exceptions: None
Opcodes: 92 MCOMB Move complemented byte
B2 MCOMW Move complemented word
D2 MCOML Move complemented long
Description: The destination operand is replaced by the ones
complement of the source operand.
Purpose: Move from processor register - access
internal privileged registers
Format: opcode procreg.rl,dst.wl
Operation: if {PSL<current-mode> NEQ 0} then {reserved
instruction fault}; dst = PRS[procreg]
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C
C. Codes not affected if destination is not
replaced.
Exceptions: Reserved operand, privileged instruction
Opcode: DB MFPR Move from processor register
Description: The specified register is stored in dst. The first
operand procreg is a longword that contains the
register number. Execution may have register
specific side effects. A reserved operand fault
can occur if the register does not exist. A
reserved instruction fault will occur if MFPR
is executed in other than kernel mode.
61.1 - Processor Registers
The following table is a summary of the registers accessible in
the privileged register space. Each mnemonic can be used to form
a symbol by prefixing it with "PR$_". The number of a register,
once assigned, will not change across implementations of the VAX
or within an implementation. All unsigned positive number are
reserved to Digital, all negative number are reserved for
customers.
The type column indicates whether the register is read-only,
write-only, or may be both read and written. The scope column
indicates whether the register is maintained on a per-process
basis or a per-CPU basis. The init column indicates whether the
register is set to some predefined initial value. The dashes
mean initialization is optional.
Register Name Mnemonic Number Type Scope Init
Kernel stack pointer KSP 0 R/W PROC ---
Executive stack pointer ESP 1 R/W PROC ---
Supervisor stack pointer SSP 2 R/W PROC ---
User stack pointer USP 3 R/W PROC ---
Interrupt stack pointer ISP 4 R/W CPU ---
P0 base register P0BR 8 R/W PROC ---
P0 length register P0LR 9 R/W PROC ---
P1 base register P1BR 10 R/W PROC ---
P1 length register P1LR 11 R/W PROC ---
System base register SBR 12 R/W CPU ---
System length register SLR 13 R/W CPU ---
Process control block base PCBB 16 R/W PROC ---
System block base SCBB 17 R/W CPU ---
Interrupt level IPL 18 R/W CPU yes
AST level ASTLVL 19 R/W PROC yes
Software interrupt request SIRR 20 W CPU ---
Software interrupt summary SISR 21 R/W CPU yes
Interval clock control ICCS 24 R/W CPU yes
Next interval count NICR 25 W CPU ---
Interval count ICR 26 R CPU ---
Time of year TODR 27 R/W CPU no
Console receiver C/S RXCS 32 R/W CPU yes
Console receiver D/B RXDB 33 R CPU ---
Console transmit C/S TXCS 34 R/W CPU yes
Console transmit D/B TXDB 35 W CPU ---
Memory management enable MAPEN 56 R/W CPU yes
Trans. buf. inval. all TBIA 57 W CPU ---
Trans. buf. inval. single TBIS 58 W CPU ---
Performance monitor enable PMR 61 R/W PROC yes
System identification SID 62 R CPU no
Purpose: Move the arithmetic negation of a scalar quantity
Format: opcode src.rx,dst.wx
Operation: dst = -scr
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0 (floating),
V = overflow (integer), C = {dst NEQ 0} (integer),
C = 0 (floating)
Exceptions: Integer overflow, reserved operand (floating)
Opcodes: 8E MNEGB Move negated byte
AE MNEGW Move negated word
CE MNEGL Move negated long
52 MNEGF Move negated F_floating
72 MNEGD Move negated D_floating
52FD MNEGG Move negated G_floating
72FD MNEGH Move negated H_floating
Description: The destination operand is replaced by the
negative of the source operand.
Purpose: Move a scalar quantity
Format: opcode src.rx,dst.wx
Operation: dst = src
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C
Exceptions: None (integer), reserved operand (floating point)
Opcodes: 90 MOVB Move byte
B0 MOVW Move word
D0 MOVL Move long
7D MOVQ Move quad
7DFD MOVO Move octa
50 MOVF Move F_floating
70 MOVD Move D_floating
50FD MOVG Move G_floating
70FD MOVH Move H_floating
Description: The destination operand is replaced by the source
operand. The source operand is not affected.
Purpose: Move address - calculate address of quantity
Format: opcode src.ax,dst.wl
Operation: dst = src
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = 0
Exceptions: None
Opcodes: 9E MOVAB Move address of byte
3E MOVAW Move address of word
DE MOVAL Move address of long
7E MOVAQ Move address of quad
7EFD MOVAO Move address of octa
DE MOVAF Move address of F_floating
7E MOVAD Move address of D_floating
7E MOVAG Move address of G_floating
7EFD MOVAH Move address of H_floating
Description: dst is replaced by the address of src. The context in
which src is evaluated is given by the data type of the
instruction. The operand at the address of src is not
referenced.
Purpose: Move character string or block of memory
Format: opcode len.rw,srcaddr.ab,dstaddr.ab ;3 operand
opcode srclen.rw,srcaddr.ab,fill.rb, ;5 operand
dstlen.rw,dstaddr.ab
Operation: {dst string} = {src string}
Exceptions: None
Opcodes: 28 MOVC3 Move character 3 operand
2C MOVC5 Move character 5 operand
Description: dst as specified by dstaddr and len (3 operand) or
dstlen (5 operand) is replaced by src as specified by
srcaddr and len (3 operand) or srclen (5 operand). If
dst is longer than src (5 operand only), the highest
addresses of dst that are not filled by src are
instead filled with fill. If dst is shorter than src,
the copied string is truncated to fit in src. The
operation of the instruction is such that any overlap
of src and dst will not affect the result.
Notes: After execution of MOVC3:
R0 = 0
R1 = address of one byte beyond the source string
R2 = 0
R3 = address of one byte beyond the destination string
R4 = 0
R5 = 0
After execution of MOVC5:
R0 = number of unmoved bytes remaining in the
source string. R0 is nonzero only if source
string is longer than the destination string
R1 = address of one byte beyond the last byte in
source string that was moved
R2 = 0
R3 = address of one byte beyond the destination string
R4 = 0
R5 = 0
Purpose: Moved a packed decimal string from one memory
location to another
Format: opcode len.rw,srcaddr.ab,dstaddr.ab
Operation: ({dstaddr + ZEXT (len/2)} : dstaddr) =
({srcaddr + ZEXT (len/2)} : srcaddr)
C. Codes: N = {{dst string} LSS 0}, V = 0,
Z = {{dst string} EQL 0}, C = C
Exceptions: Reserved operand
Opcodes: 34 MOVP Move packed
Description: The string dst specified by dstaddr and len is
replaced by the string src specified by srcaddr
and len.
Notes: After execution:
R0 = 0
R1 = address of the byte containing the
most-significant digit of the source string
R2 = 0
R3 = address of the byte containing the
most-significant digit of the destination string
Purpose: Obtain processor status
Format: opcode dst.wl
Operation: dst = PSL
C. Codes: Not affected
Exceptions: None
Opcode: DC MOVPSL Move from PSL
Purpose: to move and translate a character string
Format: opcode srclen.rw,srcaddr.ab,fill.rb,tbladdr.ab,
dstlen.rw,dstaddr.ab
C. Codes: N = {srclen LSS dstlen}, Z = {srclen EQL dstlen},
V = 0, C = {srclen LSSU dstlen}
Exceptions: None
Opcode: 2E MOVTC Move translated characters
Description: The source operand string specified by srclen and
srcaddr is translated and replaces the destination
string as specified by dstlen and dstaddr.
Translation is done by using each byte of src as an
index into tbl (a 256 byte array). The selected byte
is placed in dst. If the dst is longer than src, dst
is filled using fill. If dst is shorter than src,
the highest bytes of src are not moved. dst and src
may overlap with no ill effects -- but if dst
overlaps tbl the result is unpredictable.
Notes: After execution:
R0 = number of untranslated bytes remaining in the
source string; R0 is nonzero only if source
string is longer than destination string
R1 = address of one byte beyond the last byte in
source string that was translated
R2 = 0
R3 = address of the translation table
R4 = 0
R5 = address of one byte beyond the destination string
Purpose: To move and translate a character string, handling
escape codes (until character)
Format: opcode srclen.rw,srcaddr.ab,esc.rb,tbladdr.ab,
dstlen.rw,dstaddr.ab
C. Codes: N = {srclen LSS dstlen}, Z = {srclen EQL dstlen},
V = {terminated by escape}, C = {srclen LSSU dstlen}
Exceptions: None
Opcode: 2F MOVTUC Move translated until character
Description: The source operand string specified by srclen and
srcaddr is translated and replaces the destination
string as specified by dstlen and dstaddr. Translation
is done by using each byte of src as an index into
tbl (256 byte array). The selected byte is placed in
dst. Translation continues until a translated byte
equals esc or either string is exhausted. If
translation is terminated by esc, the condtion code
V-bit is set. If dst overlaps src or tbl, dst and the
registers are unpredictable.
Notes: After execution:
R0 = number of bytes remaining in source string
(including the byte that caused the escape);
R0 is 0 only if the entire source string was
translated and moved without escape
R1 = address of the byte that resulted in destination
string exhaustion or escape; or if no exhaustion
or escape, address of one byte beyond the
source string
R2 = 0
R3 = address of the table
R4 = number of bytes remaining in the destination
string
R5 = address of the byte in the destination string
that would have received the translated byte
that caused the escape, or would have received
a translated byte if the source string were
not exhausted; or if no exhaustion or escape,
the address of one byte beyond the destination
string
Purpose: Convert an unsigned integer to a wider unsigned
integer (move zeroed)
Format: opcode src.rx,dst.wy
Operation: dst = ZEXT (src)
C. Codes: N = 0, Z = {dst EQL 0}, V = 0, C = C
Exceptions: None
Opcodes: 9B MOVZBW Move zero-extended byte to word
9A MOVZBL Move zero-extended byte to long
3C MOVZWL Move zero-extended word to long
Description: For MOVZBW, bits 7:0 of dst are replaced by src,
bits 15:8 are zeroed. For MOVZBL, bits 7:0 of
dst are replaced by src, bits 31:8 are zeroed.
For MOVZWL, bits 15:0 of dst are replaced by src,
bits 31:16 are zeroed.
Purpose: Move to processor register - change
internal privileged registers
Format: opcode src.rl,procreg.rl
Operation: if {PSL<current-mode> NEQ 0} then {reserved
instruction fault}; PRS[procreg] = src
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C
C. Codes not affected if register is not
replaced.
Exceptions: Reserved operand, privileged instruction
Opcode: DA MTPR Move to processor register
Description: The specified register is loaded. The second operand
procreg is a longword that contains the register
number. Execution may have register-specific side
effects. A reserved operand fault can occur if the
register does not exist. A reserved instruction fault
will occur if the instruction is executed in other
than kernel mode. See the instruction MFPR for a list
of processor registers.
Purpose: Perform arithmetic multiplication
Format: opcode mulr.rx,prod.mx ;2 operand
opcode mulr.rx,muld.rx,prod.wx ;3 operand
Operation: prod = prod * mulr ;2 operand
prod = muld * mulr ;3 operand
C. Codes: N = {prod LSS 0}, Z = {prod EQL 0},
V = {overflow}, C = 0
Exceptions: Integer, floating overflow
Floating underflow, reserved operand
Opcodes: 84 MULB2 Multiply byte 2 operand
85 MULB3 Multiply byte 3 operand
A4 MULW2 Multiply word 2 operand
A5 MULW3 Multiply word 3 operand
C4 MULL2 Multiply long 2 operand
C5 MULL3 Multiply long 3 operand
44 MULF2 Multiply F_floating 2 operand
45 MULF3 Multiply F_floating 3 operand
64 MULD2 Multiply D_floating 2 operand
65 MULD3 Multiply D_floating 3 operand
44FD MULG2 Multiply G_floating 2 operand
45FD MULG3 Multiply G_floating 3 operand
64FD MULH2 Multiply H_floating 2 operand
65FD MULH3 Multiply H_floating 3 operand
Purpose: Multiply one packed decimal string by a second,
result placed in third
Format: opcode mulrlen.rw,mulraddr.ab,muldlen.rw,
muldaddr.ab,prodlen.rw,prodaddr.ab
Operation: {prod string} = {muld string} * {mulr string}
C. Codes: N = {{prod string} LSS 0}, V = {decimal overflow},
Z = {{prod string} EQL 0}, C = 0
Exceptions: Reserved operand, decimal overflow
Opcode: 25 MULP Multiply packed
Description: The multiplicand string muld specified by muldaddr
and muldlen is multiplied by the multiplier string
mulr specified by mulraddr and mulrlen. The product
is placed in the string prod as specified by prodaddr
and prodlen.
Notes: After execution:
R0 = 0
R1 = address of the byte containing the
most-significant digit of the multiplier string
R2 = 0
R3 = address of the byte containing the
most-significant digit of the multiplicand string
R4 = 0
R5 = address of the byte containing the
most-significant digit of the product string
Purpose: No operation is performed
Format: opcode
C. Codes: Not affected
Exceptions: None
Opcode: 01 NOP No Operation
Purpose: Allows fast calculation of math functions
Format: opcode arg.x,degree.rw,tbladdr.ab
Operation: result = Cdegree (first table entry)
For degree times, loop
result = arg * result
Perform multiply and retain an extended
floating fraction of 31 bits (POLYF) or
63 bits (POLYD). The fraction is truncated
before normalization.
result = result + Cnext (next table entry)
Normalize, round and check for over/
underflow only after the combined multiply/
add sequence.
if overflow then trap.
if underflow then clear result, remember
underflow and continue looping.
C. Codes: N = {R0 LSS 0}, Z = {R0 EQL 0},
V = {floating overflow}, C = 0
Exceptions: Floating overflow/underflow, reserved operand
Opcodes: 55 POLYF Polynomial evaluation F_floating
75 POLYD Polynomial evaluation D_floating
55FD POLYG Polynomial evaluation G_floating
75FD POLYH Polynomial evaluation H_floating
Purpose: Restore multiple registers from stack
Format: opcode mask.rw
Operation: Restore registers in order R14 .. R0
C. Codes: Not affected
Exceptions: None
Opcode: BA POPR Pop registers
Description: The contents of the registers whose number
corresponds to set bits in the mask operand
are replaced by longwords popped from the stack.
R[n] is pushed if mask <n> is set. The mask is
scanned from bit 14 to bit 0. Bit 15 is ignored.
Purpose: Probe accessibility - verify arguments
Format: opcode mode.rb,len.rw,base.ab
Operation: probe_mode = MAXU (mode<1:0>, PSL <PRV_MOD>);
condition_codes = {{accessibility of base} AND
{accessibilty of (base + ZEXT (len) - 1)} using
probe_mode}
C. Codes: N = 0, V = 0, C = 0,
Z = {if {accessible} then 0 else 1}
Exceptions: Translation not valid
Opcodes: 0C PROBER Probe read accessibility
0D PROBEW Probe write accessibility
Description: The PROBE instruction checks the read or write
accessibility of the first and last byte specified
by base and the zero extended length -- the bytes
in between are not checked. System software must
check all the pages in between if they are to be
accessed. The protection is checked against the
larger of the modes specified in bits <1:0> of the
mode operand and the previous mode field of the PSL.
Note that probing with a mode operand of 0 is
equivalent to probing the previous mode.
Purpose: Push address - calculate address of quantity
Format: opcode src.ax
Operation: -(SP) = src
C. Codes: N = {result LSS 0}, Z = {result EQL 0}, V = 0, C = 0
Exceptions: None
Opcodes: 9F PUSHAB Push address of byte
3F PUSHAW Push address of word
DF PUSHAL Push address of long
7F PUSHAQ Push address of quad
7FFD PUSHAO Push address of octa
DF PUSHAF Push address of F_floating
7F PUSHAD Push address of D_floating
7F PUSHAG Push address of G_floating
7FFD PUSHAH Push address of H_floating
Description: The address of src is pushed on the stack. The context
in which src is evaluated is given by the data type of
the instruction. The operand at the address of src is
not referenced. PUSHAx is equivalent to
MOVAx src,-(SP) but is shorter.
Purpose: Push source operand onto stack
Format: opcode src.rl
Operation: -(SP) = src
C. Codes: N = {src LSS 0}, Z = {src EQL 0}, V = 0, C = C
Exceptions: None
Opcode: DD PUSHL Push long
Description: The long word source operand is pushed on
the stack.
Purpose: Save multiple registers on stack
Format: opcode mask.rw
Operation: Save registers in order R0 .. R14
C. Codes: Not affected
Exceptions: None
Opcode: BB PUSHR Push registers
Description: The contents of the registers whose number corresponds
to set bits in the mask operand are pushed on the
stack as longwords. R[n] is pushed if mask <n> is set.
The mask is scanned from bit 14 to bit 0. Bit 15 is
ignored.
Purpose: Exit from an exception or interrupt service routine
and control the return
Format: opcode
Operation: tmp1 = (SP)+; tmp2 = (SP)+;
if {tmp2<current_mode> LSSU PSL<current_mode>} OR
{{tmp2<IS> EQLU 1} AND {PSL<IS> EQLU 0}} OR
{{tmp2<IS> EQLU 1} AND
{tmp2<current_mode> NEQU 0}} OR
{{tmp2<IS> EQLU 1} AND {tmp2<IPL> EQLU 0}} OR
{{tmp2<IPL> GRTU 0} AND
{tmp2<current_mode> NEQU 0}} OR
{tmp2<previous_mode> LSSU tmp2<current_mode>} OR
{tmp2<IPL> GTRU PSL<IPL>} OR
{tmp2<PSL_MBZ> NEQU 0} then
{reserved operand fault};
if {tmp2<CM> EQLU 1} AND
{{tmp2<FPD, IS, DV, FU, IV> NEQU 0} OR
{tmp2<current_mode> NEQU 3}} then
{reserved operand fault};
if PSL<IS> EQLU 1 then ISP = SP else
PSL<current_mode>_SP = SP;
if PSL<TP> EQLU 1 then tmp2<TP> = 1;
PC = tmp1;
PSL = tmp2;
if PSL<IS> EQLU 0 then
begin
SP = PSL<current_mode>_SP;
if PSL<current_mode> GEQU ASTLVL
then {request interrupt at IPL 2};
end;
{check for software interrupts}
C. Codes: N = {saved PSL<3>}, Z = {saved PSL<2>},
V = {saved PSL<1>}, C = {saved PSL<0>}
Exceptions: Reserved operand
Opcode: 02 REI Return from exception or interrupt
Description: A longword is popped from the current stack and
held in a temporary PC. A second longword is popped
and held in a temporary PSL. Validity of the popped
PSL is checked. The current stack pointer is saved
and a new stack is selected according to the new
PSL current_mode and IS fields. The level of the
highest privilege AST is checked against the current
access mode to see whether a pending AST can be
delivered. Execution resumes with the instruction
being executed at the time of the exception or
interrupt. Any instruction lookahead in the CPU
is reinitialized.
Purpose: Remove entry from queue at head, interlocked
Format: opcode header.aq,addr.wl
Operation: if {removal succeded} then
begin
N <- 0;
Z <- (header) EQL (entry+4);! Queue empty after interval
V <- {queue empty before this instruction};
C <- 0;
end;
else
begin
N <- 0;
Z <- 0;
V <- 1; ! Did not remove anything
C <- 1; ! Secondary interlock failed
end;
Exceptions: Reserved operand
Opcode: 5E REMQHI Remove entry from queue at head, interlocked
Description: If the secondary interlock is clear, the queue entry
following the header is removed from the queue and the
address operand is replaced by the address of the entry
removed. If the queue was empty prior to this instruction,
or if the secondary interlock failed, the V-bit is set;
otherwise it is cleared. If the interlock succeded and the
queue is empty at the end of this instruction, the Z-bit
is set; otherwise it is cleared.
The removal is a noninterruptable operation. The entire
operation is validated before any portion of it is
attempted. The queue will be left in a consistent state
if a memory management violation occurs.
Purpose: Remove entry from queue at tail, interlocked
Format: opcode header.aq,addr.wl
Operation: if {removal succeded} then
begin
N <- 0;
Z <- (header+4) EQL 0; ! Queue empty after removal
V <- {queue empty before this instruction};
C <- 0;
end;
else
begin
N <- 0;
Z <- 0;
V <- 1; ! Did not remove anything
C <- 1; ! Secondary interlock failed
end;
Exceptions: Reserved operand
Opcode: 5F REMQTI Remove entry from queue at tail, interlocked
Description: If the secondary interlock is clear, the queue entry
preceding the header is removed from the queue and the
address operand is replaced by the address of the entry
removed. If the queue was empty prior to this instruction,
or if the secondary interlock failed, the V-bit is set;
otherwise it is cleared. If the interlock succeded and the
queue is empty at the end of this instruction, the Z-bit
is set; otherwise it is cleared.
The removal is a noninterruptable operation. The entire
operation is validated before any portion of it is
attempted. The queue will be left in a consistent state
if a memory management violation occurs.
Purpose: Remove entry from head or tail of queue
Format: opcode entry.ab,addr.wl
Operation: if {all memory accesses can be completed} then
begin
((entry+4)) = (entry); ((entry)+4) = (entry+4);
addr = entry;
end;
else begin
{backup instruction}; {initiate fault};
end;
C. Codes: N = {(entry) LSS (entry+4)},
Z = {(entry) EQL (entry+4)},
V = {entry EQL (entry + 4)},
C = {(entry) LSSU (entry+4)}
Exceptions: None
Opcode: 0F REMQUE Remove entry from queue
Description: The queue entry specified by entry is removed from
the queue. The address operand is replaced by the
address of the entry removed. If there way no entry
in the queue to be removed, the condition code V is
set; otherwise it is cleared. The removal is a
noninterruptable operation. The entire operation is
validated before any part is executed. If a memory
management exception occurs the queue is left in a
consistent state.
Purpose: Return from called procedure
Format: opcode
Operation: {restore SP from FP}; {restore registers};
{drop stack alignment};
{if CALLS, remove arglist}; {restore PSW}
C. Codes: N = tmp1<3>, Z = tmp1<2>, V = tmp1<1>,
C = tmp1<0>
Exceptions: Reserved operand
Opcode: 04 RET Return from procedure
Description: SP is replaced with FP plus 4. A longword containing
stack alignment in bits 31:30, a CALLS/CALLG flag in
bit 29, the low 12 bits of the procedure entry mask
in bits 27:16 and a saved PSW in bits 15:0 is popped
from the stack and saved in a temporary (tmp1). PC,
FP and AP are replaced by longwords popped from the
stack. A register restore mask is formed from bits
27:16 of tmp1. Scanning from bit 0 to bit 11 of tmp1,
the contents of the registers whose numbers are
indicated by set bits in the restore mask are
replaced by longwords popped from the stack. SP is
incremented by bits 31:30 of tmp1. PSW is replaced by
bits 15:0 of tmp1. If bit 29 of tmp1 is 1 (indicating
a CALLS was used) a longword containing the number of
arguments is popped from the stack. Four times the
unsigned value of the low byte of this longword is
added to SP and SP is replaced by the result.
Purpose: Rotate of integer
Format: opcode cnt.rb,src.rl,dst.wl
Operation: dst = src rotated cnt bits
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C
Exceptions: None
Opcode: 9C ROTL Rotate long
Description: The source operand is rotated logically by the number
of bits specified by the count operand and the
destination is replaced by the result. The source
operand is unaffected. A positive count rotates to the
left, a negative to the right. A 0 count leaves the
value unaffected.
Purpose: Return from subroutine -
return control from subroutine
Format: opcode
Operation: PC = (SP)+
C. Codes: Not affected
Exceptions: None
Opcode: 05 RSB Return from subroutine
Purpose: Subtract with carry - perform extended-precision
subtraction
Format: opcode sub.rl,dif.ml
Operation: dif = dif - sub - C
C. Codes: N = {dif LSS 0}, Z = {dif EQL 0},
V = {integer overflow}, C = {borrow from MSB}
Exceptions: Integer overflow
Opcode: D9 SBWC Subtract with carry
Purpose: To find one of a set of characters in a string
Format: opcode len.rw,addr.ab,tbladdr.ab,mask.rb
Operation: {mask each character until not zero}
C. Codes: N = 0, Z = {R0 EQL 0}, Z = 0, C = 0
Exceptions: None
Opcode: 2A SCANC Scan characters
Description: The bytes of the string specified by addr and len are
used to index into a 256 byte table pointed to by
tbladdr. The byte selected from the table is ANDed
with mask. The operand proceeds until the result of
the AND is nonzero or all the bytes of the string
have been exhausted. If a nonzero AND result is
detected, the Z bit is cleared; otherwise, the Z bit
is set.
Notes: After execution:
R0 = number of bytes remaining in the string
(including the byte that produced the
nonzero AND result); R0 is 0 only if
there was no nonzero result
R1 = address of the byte that produced the
nonzero AND result, if no nonzero result,
address of one byte beyond the string
R2 = 0
R3 = address of the table
If the string has 0 length, condition code Z is set
just as though the entire string were scanned.
Purpose: To skip a character in a string
Format: opcode char.rb,len.rw,addr.ab
Operation: {compare each character until not equal}
C. Codes: N = 0, Z = {R0 EQL 0}, Z = 0, C = 0
Exceptions: None
Opcode: 3B SKPC Scan characters
Description: char is compared with the bytes of the string
specified by addr and len. Comparison continues until
char does not equal the character in the string or
until the string is exhausted. If inequality is
detected, the Z bit is cleared; otherwise, the Z bit
is set.
Notes: After execution:
R0 = number of bytes remaining in the string
(including the unequal one) if unequal byte
located; otherwise 0
R1 = address of the byte located if byte located;
otherwise address of one byte beyond the string
If the string has 0 length, condition code Z is set
just as though each byte of the entire string were
equal to the character.
Purpose: Subtract one and branch - decrement integer loop count
and loop
Format: opcode index.ml,displ.bb
Operation: index = index - 1; if {{SOBGEQ} and {index GEQ 0}} or
{{SOBGTR} and {index GTR 0}} then
PC = PC + SEXT (displ)
C. Codes: N = {index LSS 0}, Z = {index EQL 0},
V = {integer overflow}, C = C
Exceptions: Integer overflow
Opcodes: F4 SOBGEQ Subtract one, branch greater or equal
F5 SOBGTR Subtract one, branch greater than
Purpose: To skip a set of characters in a string
Format: opcode len.rw,addr.ab,tbladdr.ab,mask.rb
Operation: {mask each character until zero}
C. Codes: N = 0, Z = {R0 EQL 0}, V = 0, C = 0
Exceptions: None
Opcode: 2B SPANC Span characters
Description: The bytes of the string specified by addr and len are
used to index into a 256 byte table pointed to by
tbladdr. The byte selected from the table is ANDed
with mask. The operand proceeds until the result of
the AND is zero or all the bytes of the string have
been exhausted. If a zero AND result is detected, the
Z bit is cleared; otherwise, the Z bit is set.
Notes: After execution:
R0 = number of bytes remaining in the string
(including the byte that produced the
0 AND result); R0 is 0 only if
there was no 0 AND result
R1 = address of the byte that produced the
0 AND result, if no nonzero result,
address of one byte beyond the string
R2 = 0
R3 = address of the table
If the string has 0 length, condition code Z is set
just as though the entire string were spanned
Purpose: Perform arithmetic subtraction
Format: opcode sub.rx,dif.mx ;2 operand
opcode sub.rx,min.rx,dif.wx ;3 operand
Operation: dif = dif - sub ;2 operand
dif = min - sub ;3 operand
C. Codes: N = {dif LSS 0}, Z = {dif EQL 0},
V = {overflow}, C = 0 (floating),
C = {borrow from MSB (integer)}
Exceptions: Integer/floating overflow, floating
underflow, reserved operand
Opcodes: 82 SUBB2 Subtract byte 2 operand
83 SUBB3 Subtract byte 3 operand
A2 SUBW2 Subtract word 2 operand
A3 SUBW3 Subtract word 3 operand
C2 SUBL2 Subtract long 2 operand
C3 SUBL3 Subtract long 3 operand
42 SUBF2 Subtract F_floating 2 operand
43 SUBF3 Subtract F_floating 3 operand
62 SUBD2 Subtract D_floating 2 operand
63 SUBD3 Subtract D_floating 3 operand
42FD SUBG2 Subtract G_floating 2 operand
43FD SUBG3 Subtract G_floating 3 operand
62FD SUBH2 Subtract H_floating 2 operand
63FD SUBH3 Subtract H_floating 3 operand
Purpose: Subtract one packed decimal string from a second
Format: opcode sublen.rw,subaddr.ab,
diflen.rw,difaddr.ab ;4 operand
opcode sublen.rw,subaddr.ab,minlen.rw,
minaddr.ab,diflen.rw,difaddr.ab ;6 operand
Operation: {dif string} = {dif string} - {sub string} ;4 operand
{dif string} = {min string} - {sub string} ;6 operand
C. Codes: N = {{dif string} LSS 0}, V = {decimal overflow},
Z = {{dif string} EQL 0}, C = 0
Exceptions: Reserved operand, decimal overflow
Opcode: 25 SUBP4 Subtract packed 4 operand
23 SUBP6 Subtract packed 6 operand
Description: sub as specified by subaddr and sublen is subtracted
from dif as specified by difaddr and diflen (in 4
operand form) or min as specified by minaddr and
minlen (in 6 operand form) and the result is placed
in dif.
Notes: After execution of SUBP4:
R0 = 0
R1 = address of the byte containing the
most-significant digit of the subtrahend string
R2 = 0
R3 = address of the byte containing the
most-significant digit of the difference string
After execution of SUBP6:
R0 = 0
R1 = address of the byte containing the
most-significant digit of the subtrahend string
R2 = 0
R3 = address of the byte containing the
most-significant digit of the minuend string
R4 = 0
R5 = address of the byte containing the
most-significant digit of the difference string
Purpose: Save processor context - save register and
memory management context
Format: opcode
Operation: if PSL<current-mode> NEQU 0 then {opcode reserved
to Digital fault}; {save process general registers
in the process control block}; {remove PSL and PC
from stack and save in PCB}; {switch to interrupt
stack}
C. Codes: Not affected
Exceptions: Reserved operand, privileged instruction
Opcodes: 07 SVPCTX Load process context
Description: The process control block is specified by the
internal processor register PCBB (process control
block base). The general registers are saved in
the PCB. If the current stack in use is the kernel
stack, execution is changed to the interrupt
stack.
Purpose: Arithmetic compare of a scalar to 0.
Format: opcode src.rx
Operation: src - 0
C. Codes: N = {src LSS 0}, Z = {src EQL 0}, V = 0, C = 0
Exceptions: None (integer), reserved operand (floating)
Opcodes: 95 TSTB Test byte
B5 TSTW Test word
D5 TSTL Test long
53 TSTF Test F_floating
73 TSTD Test D_floating
53FD TSTG Test G_floating
73FD TSTH Test H_floating
Description: The condition codes are affected according to
the values of src.
Purpose: Extended function call - provides customer-defined
extensions to the instruction set
Format: opcode
Operation: {XFC fault}
C. Codes: N = 0, Z = 0, V = 0, C = 0
Exceptions: Opcode reserved to customer, customer reserved
exception
Opcodes: FC XFC Extended function call
Description: This instruction requests services of nonstandard
microcode or software. If no special microcode is
loaded, then an exception is generated to a kernel
mode software simulator. Typically the byte after
the XFC would request a specific service. Parameters
would be passed either as normal operands or in the
registers.
Purpose: Perform logical exclusive OR of two integers
Format: opcode mask.rx,dst.mx ;2 operand
opcode mask.rx,src.rx,dst.rx ;3 operand
Operation: dst = dst XOR mask ;2 operand
dst = src XOR mask ;3 operand
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C
Exceptions: None
Opcodes: 88 XORB2 Exclusive OR byte, 2 operand
89 XORB3 Exclusive OR byte, 3 operand
A8 XORW2 Exclusive OR word, 2 operand
A9 XORW3 Exclusive OR word, 3 operand
C8 XORL2 Exclusive OR long, 2 operand
C9 XORL3 Exclusive OR long, 3 operand
Description: In 2 operand format, dst is XORed with mask and dst
is replaced by the result. In 3 operand format, src
is XORed with mask and dst is replaced by the result.
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