MACRO, VAX MACRO Assembler
*Conan The Librarian (sorry for the slow response - running on an old VAX)
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VMS Help MACRO, VAX MACRO Assembler *Conan The Librarian (sorry for the slow response - running on an old VAX) |
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| 1 - Parameter |
filespec[,...]
Specifies a VAX MACRO assembly language source file to be
assembled. If you specify more than one file, separate the file
specifications with either commas (,) or plus signs (+). File
specifications separated by commas cause the MACRO assembler to
produce an object file (and, if indicated, a listing file) for each
specified file. File specifications separated by plus signs are
concatenated into one input file and produce a single object file
(and listing file).
You cannot include the asterisk (*) and the percent sign (%)
wildcard characters in a file specification. For each file
specification, the MACRO command supplies a default file type .MAR.
The MACRO assembler creates output files of one version higher than
the highest version existing in the target directory.
| 2 - Qualifiers |
/ALPHA
On Alpha systems, invokes the MACRO-64 Assembler for OpenVMS Alpha
(if installed on the system). For a description of the assembler,
see the MACRO-64 Assembler for OpenVMS Alpha Reference Manual.
/ANALYSIS_DATA
/ANALYSIS_DATA[=filespec]
/NOANALYSIS_DATA (default)
Controls whether the assembler creates an analysis data file for
the OpenVMS Source Code Analyzer (SCA), and optionally provides
the file specification.
By default, the assembler does not create an analysis data file.
If you specify the /ANALYSIS_DATA qualifier without a file
specification, the assembler creates a file with the same file
name as the first input file for the MACRO command. The default
file type for analysis data files is .ANA. When you specify the
/ANALYSIS_DATA qualifier, you can control the defaults applied to
the output file specification by the placement of the qualifier
in the command line.
/CROSS_REFERENCE
/CROSS_REFERENCE[=(function[,...])]
/NOCROSS_REFERENCE (default)
Controls whether a listing is produced of the locations in the
source file where the specified function (or functions) is
defined or referenced. If you specify only one function, you
can omit the parentheses.
You can specify the following functions:
ALL Cross-references directives, macros, operation codes,
registers, and symbols
DIRECTIVES Cross-references directives
MACROS Cross-references macros
OPCODES Cross-references operation codes
REGISTERS Cross-references registers
SYMBOLS Cross-references symbols
Because the assembler writes the cross-references to the listing
file, you must specify the /LIST qualifier with the /CROSS_
REFERENCE qualifier. If you specify no functions in the /CROSS_
REFERENCE qualifier, the assembler assumes the default value
of /CROSS_REFERENCE=(MACROS,SYMBOLS). The /NOCROSS_REFERENCE
qualifier excludes the cross-reference listing.
/DEBUG
/DEBUG[=option]
/NODEBUG (default)
Includes or excludes local symbols in the symbol table or
traceback information in the object module. You can replace the
/ENABLE and /DISABLE qualifiers with the /DEBUG and /NODEBUG
qualifiers when you use the appropriate DEBUG and TRACEBACK
options. The /DEBUG or the /NODEBUG qualifier overrides debugging
characteristics set with the .ENABLE or .DISABLE assembler
directives.
You can specify one or more of the following options:
ALL Includes in the object module all local symbols
in the symbol table, and provides all traceback
information for the debugger. This option is
equivalent to /ENABLE=(DEBUG,TRACEBACK).
NONE Makes local symbols and traceback information in
the object module unavailable to the debugger. This
option is equivalent to /DISABLE=(DEBUG,TRACEBACK).
SYMBOLS Makes all local symbols in the object module
available to the debugger. Makes traceback
information unavailable to the debugger. This option
is equivalent to /ENABLE=DEBUG and /DISABLE=TRACEBACK
together.
TRACEBACK Makes traceback information in the object module
available to the debugger and local symbols
unavailable to the debugger. This option is
equivalent to /ENABLE=TRACEBACK and /DISABLE=DEBUG
together.
If you specify no options to the /DEBUG qualifier, it assumes the
default value of /DEBUG=ALL.
/DIAGNOSTICS
/DIAGNOSTICS[=filespec]
/NODIAGNOSTICS (default)
Creates a file containing assembler messages and diagnostic
information. If you omit the file specification, the default file
name is the same as the source program; the default file type is
DIA.
No wildcard characters are allowed in the file specification.
The diagnostics file is reserved for use with Digital layered
products, such as the VAX Language-Sensitive Editor (LSE).
/DISABLE
/DISABLE=(function[,...])
/NODISABLE
Provides initial settings for the functions disabled by the
.DISABLE assembler directive. You can specify one or more of
the following functions:
ABSOLUTE Assembles relative addresses as absolute addresses.
DEBUG Includes local symbol table information in the object
file for use with the debugger.
GLOBAL Assumes undefined symbols to be external symbols.
SUPPRESSION Suppresses listing of unreferenced symbols in the
symbol table.
TRACEBACK Provides traceback information to the debugger.
TRUNCATION Truncates floating-point numbers (if truncation is
disabled, numbers are rounded).
VECTOR Enables the assembler to accept and correctly process
vector code.
If you specify only one function, you can omit the
parentheses. If you specify no functions in the
/DISABLE qualifier, it assumes the default value of
/DISABLE=(ABSOLUTE,DEBUG, TRUNCATION, VECTOR). The /NODISABLE
qualifier has the same effect as not specifying the /DISABLE
qualifier, or negates the effects of any /DISABLE qualifiers
specified earlier in the command line.
/ENABLE
/ENABLE=(function[,...])
/NOENABLE
Provides initial settings for the functions controlled by the
.ENABLE assembler directive. You can specify one or more of the
following functions:
ABSOLUTE Assembles relative addresses as absolute addresses.
DEBUG Includes local symbol table information in the object
file for use with the debugger.
GLOBAL Assumes undefined symbols to be external symbols.
SUPPRESSION Suppresses listing of unreferenced symbols in the
symbol table.
TRACEBACK Provides traceback information to the debugger.
TRUNCATION Truncates floating-point numbers (if truncation is
disabled, numbers are rounded).
VECTOR Enables the assembler to accept and correctly process
vector code.
The /NOENABLE qualifier has the same effect as not specifying
the /ENABLE qualifier, or negates the effects of any /ENABLE
qualifiers specified earlier in the command line. You can
specify one or more of the functions listed in the description
of the /DISABLE qualifier. If you specify only one function,
you can omit the parentheses. If you specify no functions
in the /DISABLE qualifier, it assumes the default value of
/ENABLE=(GLOBAL,TRACEBACK,SUPPRESSION).
/LIBRARY
/LIBRARY
/NOLIBRARY
Positional qualifier. The /LIBRARY qualifier cannot be used with
the /UPDATE qualifier.
The associated input file to the /LIBRARY qualifier must be a
macro library. The default file type is MLB. The /NOLIBRARY
qualifier has the same effect as not specifying the /LIBRARY
qualifier, or negates the effects of any /LIBRARY qualifiers
specified earlier in the command line.
The assembler can search up to 16 libraries, one of which is
always STARLET.MLB. This number applies to a particular assembly,
not necessarily to a particular MACRO command. If you enter the
MACRO command so that more than one source file is assembled,
but the source files are assembled separately, you can specify up
to 16 macro libraries for each separate assembly. More than one
macro library in an assembly causes the libraries to be searched
in reverse order of their specification.
A macro call in a source program causes the assembler to begin
the following sequence of searches:
1. An initial search of the libraries specified with the .LIBRARY
directive. The assembler searches these libraries in the
reverse order of that in which they were declared.
2. If the macro definition is not found in any of the libraries
specified with the .LIBRARY directive, a search of the
libraries specified in the MACRO command line (in the reverse
order in which they were specified).
3. If the macro definition is not found in any of the libraries
specified in the command line, a search of STARLET.MLB.
/LIST
/LIST[=filespec]
/NOLIST
Creates or omits an output listing, and optionally provides an
output file specification for it. The default file type for the
listing file is LIS. No wildcard characters are allowed in the
file specification.
An interactive MACRO command does not produce a listing file
by default. The /NOLIST qualifier, present either explicitly or
by default, causes errors to be reported on the current output
device.
The /LIST qualifier is the default for a MACRO command in a
batch job. The /LIST qualifier allows you to control the defaults
applied to the output file specification by the placement of the
qualifier in the command line. For more information on entering
output file qualifiers, see the OpenVMS User's Manual.
/OBJECT
/OBJECT[=filespec]
/NOOBJECT
Creates or omits an object module. It also defines the file
specification. By default, the assembler creates an object module
with the same file name as the first input file. The default file
type for object files is OBJ. No wildcard characters are allowed
in the file specification.
The /OBJECT qualifier controls the defaults applied to the
output file specification by the placement of the qualifier in
the command line. For more information on entering output file
qualifiers, see the OpenVMS User's Manual.
/SHOW
/SHOW[=(function[,...])]
/NOSHOW[=(function[,...])]
Provides initial settings for the functions controlled by the
assembler directives .SHOW and .NOSHOW.
You can specify one or more of the following functions:
CONDITIONALS Lists unsatisfied conditional code associated with
.IF and .ENDC MACRO directives.
CALLS Lists macro calls and repeat range expansions.
DEFINITIONS Lists macro definitions.
EXPANSIONS Lists macro expansions.
BINARY Lists binary code generated by the expansion of
macro calls.
If you specify more than one function, separate each with a
comma and enclose the list in parentheses. If you specify
no functions in the /SHOW qualifier, it increments the
listing level count; the /NOSHOW qualifier decrements the
count in similar circumstances. Because these qualifiers
contribute to the listing file, you must also specify the
/LIST qualifier when you use them. If you do not specify
the /SHOW qualifier, the MACRO command assumes a default of
/SHOW=(CONDITIONALS,CALLS,DEFINITIONS). If you specify only one
function, you can omit the parentheses.
/UPDATE
/UPDATE[=(update-filespec[,...])]
/NOUPDATE
Positional qualifier. The /UPDATE qualifier cannot be used with
the /ALPHA, the /LIBRARY, or the /MIGRATION qualifier.
Updates the input file it qualifies by using the SUMSLP batch
editor and the specified update file or files. By default, the
assembler assumes that the update file has the same file name
as the input source file and a file type of UPD. You cannot
include a wildcard character in the file specifications. If it
cannot find a specified update file, the assembler prints an
informational message and continues the assembly.
If you specify only one update file, you can omit the
parentheses. If you specify more than one update file, the
assembler merges the contents into a single list of updates
before applying the updates to the source file.
The /NOUPDATE qualifier has the same effect as not specifying the
/UPDATE qualifier, or negates any /UPDATE qualifiers specified
earlier in the command line. The input source file and update
files are not changed by the update operation. The effects of the
update appear in the compiled output. If you specify the /LIST
qualifier with the /UPDATE qualifier, the assembler writes an
audit trail of the changes to the listing file.
3 - /ANALYSIS_DATA
/ANALYSIS_DATA[=filespec]
/NOANALYSIS_DATA (default)
Controls whether the assembler creates an analysis data file for
the OpenVMS Source Code Analyzer (SCA), and optionally provides
the file specification.
By default, the assembler does not create an analysis data file.
If you specify the /ANALYSIS_DATA qualifier without a file
specification, the assembler creates a file with the same file
name as the first input file for the MACRO command. The default
file type for analysis data files is ANA. When you specify the
/ANALYSIS_DATA qualifier, you can control the defaults applied to
the output file specification by the placement of the qualifier
in the command line.
4 - /CROSS_REFERENCE
/CROSS_REFERENCE[=(function[,...])]
/NOCROSS_REFERENCE (default)
Controls whether a listing is produced of the locations in the
source file where the specified function (or functions) is
defined or referenced. If you specify only one function, you
can omit the parentheses.
You can specify the following functions:
ALL Cross-references directives, macros, operation codes,
registers, and symbols
DIRECTIVES Cross-references directives
MACROS Cross-references macros
OPCODES Cross-references operation codes
REGISTERS Cross-references registers
SYMBOLS Cross-references symbols
Because the assembler writes the cross-references to the listing
file, you must specify the /LIST qualifier with the /CROSS_
REFERENCE qualifier. If you specify no functions in the /CROSS_
REFERENCE qualifier, the assembler assumes the default value
of /CROSS_REFERENCE=(MACROS,SYMBOLS). The /NOCROSS_REFERENCE
qualifier excludes the cross-reference listing.
5 - /DEBUG
/DEBUG[=option]
/NODEBUG (default)
Includes or excludes local symbols in the symbol table or
traceback information in the object module. You can replace the
/ENABLE and /DISABLE qualifiers with the /DEBUG and /NODEBUG
qualifiers when you use the appropriate DEBUG and TRACEBACK
options. The /DEBUG or the /NODEBUG qualifier overrides debugging
characteristics set with the .ENABLE or .DISABLE assembler
directives.
You can specify one or more of the following options:
ALL Includes in the object module all local symbols
in the symbol table, and provides all traceback
information for the debugger. This option is
equivalent to /ENABLE=(DEBUG,TRACEBACK).
NONE Makes local symbols and traceback information in
the object module unavailable to the debugger. This
option is equivalent to /DISABLE=(DEBUG,TRACEBACK).
SYMBOLS Makes all local symbols in the object module
available to the debugger. Makes traceback
information unavailable to the debugger. This option
is equivalent to /ENABLE=DEBUG and /DISABLE=TRACEBACK
together.
TRACEBACK Makes traceback information in the object module
available to the debugger and local symbols
unavailable to the debugger. This option is
equivalent to /ENABLE=TRACEBACK and /DISABLE=DEBUG
together.
If you specify no options to the /DEBUG qualifier, it assumes the
default value of /DEBUG=ALL.
6 - /DIAGNOSTICS
/DIAGNOSTICS[=filespec]
/NODIAGNOSTICS (default)
Creates a file containing assembler messages and diagnostic
information. If you omit the file specification, the default file
name is the same as the source program; the default file type is
DIA.
No wildcard characters are allowed in the file specification.
The diagnostics file is reserved for use with Digital layered
products, such as the VAX Language-Sensitive Editor (LSE).
7 - /DISABLE
/DISABLE=(function[,...])
/NODISABLE
Provides initial settings for the functions disabled by the
.DISABLE assembler directive. You can specify one or more of
the following functions:
ABSOLUTE Assembles relative addresses as absolute addresses.
DEBUG Includes local symbol table information in the object
file for use with the debugger.
GLOBAL Assumes undefined symbols to be external symbols.
SUPPRESSION Suppresses listing of unreferenced symbols in the
symbol table.
TRACEBACK Provides traceback information to the debugger.
TRUNCATION Truncates floating-point numbers (if truncation is
disabled, numbers are rounded).
VECTOR Enables the assembler to accept and correctly process
vector code.
If you specify only one function, you can omit the
parentheses. If you specify no functions in the
/DISABLE qualifier, it assumes the default value of
/DISABLE=(ABSOLUTE,DEBUG, TRUNCATION, VECTOR). The /NODISABLE
qualifier has the same effect as not specifying the /DISABLE
qualifier, or negates the effects of any /DISABLE qualifiers
specified earlier in the command line.
8 - /ENABLE
/ENABLE=(function[,...])
/NOENABLE
Provides initial settings for the functions controlled by the
.ENABLE assembler directive. You can specify one or more of the
following functions:
ABSOLUTE Assembles relative addresses as absolute addresses.
DEBUG Includes local symbol table information in the object
file for use with the debugger.
GLOBAL Assumes undefined symbols to be external symbols.
SUPPRESSION Suppresses listing of unreferenced symbols in the
symbol table.
TRACEBACK Provides traceback information to the debugger.
TRUNCATION Truncates floating-point numbers (if truncation is
disabled, numbers are rounded).
VECTOR Enables the assembler to accept and correctly process
vector code.
The /NOENABLE qualifier has the same effect as not specifying
the /ENABLE qualifier, or negates the effects of any /ENABLE
qualifiers specified earlier in the command line. You can
specify one or more of the functions listed in the description
of the /DISABLE qualifier. If you specify only one function,
you can omit the parentheses. If you specify no functions
in the /DISABLE qualifier, it assumes the default value of
/ENABLE=(GLOBAL,TRACEBACK,SUPPRESSION).
9 - /LIBRARY
/LIBRARY
/NOLIBRARY
Positional qualifier. The /LIBRARY qualifier cannot be used with
the /UPDATE qualifier.
The associated input file to the /LIBRARY qualifier must be a
macro library. The default file type is MLB. The /NOLIBRARY
qualifier has the same effect as not specifying the /LIBRARY
qualifier, or negates the effects of any /LIBRARY qualifiers
specified earlier in the command line.
The assembler can search up to 16 libraries, one of which is
always STARLET.MLB. This number applies to a particular assembly,
not necessarily to a particular MACRO command. If you enter the
MACRO command so that more than one source file is assembled,
but the source files are assembled separately, you can specify up
to 16 macro libraries for each separate assembly. More than one
macro library in an assembly causes the libraries to be searched
in reverse order of their specification.
A macro call in a source program causes the assembler to begin
the following sequence of searches:
1. An initial search of the libraries specified with the .LIBRARY
directive. The assembler searches these libraries in the
reverse order of that in which they were declared.
2. If the macro definition is not found in any of the libraries
specified with the .LIBRARY directive, a search of the
libraries specified in the MACRO command line (in the reverse
order in which they were specified).
3. If the macro definition is not found in any of the libraries
specified in the command line, a search of STARLET.MLB.
10 - /LIST
/LIST[=filespec]
/NOLIST
Creates or omits an output listing, and optionally provides an
output file specification for it. The default file type for the
listing file is LIS. No wildcard characters are allowed in the
file specification.
An interactive MACRO command does not produce a listing file
by default. The /NOLIST qualifier, present either explicitly or
by default, causes errors to be reported on the current output
device.
The /LIST qualifier is the default for a MACRO command in a
batch job. The /LIST qualifier allows you to control the defaults
applied to the output file specification by the placement of the
qualifier in the command line. For more information on entering
output file qualifiers, see the OpenVMS User's Manual.
11 - /OBJECT
/OBJECT[=filespec]
/NOOBJECT
Creates or omits an object module. It also defines the file
specification. By default, the assembler creates an object module
with the same file name as the first input file. The default file
type for object files is OBJ. No wildcard characters are allowed
in the file specification.
The /OBJECT qualifier controls the defaults applied to the
output file specification by the placement of the qualifier in
the command line. For more information on entering output file
qualifiers, see the OpenVMS User's Manual.
12 - /SHOW
/SHOW[=(function[,...])]
/NOSHOW[=(function[,...])]
Provides initial settings for the functions controlled by the
assembler directives .SHOW and .NOSHOW.
You can specify one or more of the following functions:
CONDITIONALS Lists unsatisfied conditional code associated with
.IF and .ENDC MACRO directives.
CALLS Lists macro calls and repeat range expansions.
DEFINITIONS Lists macro definitions.
EXPANSIONS Lists macro expansions.
BINARY Lists binary code generated by the expansion of
macro calls.
If you specify more than one function, separate each with a
comma and enclose the list in parentheses. If you specify
no functions in the /SHOW qualifier, it increments the
listing level count; the /NOSHOW qualifier decrements the
count in similar circumstances. Because these qualifiers
contribute to the listing file, you must also specify the
/LIST qualifier when you use them. If you do not specify
the /SHOW qualifier, the MACRO command assumes a default of
/SHOW=(CONDITIONALS,CALLS,DEFINITIONS). If you specify only one
function, you can omit the parentheses.
13 - /UPDATE
/UPDATE[=(update-filespec[,...])]
/NOUPDATE
Positional qualifier. The /UPDATE qualifier cannot be used with
the /LIBRARY qualifier.
Updates the input file it qualifies by using the SUMSLP batch
editor and the specified update file or files. By default, the
assembler assumes that the update file has the same file name
as the input source file and a file type of UPD. You cannot
include a wildcard character in the file specifications. If it
cannot find a specified update file, the assembler prints an
informational message and continues the assembly.
If you specify only one update file, you can omit the
parentheses. If you specify more than one update file, the
assembler merges the contents into a single list of updates
before applying the updates to the source file.
The /NOUPDATE qualifier has the same effect as not specifying the
/UPDATE qualifier, or negates any /UPDATE qualifiers specified
earlier in the command line. The input source file and update
files are not changed by the update operation. The effects of the
update appear in the compiled output. If you specify the /LIST
qualifier with the /UPDATE qualifier, the assembler writes an
audit trail of the changes to the listing file.
| 14 - Description |
The MACRO command invokes the VAX MACRO assembler to assemble one
or more assembly language source files.
The qualifiers to the MACRO command serve as either command
(global) qualifiers or positional qualifiers. A command
qualifier affects all the files specified in the MACRO command. A
positional qualifier affects only the file that it qualifies. All
MACRO qualifiers except the /LIBRARY and /UPDATE qualifiers are
usable as either command or positional qualifiers. The /LIBRARY
and /UPDATE qualifiers are positional qualifiers only.
See the qualifier descriptions for restrictions.
For a complete functional description of the VAX MACRO assembler
directives, see the VAX MACRO and Instruction Set Reference
Manual. For a complete functional description of the MACRO-32
compiler for OpenVMS Alpha, see Migrating to an OpenVMS Alpha System:
Porting VAX MACRO Code.
| 15 - Directives |
The general assembler directives provide facilities for performing
11 types of functions; listing control, message display,
assembler option, data storage, location control, program
sectioning, symbol control, routine entry point,
conditional and subconditional assembly, cross-reference,
instruction generation, and linker option.
The alternate form, if any, is given in parentheses.
15.1 - .ADDRESS
Stores successive longwords containing addresses in the
object module. DIGITAL recommends that you use .ADDRESS rather
than .LONG for storing address data to provide additional
information to the Linker. In shareable images, addresses
that you specify with .ADDRESS produce position-independent
code.
.ADDRESS address-list
address-list
A list of symbols or expressions, separated by commas, which
VAX MACRO interprets as addresses. Repetition factors are not
allowed.
15.2 - .ALIGN
Aligns the location counter to the boundary specified by either
an integer or a keyword.
.ALIGN integer[,expression]
.ALIGN keyword[,expression]
integer
An integer in the range of 0 through 9. The location counter
is aligned at an address that is the value of 2 raised to the
power of the integer.
keyword
One of five keywords that specify the alignment boundary.
The location counter is aligned to an address that is the next
multiple of the values listed below.
Keyword Size (in Bytes)
BYTE 2^0 = 1
WORD 2^1 = 2
LONG 2^2 = 4
QUAD 2^3 = 8
PAGE 2^9 = 512
expression
Specifies the fill value to be stored in each byte. The
expression must not contain any undefined symbols and must
be an absolute expression.
15.3 - .ASCIx
ASCII character storage directives
VAX MACRO has four ASCII character storage directives:
Directive Function
ASCIC Counted ASCII string storage
ASCID String-descriptor ASCII string storage
ASCII ASCII string storage
ASCIZ Zero-terminated ASCII string storage
Each directive is followed by a string of characters enclosed in
a pair of matching delimiters. The delimiters can be any
printable character except the space or tab character, equal
sign (=), semicolon (;), or left angle bracket (<). The character
that you use as the delimiter cannot appear in the string itself.
Although you can use alphanumeric characters as delimiters, use
nonalphanumeric characters to avoid confusion.
Any character except the null, carriage return, and form
feed characters can appear within the string. The assembler
does not convert lowercase alphabetic characters to uppercase.
ASCII character storage directives convert the characters to
their 8-bit ASCII and store them one character to a byte.
Any character, including the null, carriage return, and form
feed characters, can be represented by an expression enclosed
in angle brackets outside of the delimiters. You must define the
ASCII values of null, carriage return, and form feed with a
direct assignment statement. The ASCII character storage
directives store the 8-bit binary value specified by the
expression.
ASCII strings can be continued over several lines. Use the hyphen
as the line continuation character and delimit the string on each
line at both ends. Note that you can use a different pair of
delimiters for each line.
15. 3.1 - .ASCIC
Performs the same function as .ASCII, except that .ASCIC inserts
a count byte before the string data. The count byte contains
the length of the string in bytes. The length given includes any
bytes of nonprintable characters outside the delimited string but
excludes the count byte.
.ASCIC string
string
A delimited ASCII string.
15. 3.2 - .ASCID
Performs the same function as ASCII, except that .ASCID inserts
a string descriptor before the string data.
.ASCID string
string
A delimited ASCII string.
The string descriptor has the following format:
31 0
____________________________________
| information | length |
+----------------+-----------------+
| pointer |
+----------------------------------+
length
The length of the string (two bytes).
information
Descriptor information (two bytes) is always set to 010E.
pointer
Position independent pointer to the string (four bytes).
String descriptors are used in calling procedures.
15. 3.3 - .ASCII
Stores the ASCII value of each character in the ASCII string or
the value of each byte expression in the next available byte.
.ASCII string
string
A delimited ASCII string.
15. 3.4 - .ASCIZ
Performs the same function as .ASCII, except that .ASCIZ appends
a null byte as the final character of the string. When a list or
text string is created with an .ASCIZ directive, you need only
perform a search for the null character in the last byte to
determine the end of the string.
.ASCIZ string
string
A delimited ASCII string.
15.4 - .BLKx
.BLKx expression
expression
An expression specifying the amount of storage to be allocated.
All the symbols in the expression must be defined and the
expression must be an absolute expression. If the expression is
omitted, a default value of 1 is assumed.
VAX MACRO has 10 block storage directives. The value of
the expression determines the number of data items for which VAX
MACRO reserves storage.
Directive Reserves Storage For
.BLKA addresses (longwords)
.BLKB byte data
.BLKD double-precision floating-point data
(quadwords)
.BLKF single-precision floating-point data
(longwords)
.BLKG G_floating data (quadwords)
.BLKH H_floating data (octawords)
.BLKL longword data
.BLKO octaword data
.BLKQ quadword data
.BLKW word data
15. 4.1 - .BLKA
Reserves storage for addresses (longwords)
.BLKA expression
expression
An expression specifying the amount of storage to be allocated.
15. 4.2 - .BLKB
Reserves storage for byte data
.BLKB expression
expression
An expression specifying the amount of storage to be allocated.
15. 4.3 - .BLKD
Reserves storage for double-precision floating-point
data (quadwords).
.BLKD expression
expression
An expression specifying the amount of storage to be allocated.
15. 4.4 - .BLKF
Reserves storage for single-precision floating-point
data (longwords).
.BLKF expression
expression
An expression specifying the amount of storage to be allocated.
15. 4.5 - .BLKG
Reserves storage for G_floating data (quadwords).
.BLKG expression
expression
An expression specifying the amount of storage to be allocated.
15. 4.6 - .BLKH
Reserves storage for H_floating data (octawords).
.BLKH expression
expression
An expression specifying the amount of storage to be allocated.
15. 4.7 - .BLKL
Reserves storage for longword data.
.BLKL expression
expression
An expression specifying the amount of storage to be allocated.
15. 4.8 - .BLKO
Reserves storage for octaword data.
.BLKO expression
expression
An expression specifying the amount of storage to be allocated.
15. 4.9 - .BLKQ
Reserves storage for quadword data.
.BLKQ expression
expression
An expression specifying the amount of storage to be allocated.
15. 4.10 - .BLKW
Reserves storage for word data.
.BLKW expression
expression
An expression specifying the amount of storage to be allocated.
15.5 - .BYTE
Generates successive bytes of binary data in the object module.
.BYTE expression-list
expression-list
One or more expressions separated by commas. Each expression
is first evaluated as a longword expression; then the value
of the expression is truncated to one byte. The value of each
expression should be in the range of 0 through 255 for unsigned
data or in the range of -128 through +127 for signed data.
Optionally, each expression can be followed by a repetition
factor delimited by square brackets. An expression followed by a
repetition factor has the format:
expression1[expression2]
expression1
An expression that specifies the value to be stored.
[expression2]
An expression that specifies the number of times the value will
be repeated. The expression must not contain any undefined
symbols and it must be absolute. The square brackets are required.
15.6 - .CROSS
Controls which symbols are included in the cross-reference listing.
.CROSS [symbol-list] (Default)
.NOCROSS [symbol-list]
symbol-list
A list of legal symbol names separated by commas.
When you specify the /CROSS_REFERENCE qualifier in the MACRO
command, VAX MACRO produces a cross-reference listing. The
directives have an effect only if /CROSS_REFERENCE was specified in
the MACRO command.
Using .NOCROSS with a symbol list disables the
cross-reference listing for the listed symbols only. Using .CROSS
with a symbol list enables or reenables the cross-reference
listing of the listed symbols.
15.7 - .DEBUG
Specifies that the symbols in the list are made known to the
VAX Symbolic Debugger.
.DEBUG symbol-list
symbol-list
A list of legal symbols separated by commas.
During an interactive debugging session, you can use these symbols
to refer to memory locations or to examine the values assigned
to the symbols.
The assembler adds the symbols in the symbol list to the symbol
table in the object module. You need not specify global
symbols in the .DEBUG directive because global symbols are
automatically put in the object module's symbol table.
15.8 - .DEFAULT
Determines the default displacement length for the relative
and relative deferred addressing modes.
.DEFAULT DISPLACEMENT, keyword
keyword
One of three keywords - BYTE, WORD, or LONG - indicating the
default displacement length.
This has no effect on the default displacement for displacement
and displacement deferred addressing modes. If there is no
.DEFAULT in a source module, the default displacement length for the
relative and relative deferred addressing modes is a longword.
15.9 - .D FLOATING (.DOUBLE)
Evaluates the specified floating-point constants and stores
the results in the object module. Generates 64-bit,
double-precision, floating-point data (1 bit of sign, 8 bits of
exponent, and 55 bits of fraction).
.D_FLOATING literal-list
.DOUBLE literal-list
literal-list
A list of floating-point constants, which cannot contain any unary
or binary operators except unary plus or unary minus.
Double-precision floating-point numbers are always rounded. They
are not affected by .ENABLE TRUNCATION. The floating-point
constants in the literal list must not be preceded by the
floating-point operator (^F).
15.10 - .DISABLE (.DSABL)
Disables the specified assembler functions as enabled by .ENABLE.
.DISABLE argument-list
argument-list
One or more of the following: ABSOLUTE, DEBUG, GLOBAL,
LOCAL_BLOCK, SUPPRESSION, TRACEBACK, or TRUNCATION. You can use
either the long or the short form of the symbolic arguments. If
you specify multiple arguments, separate them by commas, spaces, or
tabs.
15.11 - .ENABLE (.ENABL)
Enables the specified assembly function.
.ENABLE argument-list
argument-list
One or more of the following: ABSOLUTE, DEBUG, GLOBAL,
LOCAL_BLOCK, SUPPRESSION, TRACEBACK, or TRUNCATION. You can use
either the long or the short form of the symbolic arguments. If
you specify multiple arguments, separate them by commas, spaces, or
tabs.
ENABLE and its negative form, DISABLE, control the
following assembler functions:
o Creating local label blocks
o Making all local symbols available to the debugger
and enabling the traceback feature
o Specifying that undefined symbol references are
external references
o Truncating or rounding single-precision floating-point
numbers
o Suppressing the listing of symbols that are defined
but not referenced
o Specifying that all the PC references are absolute,
not relative
15.12 - .END
Terminates the source program.
.END [symbol]
symbol
The address (called the transfer address) at which program
execution is to begin.
No additional text should occur beyond this point in the
current source file or in any additional source files
specified in the command line for this assembly. If any additional
text does occur, the assembler ignores it.
The transfer address must be in a program section that has the
EXE attribute.
When an executable image consisting of several object modules
is linked, only one object module should be terminated by an
.END directive that specifies a transfer address. All other
object modules should be terminated by .END directives that do not
specify a transfer address.
15.13 - .ENDC
Terminates the conditional range started by the .IF directive.
.ENDC
15.14 - .ENDM
Terminates the MACRO definition.
.ENDM [macro-name]
macro-name
The name of the macro whose definition is to be terminated.
The macro name is optional; if specified, it must match the name
defined in the matching .MACRO directive. The macro name should be
specified so that the assembler can detect any improperly
nested macro definitions.
15.15 - .ENDR
Indicates the end of a repeat range. It must be the final
statement of every indefinite repeat block directive (.IRP and
.IRPC) and every repeat block directive (.REPEAT).
.ENDR
15.16 - .ENTRY
Defines a symbolic name for an entry point and stores a register
save mask (two bytes) at that location.
.ENTRY symbol,expression
symbol
The symbolic name for the entry point.
expression
The register save mask for the entry point. The expression must
be an absolute expression and must not contain any undefined
symbols.
The symbol is defined as a global symbol with a value equal to
the value of the location counter at the .ENTRY directive. You
can use the entry point as the transfer address of the program.
15.17 - .ERROR
Causes the assembler to display an error message on the terminal
or batch log file and in the listing file.
.ERROR [expression] ;comment
expression
An expression whose value is displayed when .ERROR is
encountered during assembly.
;comment
A comment that is displayed when .ERROR is encountered
during assembly. The comment must be preceded by a semicolon.
15.18 - .EVEN
Ensures that the current value of the location counter is even
by adding 1 if the current value is odd. If the current
value is already even, no action is taken.
.EVEN
15.19 - .EXTERNAL (.EXTRN)
Indicates that the specified symbols are external; that is,
the symbols are defined in another object module and cannot be
defined until link time
.EXTERNAL symbol-list
symbol-list
A list of legal symbols, separated by commas.
If the GLOBAL argument is enabled, all unresolved references will
be marked as global and external. If GLOBAL is enabled, you
need not specify .EXTERNAL. If GLOBAL is disabled, you must
explicitly specify .EXTERNAL to declare any symbols that are
defined externally but are referred to in the current module.
15.20 - .F FLOATING (.FLOAT)
Evaluates the specified floating-point constants and stores
the results in the object module. .F_FLOATING generates
32-bit, single-precision, floating-point data (1 bit of sign, 8
bits of exponent, and 23 bits of fractional significance).
.F_FLOATING literal-list
.FLOAT literal-list
literal-list
A list of floating-point constants. The constants cannot contain
any unary or binary operators except unary plus and unary
minus. The floating-point constants in the literal list must not
be preceded by the floating-point unary operator (^F).
15.21 - .G FLOATING
Evaluates the specified floating-point constants and stores
the results in the object module. .G_FLOATING generates 64-bit
data (1 bit of sign, 11 bits of exponent, and 52 bits of fraction).
.G_FLOATING literal-list
literal-list
A list of floating-point constants. The constants cannot contain
any unary or binary operators except unary plus or unary minus.
G_floating-point numbers are always rounded. They are not
affected by the .ENABLE TRUNCATION directive.
The floating-point constants in the literal list must not be
preceded by the floating-point operator (^F).
15.22 - .GLOBAL (.GLOBL)
Indicates that specified symbol names are either globally defined
in the current module or externally defined in another module.
.GLOBAL symbol-list
symbol-list
A list of legal symbol names, separated by commas.
15.23 - .H FLOATING
Evaluates the specified floating-point constants and stores
the results in the object module. .H_FLOATING generates 128-bit
data (1 bit of sign, 15 bits of exponent, and 112 bits of
fraction).
.H_FLOATING literal-list
literal-list
A list of floating-point constants. The constants cannot contain
any unary or binary operators except unary plus or unary minus.
H_floating-point numbers are always rounded. They are not
affected by the .ENABLE TRUNCATION directive.
The floating-point constants in the literal list must not be
preceded by the floating-point operator (^F).
15.24 - .IDENT
Provides a means of identifying the object module.
This identification is in addition to the name assigned to the
object module with .TITLE. A character string can be specified in
.IDENT to label the object module. This string is printed in the
header of the listing file and also appears in the object module.
.IDENT string
string
A 1- to 31-character string that identifies the module, such as
a string that specifies a version number.
If a source module contains more than one .IDENT, the last
directive given establishes the character string that forms part
of the object module identification.
15.25 - .IF
A conditional assembly block is a series of source statements that
is assembled only if a certain condition is met. .IF
starts the conditional block and .ENDC ends the conditional block.
.IF condition argument(s)
...
range
...
.ENDC
condition
A specified condition that must be met if the block is to be
included in the assembly. The condition must be separated from
the argument by a comma, space, or tab.
argument(s)
One or more symbolic arguments or expressions of the
specified conditional test. If the argument is an
expression, it cannot contain any undefined symbols and must be an
absolute expression.
range
The block of source code that is conditionally included in
the assembly.
Each .IF must have a corresponding .ENDC. The .IF directive
contains a condition test and one or two arguments. The
condition test specified is applied to the argument(s). If the
test is met, all VAX MACRO statements between .IF and .ENDC are
assembled. If the test is not met, the statements are not
assembled. An exception to this rule occurs when you use
subconditional directives.
VAX MACRO permits a nesting depth of 31 conditional assembly
levels.
15.26 - .IF FALSE (.IFF)
Starts a subconditional assembly block to be assembled if
the condition test specified when the conditional assembly
block was entered was false. The subconditional assembly block
that starts with .IF_FALSE continues up to the next
subconditional assembly directive or to the end of the conditional
assembly block.
.IF_FALSE
The alternate form of .IF_FALSE is .IFF.
15.27 - .IF TRUE (.IFT)
Starts a subconditional assembly block to be assembled if
the condition test specified when the conditional assembly
block was entered was true. The subconditional assembly block that
starts with .IF_TRUE continues up to the next subconditional
assembly directive or to the end of the conditional assembly block.
.IF_TRUE
The alternate form of .IF_TRUE is .IFT.
15.28 - .IF TRUE FALSE (.IFTF)
Starts a subconditional assembly block to be assembled regardless
of whether the condition test specified when the conditional
assembly block was entered was true or false. The
subconditional assembly block that starts with .IF_TRUE_FALSE
continues up to the next subconditional assembly directive or to
the end of the conditional assembly block.
.IF_TRUE_FALSE
The alternate form of .IF_TRUE_FALSE is .IFTF.
15.29 - .IIF
Provides a means of writing a one-line conditional assembly block.
.IIF condition [,]argument(s), statement
condition
One of the legal condition tests defined for conditional
assembly blocks. The condition must be separated from the
arguments by a comma, space, or tab. If the first argument can
be a blank, the condition must be separated from the arguments
with a comma.
argument(s)
An expression or symbolic argument associated with the
immediate conditional assembly block directive.
statement
The statement to be assembled if the condition is satisfied.
The condition to be tested and the conditional assembly block
are expressed completely within the line containing the
directive. No terminating .ENDC statement is required.
15.30 - .IRP
Replaces a formal argument with successive actual arguments
specified in an argument list.
.IRP symbol,<argument list>
...
range
...
.ENDR
symbol
A formal argument that is successively replaced with the
specified actual arguments enclosed in angle brackets. If no
formal argument is specified, the assembler displays an error
message.
<argument list>
A list of actual arguments enclosed in angle brackets and used
in expanding the indefinite repeat range. An actual
argument can consist of one or more characters. Multiple
arguments must be separated by a legal separator (comma, space,
or tab). If no actual arguments are specified, no action is taken.
range
The block of source text to be repeated once for each occurrence
of an actual argument in the list. The range can contain
macro definitions and repeat ranges. .MEXIT is legal within the
range.
This replacement process occurs during the expansion of
the indefinite repeat block range.
15.31 - .IRPC
Similar to .IRP except that .IRPC permits single-character
substitution rather than argument substitution.
.IRPC symbol, <string>
...
range
...
.ENDR
symbol
A formal argument that is successively replaced with the
specified characters enclosed in angle brackets. If no formal
argument is specified, the assembler displays an error message.
<string>
A sequence of characters enclosed in angle brackets and used in
the expansion of the indefinite repeat range. Although the
angle brackets are required only when the string contains
separating characters, their use is recommended for legibility.
range
The block of source text to be repeated once for each occurrence of
a character in the list. The range can contain macro definitions
and repeat ranges.
On each iteration of the indefinite repeat range, the formal
argument is replaced with each successive character in the
specified string. The .ENDR directive specifies the end of the
range.
15.32 - .LIBRARY
Adds a name to the macro library list that is searched whenever
a .MCALL or an undefined opcode is encountered.
.LIBRARY macro-library-name
macro-library-name
A delimited string that is the file specification of a macro
library.
The libraries are searched in the reverse order in which they
were specified to the assembler.
If you omit any information from the macro-library-name
argument, default values are assumed.
15.33 - .LINK
Allows you to include Linker option records in an object
module produced by VAX MACRO. The qualifiers for the .LINK
directive perform functions similar to the functions performed
by the same qualifiers for the DCL command LINK.
.LINK "file-spec" [/qualifier[=(module-name[,...])],...]
file-spec[,...]
A delimited string that specifies one or more input files. The
input files can be object modules to be linked, or shareable
images to be included in the output image. Input files can also
be libraries containing external references or specific modules
for inclusion in the output image. The Linker will search the
libraries for the external references. If you specify multiple
input files, separate the file specifications with commas (,).
If you do not specify a file type in an input file specification,
the Linker supplies default file types, based on the nature of the
file. All object modules are assumed to have file types of OBJ.
/INCLUDE=(module-name[,...])
Indicates that the associated input file is an object library
or shareable image library, and that only the module names
specified are to be unconditionally included as input to the
Linker. At least one module name must be specified. If you
specify more than one module name, separate the names with
commas and enclose the list in parentheses.
/LIBRARY
Indicates that the associated input file is a library to be
searched for modules to resolve any undefined symbols in the input
files.
/SELECTIVE_SEARCH
Directs the Linker to add to its symbol table only those
global symbols that are defined in the specified file and are
currently unresolved. If /SELECTIVE_SEARCH is not specified,
the Linker includes all symbols from that file in its global
symbol table.
/SHAREABLE
Requests that the Linker include a shareable image file. No
wildcard characters are allowed in the file specification.
15.34 - .LONG
Generates successive longwords (four bytes) of data in the
object module.
.LONG expression1[expression2], ...
expression1
An expression that specifies the value to be stored.
[expression2]
An expression that specifies the number of times the value
is repeated. The square brackets are required.
Each expression in the list must have a value that can be
represented in 32 bits.
15.35 - .MACRO
Begins the definition of a macro.
.MACRO macro-name [formal-argument-list]
...
range
...
.ENDM [macro name]
macro-name
The name of the macro to be defined; this name can be any
legal symbol up to 31 characters long.
formal-argument-list
The symbols, separated by commas, to be replaced by the
actual arguments in the macro call.
range
The source text to be included in the macro expansion.
If the name specified is the same as the name of a previously
defined macro, the previous definition is deleted and replaced
with the new one. The .MACRO directive is followed by the
source text to be included in the macro expansion. The .ENDM
directive specifies the end of the range.
If a macro has the same name as a VAX opcode, the macro is
used instead of the instruction. This feature allows you to
temporarily redefine an opcode.
If a macro has the same name as a VAX opcode and is in a
macro library, you must use the .MCALL directive to define
the macro. Otherwise, because the symbol is already defined (as the
opcode), the assembler will not search the macro libraries.
15.36 - .MASK
Reserves a word for a register save mask for a transfer vector.
.MASK symbol[,expression]
symbol
A symbol defined in an .ENTRY directive.
expression
A register save mask.
If .MASK does not contain an expression, the assembler directs
the Linker to copy the register save mask specified in .ENTRY to
the word reserved by .MASK.
If .MASK contains an expression, the assembler directs the Linker
to combine this expression with the register save mask
specified in .ENTRY and store the result in the word reserved
by .MASK. The Linker performs an inclusive OR operation to
combine the mask in the entry point and the value of the
expression. Consequently, a register specified in either .ENTRY
or .MASK will be included in the combined mask.
15.37 - .MCALL
Specifies the names of the system and/or user-defined macros that
are required to assemble the source program but are not defined
in the source file.
.MCALL macro-name-list
macro-name-list
A list of macros to be defined for this assembly. Separate the
macro names with commas.
You must use .MCALL when a macro has the same name as an opcode.
15.38 - .MDELETE
Deletes the definitions of specified macros.
.MDELETE macro-name-list
macro-name-list
A list of macros whose definitions are to be deleted. Separate
the names with commas.
.MDELETE completely deletes the macro, freeing memory as
necessary. Macro redefinition with .MACRO merely redefines the
macro.
15.39 - .MEXIT
Terminates a macro expansion before the end of the macro.
.MEXIT
Termination is the same as if .ENDM were encountered. .MEXIT is
useful in conditional expansion of macros because it bypasses
the complexities of nested conditional directives and alternate
assembly paths.
15.40 - .NARG
Counts all the positional arguments specified in the macro
call, including null arguments (specified by adjacent commas).
.NARG symbol
symbol
A symbol that is assigned a value equal to the number of arguments
in the macro call.
15.41 - .NCHR
Determines the number of characters in a specified character
string.
.NCHR symbol,<string>
symbol
A symbol that is assigned a value equal to the number of
characters in the specified character string.
<string>
A sequence of printable characters. Delimit the character
string with angle brackets (or a character preceded by a
circumflex) only if the specified character string contains a
legal separator (comma, space, and/or tab) or a semicolon.
It can appear anywhere in a VAX MACRO program and is useful
in calculating the length of macro arguments.
15.42 - .NOCROSS
Controls which symbols are included in the cross-reference listing.
.CROSS [symbol-list] (Default)
.NOCROSS [symbol-list]
symbol-list
A list of legal symbol names separated by commas.
When you specify the /CROSS_REFERENCE qualifier in the MACRO
command, VAX MACRO produces a cross-reference listing. The
directives have an effect only if /CROSS_REFERENCE was specified in
the MACRO command.
Using .NOCROSS with a symbol list disables the
cross-reference listing for the listed symbols only. Using .CROSS
with a symbol list enables or reenables the cross-reference
listing of the listed symbols.
15.43 - .NTYPE
Determines the addressing mode of the specified operand.
.NTYPE symbol,operand
symbol
Any legal VAX MACRO symbol. This symbol is assigned a value equal
to the 8- or 16-bit addressing mode of the operand argument
that follows.
operand
Any legal address expression, as you use it with an opcode. If
no argument is specified, 0 is assumed.
The value of the symbol is set to the specified addressing mode.
In most cases, an 8-bit (1-byte) value is returned. Bits 0
through 3 specify the register associated with the mode, and bits 4
through 7 specify the addressing mode. Literal mode is
indicated by a 0 in bits 4 through 7, instead of the values 0
through 3. Mode 1 indicates an immediate mode operand, mode
2 indicates an absolute mode operand, and mode 3 indicates a
general mode operand.
For indexed addressing mode, a 16-bit (2-byte) value is
returned. The high-order byte contains the addressing mode of the
base operand specifier and the low-order byte contains the
addressing mode of the primary operand (the index register).
15.44 - .OCTA
Generates 128 bits (16 bytes) of binary data.
.OCTA literal
.OCTA symbol
literal
Any constant value. This value can be preceded by ^O, ^B, ^X, or
^D to specify the radix as octal, binary, hexadecimal, or
decimal, respectively; or it can be preceded by ^A to specify
ASCII text. Decimal is the default radix.
symbol
A symbol defined elsewhere in the program. This symbol results in
a sign-extended, 32-bit value being stored in an octaword.
It does not evaluate expressions and that it accepts only one
value.
15.45 - .ODD
Ensures that the current value of the location counter is odd
by adding 1 if the current value is even. If the current
value is already odd, no action is taken.
.ODD
15.46 - .OPDEF
Defines an opcode, which is inserted into a user-defined
opcode table.
.OPDEF opcode value,operand-descriptor-list
opcode
An ASCII string specifying the name of the opcode. The string can
be up to 31 characters long and can contain the letters A through
Z, the digits 0 through 9, and the special characters underline,
(_), dollar sign ($), and period (.). The string should not
start with a digit and should not be surrounded by delimiters.
value
An expression that specifies the value of the opcode. The
expression must be absolute and must not contain any undefined
values. The value of the expression must be in the range of 0
through decimal 65,535 (hexadecimal FFFF), but you cannot use the
values 252 through 255 because the architecture specifies these as
the start of a 2-byte opcode. The expression is represented as
follows:
if 0 < expression < 251 expression is a 1-byte opcode.
if expression > 255 expression bits 7:0 are the first
byte of the opcode and expression
bits 15:8 are the second byte of
the opcode.
operand-descriptor-list
A list of operand descriptors that specifies the number of
operands and the type of each. Up to 16 operand descriptors are
allowed in the list.
15.47 - .PACKED
Generates packed decimal data, two digits per byte.
.PACKED decimal-string[,symbol]
decimal-string
A decimal number from 0 through 31 digits long with an optional
sign. Digits can be in the range of 0 through 9.
symbol
An optional symbol that is assigned a value equivalent to the
number of decimal digits in the string. The sign is not counted as
a digit.
15.48 - .PAGE
Forces a new page in the listing.
.PAGE
VAX MACRO ignores .PAGE in a macro definition. The paging
operation is performed only during macro expansion.
15.49 - .PRINT
Causes the assembler to display an informational message.
.PRINT [expression] ;comment
expression
An expression whose value is displayed when .PRINT is
encountered during assembly.
;comment
A comment that is displayed when .PRINT is encountered
during assembly. The comment must be preceded by a semicolon.
If .PRINT is included in a macro library, end the comment with
an additional semicolon. If you omit the semicolon, the comment
will be stripped from the directive and will not be displayed when
the macro is called.
15.50 - .PSECT
Defines a program section and its attributes and refers to a
program section once it is defined.
.PSECT [program-section-name[,argument-list]]
program-section-name
The name of the program section. This name can be up to
31 characters long and can contain any alphanumeric character
and the special characters underline (_), dollar sign ($), and
period (.). The first character must not be a digit.
argument-list
A list containing the program section attributes and the
program section alignment. Program sections are aligned when you
specify an integer in the range of 0 through 9 or one of the
five keywords; byte, word, long, quad, or page. If you
specify an integer, the program section is linked to begin at the
next virtual address, which is a multiple of 2 raised to the
power of the integer. If you specify a keyword, the program
section is linked to begin at the next virtual address (a
multiple of the specified values.) BYTE is the default.
Program Section Attributes:
Attribute Function
ABS Absolute
CON Concatenate (Default)
EXE Executable (Default)
GBL Global
LCL Local (Default)
LIB Library Segment
NOEXE Not Executable
NOPIC Non-Position-Independent Content (Default)
NORD Nonreadable
NOSHR No Share (Default)
NOVEC Nonvector-Containing (Default)
NOWRT Nonwriteable
OVR Overlay
PIC Position-Independent Content
RD Readable (Default)
REL Relocatable (Default)
SHR Share
USR User Segment
VEC Vector-Containing
WRT Write (Default)
The assembler automatically defines two program sections:
the absolute program section and the unnamed (or blank) program
section.
Any symbol definitions that appear before any instruction, data,
or .PSECT directive are placed in the absolute program section.
15.51 - .QUAD
Generates 64 bits (eight bytes) of binary data.
.QUAD literal
.QUAD symbol
literal
Any constant value. This value can be preceded by ^O, ^B, ^X, or
^D to specify the radix as octal, binary, hexadecimal, or
decimal, respectively; or it can be preceded by ^A to specify the
ASCII text operator. Decimal is the default radix.
symbol
A symbol defined elsewhere in the program. This symbol results in
a sign-extended, 32-bit value being stored in a quadword.
It does not evaluate expressions and that it accepts only one
value. It does not accept a list.
.REFn
Operand generation directives that you can use in macros to
define new opcodes.
.REF1 byte operand
.REF2 word operand
.REF4 longword operand
.REF8 quadword operand
.REF16 octaword context
The .REFn directives are provided for compatibility with VAX
MACRO V1.0.
15.52 - .REPEAT (.REPT)
Repeats a block of code a specified number of times, in line with
other source code. The .ENDR directive specifies the end of the
range.
.REPEAT expression
...
range
...
.ENDR
expression
An expression whose value controls the number of times the range
is to be assembled within the program. When the expression is less
than or equal to 0, the repeat block is not assembled. The
expression must be absolute and must not contain any undefined
symbols.
range
The source text to be repeated the number of times specified by
the value of the expression. The repeat block can contain
macro definitions, indefinite repeat blocks, or other repeat
blocks.
15.53 - .RESTORE PSECT (.RESTORE)
Retrieves the program section from the top of the program
section context stack, an internal stack in the assembler.
.RESTORE_PSECT
When .RESTORE_PSECT retrieves a program section, it restores
the current location counter to the value it had when the program
section was saved. The local label block is also restored if it
was saved when the program section was saved.
The alternate form of .RESTORE_PSECT is .RESTORE.
15.54 - .SAVE PSECT (.SAVE)
Stores the current program section context on the top of the
program section context stack, an internal assembler stack.
.SAVE_PSECT [LOCAL_BLOCK]
LOCAL_BLOCK
An optional keyword that specifies that the current local label is
to be saved with the program section context.
It leaves the current program section context in effect. The
program section context stack can hold 31 entries. Each entry
includes the value of the current location counter and the maximum
value assigned to the location counter in the current program
section.
The alternate form of .SAVE_PSECT is .SAVE.
15.55 - .SHOW .NOSHOW
Specify listing control options in the source text of a program.
.SHOW [argument-list]
.NOSHOW [argument-list]
argument-list
One or more of the optional symbolic arguments; BINARY,
CALLS, CONDITIONALS, DEFINITIONS, and EXPANSIONS. You can use
either the long form or the short form of the arguments. You
can use each argument alone or in combination with other
arguments, but you must separate them by commas, tabs, or spaces.
You can use .SHOW and .NOSHOW with or without an argument list.
15.56 - .SIGNED BYTE
Equivalent to .BYTE, except that VAX MACRO indicates that the data
is signed in the object module.
.SIGNED_BYTE expression1[expression2], ...
An expression or list of expressions separated by commas. You
have the option of following each expression with a repetition
factor delimited by square brackets.
expression1
An expression that specifies the value to be stored. The value
must be in the range -128 through +127.
[expression2]
An expression that specifies the number of times the value will
be repeated. The expression must not contain any undefined
symbols and must be an absolute expression. The square brackets
are required.
.SIGNED_WORD
Equivalent to .WORD except that the assembler indicates that the
data is signed in the object module.
.SIGNED_WORD expression1[expression2], ...
An expression or list of expressions separated by commas. You
have the option of following each expression with a repetition
factor delimited by square brackets.
expression1
An expression that specifies the value to be stored. The value
must be in the range -32,768 through +32,767.
[expression2]
An expression that specifies the number of times the value will
be repeated. The expression must not contain any undefined
symbols and must be an absolute expression. The square brackets
are required.
.SUBTITLE_(.SBTTL)
Causes the assembler to print the line of text, represented by
the comment-string, in the table of contents.
.SUBTITLE comment-string
comment-string
An ASCII string from 1 to 40 characters long; excess characters
are truncated.
The assembler also prints the line of text as the subtitle on
the second line of each assembly listing page. This subtitle
text is printed on each page until altered by a subsequent
.SUBTITLE directive in the program.
The alternate form of .SUBTITLE is .SBTTL.
15.57 - .TITLE
Assigns a name to the object module.
.TITLE module-name comment-string
module-name
An identifier from 1 to 31 characters long.
comment-string
An ASCII string from 1 to 40 characters long; excess characters
are truncated.
The module name specified with .TITLE bears no relationship to
the file specification of the object module, as specified in
the VAX MACRO command line. The object module name appears in
the Linker load map, and is also the module name that the debugger
and librarian recognize. There are three display message
directives, .ERROR, .PRINT, and .WARN. They can be used to
display information indicating that a macro call contains an error
or illegal set of conditions.
15.58 - .TRANSFER
Redefines a global symbol for use in a shareable image.
.TRANSFER symbol
symbol
A global symbol that is an entry point in a procedure or routine.
The Linker redefines the symbol as the value of the location
counter at the .TRANSFER directive after a shareable image is
linked.
15.59 - .WARN
Causes the assembler to display a warning message on the terminal
or in the batch log file, and in the listing file.
.WARN [expression] ;comment
expression
An expression whose value is displayed when .WARN is
encountered during assembly.
;comment
A comment that is displayed when .WARN is encountered
during assembly. The comment must be preceded by a semicolon.
If .WARN is included in a macro library, end the comment with
an additional semicolon. If you omit the semicolon, the comment
will be stripped from the directive and will not be displayed when
the macro is called.
15.60 - .WEAK
Specifies symbols that are either defined externally in
another module or defined globally in the current module.
.WEAK symbol-list
symbol-list
A list of legal symbols separated by commas.
When .WEAK specifies a symbol that is not defined in the
current module, the symbol is externally defined. If the Linker
finds the symbol's definition in another module, it uses that
definition. If the Linker does not find an external
definition, the symbol has a value of 0 and the Linker does not
report an error. The Linker does not search a library for the
symbol, but if a module brought in from a library for another
reason contains the symbol definition, the Linker uses it.
When .WEAK specifies a symbol that is defined in the current
module, the symbol is considered to be globally defined.
However, if this module is inserted in an object library, this
symbol is not inserted in the library's symbol table.
Consequently, searching the library at link time to resolve this
symbol does not cause the module to be included.
15.61 - .WORD
Generates successive words (two bytes) of data in the object
module.
.WORD expression1[expression2], ...
One or more expressions separated by commas. You have the option
of following each expression by a repetition factor delimited
with square brackets.
expression1
An expression that specifies the value to be stored.
[expression2]
An expression that specifies the number of times the value will
be repeated. The expression must not contain any undefined
symbols and must be an absolute expression. The square brackets
are required.
| 16 - Instructions |
16.1 - ACBx
Purpose: Add compare and branch - maintain loop count
and loop
Format: opcode limit.rx,add.rx,index.rx,displ.bw
Operation: index = index + add; if {{add GEQ 0} AND {index LEQ
limit}} OR {{add LSS 0} AND {index GEQ limit}} then
PC = PC + SEXT (displ)
C. Codes: N = {index LSS 0}, Z = {index EQL 0}, C = C,
V = {integer or floating overflow}
Exceptions: Integer or floating overflow, floating
underflow, reserved operand
Opcodes: 9D ACBB Add compare and branch byte
3D ACBW Add compare and branch word
F1 ACBL Add compare and branch long
4F ACBF Add compare and branch F_floating
6F ACBD Add compare and branch D_floating
4FFD ACBG Add compare and branch G_floating
6FFD ACBH Add compare and branch H_floating
Description: add is added to index and index is replaced by the
result. index is compared with limit. If add is
greater than or equal to zero and the comparison is
less than or equal to zero or if add is less than
zero and the comparison is greater than or equal,
the branch is taken. The condition codes are
unpredictable on a reserved operand fault.
16.2 - ADAWI
Purpose: Add aligned word interlocked - maintain operating
system resource usage counts
Format: opcode add.rw,sum.mw
Operation: tmp = add; {set interlock}; sum = sum + tmp;
{release interlock}
C. Codes: N = {sum LSS 0}, Z = {sum EQL 0},
V = {integer overflow}, C = {carry from MSB}
Exceptions: Reserved operand fault, integer overflow
Opcode: 58 ADAWI Add aligned word interlocked
Description: The add operand is added to sum and sum is replaced
by the result. The operation is interlocked against
ADAWI operations by other processors or devices in
the system. The destination must be aligned on a
word boundary, i.e. bit zero of sum's address must
be zero. A reserved operand fault is taken if it
is not.
16.3 - ADDxx
Purpose: Perform arithmetic addition
Format: opcode add.rx,sum.mx ;2 operand
opcode add1.rx,add2.rx,sum.wx ;3 operand
Operation: sum = sum + add ;2 operand
sum = add1 + add2 ;3 operand
C. Codes: N = {sum LSS 0}, Z = {sum EQL 0}, V = {overflow},
C = 0 (floating), C = {carry from MSB} (integer)
Exceptions: Integer or floating overflow, floating
underflow, reserved operand
Opcodes: 80 ADDB2 Add byte 2 operand
81 ADDB3 Add byte 3 operand
A0 ADDW2 Add word 2 operand
A1 ADDW3 Add word 3 operand
C0 ADDL2 Add long 2 operand
C1 ADDL3 Add long 3 operand
40 ADDF2 Add F_floating 2 operand
41 ADDF3 Add F_floating 3 operand
60 ADDD2 Add D_floating 2 operand
61 ADDD3 Add D_floating 3 operand
40FD ADDG2 Add G_floating 2 operand
41FD ADDG3 Add G_floating 3 operand
60FD ADDH2 Add H_floating 2 operand
61FD ADDH3 Add H_floating 3 operand
16.4 - ADDPx
Purpose: Add one packed decimal string to another
Format: opcode addlen.rw,addaddr.ab,
sumlen.rw, sumaddr.ab ;4 operand
opcode add1len.rw,add1addr.ab,add2len.rw,
add2addr.ab,sumlen.rw,sumaddr.ab ;6 operand
Operation: {sum string} = {sum string} +
{add string} ;4 operand
{sum string} = {add1 string} +
{add2 string} ;6 operand
C. Codes: N = {{sum string} LSS 0}, Z = {{sum string} EQL 0},
V = {decimal overflow}, C = 0
Exceptions: Reserved operand, decimal overflow
Opcodes: 80 ADDP4 Add packed 4 operand
81 ADDP6 Add packed 6 operand
Description: In 4 operand format, the addend string as specified
by addlen and addaddr is added to the sum string
specified by sumlen and sumaddr, and sum is replaced
by the result. In 6 operand format, the addend 1
string specified by add1len and add1addr is added to
the addend 2 string specified by add2len and
add2addr, and the sum string is replaced by the
result.
Notes: After execution of ADDP4:
R0 = 0
R1 = address of the byte containing the
most-significant digit of the addend string
R2 = 0
R3 = address of the byte containing the
most-significant digit of the sum string
After execution of ADDP6:
R0 = 0
R1 = address of the byte containing the
most-significant digit of the addend 1 string
R2 = 0
R3 = address of the byte containing the
most-significant digit of the addend 2 string
R4 = 0
R5 = address of the byte containing the
most-significant digit of the sum string
16.5 - ADWC
Purpose: Add with carry - perform extended-precision addition
Format: opcode add.rl,sum.ml
Operation: sum = sum + add + C
C. Codes: N = {sum LSS 0}, Z = {sum EQL 0},
V = {integer overflow}, C = {carry from MSB}
Exceptions: Integer overflow
Opcode: D8 ADWC Add with carry
16.6 - AOBLxx
Purpose: Add one and branch - increment integer loop count
and loop
Format: opcode limit.rl,index.ml,displ.bb
Operation: index = index + 1; if {{AOBLSS} and {index LSS
limit}} or {{AOBLEQ} and {index LEQ limit}} then
PC = PC + SEXT (displ)
C. Codes: N = {index LSS 0}, Z = {index EQL 0},
V = {integer overflow}, C = C
Exceptions: Integer overflow
Opcodes: F2 AOBLSS Add one, branch less than
F3 AOBLEQ Add one, branch less or equal
16.7 - ASHx
Purpose: Shift of integer
Format: opcode cnt.rb,src.rx,dst.wx
Operation: dst = src shifted cnt bits
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0},
V = {integer overflow}, C = 0
Exceptions: Integer overflow
Opcodes: 78 ASHL Arithmetic shift long
79 ASHQ Arithmetic shift quad
Description: src is arithmetically shifted by the number of bits
specified by cnt and the result is placed in dst.
Positive cnt shifts left bringing 0's into the LSB.
Negative cnt shifts right bringing copies of the MSB
into the MSB. Zero cnt copies dst to src unaffected.
ASHP
Purpose: Arithmetic shift and round packed - scale numeric
content of a packed decimal string by a power of ten
Format: opcode cnt.rb,srclen.rw,srcaddr.ab,round.rb,
dstlen.rw,dstaddr.ab
Operation: {dst string} = {{src string} + {round <3:0>*
(10**(-cnt-1))}} * (10**cnt);
C. Codes: N = {{dst string} LSS 0}, Z = {{dst string} EQL 0},
V = {decimal overflow}, C = 0
Exceptions: Reserved operand, decimal overflow
Opcodes: F8 ASHP Arithmetic shift packed
Description: src as specified by srclen and srcaddr is scaled by
a power of 10 specified by cnt. dst is replaced by
the result. A positive cnt effectively multiplies,
a negative cnt effectively divides and a zero cnt
just moves src to dst while affecting the condition
codes. If cnt is negative the result is rounded
using round.
Notes: After execution:
R0 = 0
R1 = address of the byte containing the
most-significant digit of the source string
R2 = 0
R3 = address of the byte containing the
most-significant digit of the destination string
16.8 - Bxxxx
Purpose: Branch - test condition code(s)
Format: opcode displ.bb
Operation: if {condition} then PC = {PC + SEXT (displ)}
C. Codes: Not affected
Exceptions: None
Opcodes: 12 {Z EQL 0} BNEQ Branch not equal (s)
BNEQU Branch not equal (u)
13 {Z EQL 1} BEQL Branch equal (s)
BEQLU Branch equal (u)
14 {(N OR Z) EQL 0} BGTR Branch greater than (s)
15 {(N OR Z) EQL 1} BLEQ Branch less or equal (s)
18 {N EQL 0} BGEQ Branch greater, equal (s)
19 {N EQL 1} BLSS Branch less than (s)
1A {(C OR Z) EQL 0} BGTRU Branch greater than (u)
1B {(C OR Z) EQL 1} BLEQU Branch less or equal (u)
1C {V EQL 0} BVC Branch overflow clear
1D {V EQL 1} BVS Branch overflow set
1E {C EQL 0} BGEQU Branch greater, equal (u)
BCC Branch carry clear
1F {C EQL 1} BLSSU Branch less than (u)
BCS Branch carry set
legend: s - signed, u - unsigned
Description: The condition codes are tested and if the condition
indicated by the instruction is met, the sign
extended branch displacement is added to the PC.
16.9 - BBx
Purpose: Branch on bit - test selected bit
Format: opcode pos.rl,base.ab,displ.bb
Operation: teststate = {if {BBS} then 1 else 0}; if {FIELD
(pos, 1, base) EQL teststate} then PC = {PC +
SEXT (displ)}
C. Codes: Unaffected
Exceptions: Reserved operand
Opcodes: E0 BBS Branch on bit set
E1 BBC Branch on bit clear
Description: The single bit field specified by pos and base is
tested. If it is in the test state indicated by the
instruction, the sign extended branch displacement
is added to PC and the result is placed in PC.
16.10 - BBxx
Purpose: Branch on bit - test and modify selected bit
Format: opcode pos.rl,base.ab,displ.bb
Operation: teststate = if {BBSS or BBSC} then 1 else 0;
newstate = if {BBSS or BBCS} then 1 else 0; temp =
FIELD (pos, 1, base); FIELD (pos, 1, base) =
newstate; if temp EQL teststate then PC = {PC +
SEXT (displ)}
C. Codes: Unaffected
Exceptions: Reserved operand
Opcodes: E2 BBSS Branch on bit set and set
E3 BBCS Branch on bit clear and set
E4 BBSC Branch on bit set and clear
E5 BBCC Branch on bit clear and clear
Description: The single bit field specified by pos and base is
tested. If it is in the test state indicated by the
instruction, the sign extended branch displacement
is added to PC and placed in PC. Regardless of
whether the branch is taken or not, the tested bit
is put in the new state as indicated by the
instruction.
16.11 - BBxxI
Purpose: Branch on bit interlocked - test and modify selected
bit under memory interlock.
Format: opcode pos.rl,base.ab,displ.bb
Operation: teststate = if {BBSSI} then 1 else 0; newstate =
teststate; {set interlock}; temp = FIELD (pos,
1, base); FIELD (pos, 1, base) = newstate; {release
interlock}; if temp EQL teststate then PC =
{PC + SEXT(displ)}
C. Codes: Not affected
Exceptions: Reserved operand
Opcodes: E6 BBSSI Branch bit set, set interlocked
E7 BBCCI Branch bit clear, clear interlocked
Description: The single bit field specified by pos and base is
tested. If it is in the state indicated by the
instruction, the sign extended branch displacement
displ is added to PC. The bit is set to the state
indicated by the instruction. The operation is
interlocked against other processors or devices in
the system.
16.12 - BICxx
Purpose: Bit clear - perform complemented AND of two integers
Format: opcode mask.rx,dst.mx ;2 operand
opcode mask.rx,src.rx,dst.rx ;3 operand
Operation: dst = dst AND {NOT mask} ;2 operand
dst = src AND {NOT mask} ;3 operand
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C
Exceptions: None
Opcodes: 8A BICB2 Bit clear byte, 2 operand
8B BICB3 Bit clear byte, 3 operand
AA BICW2 Bit clear word, 2 operand
AB BICW3 Bit clear word, 3 operand
CA BICL2 Bit clear long, 2 operand
CB BICL3 Bit clear long, 3 operand
Description: In 2 operand format, dst is ANDed with the ones
complement of mask and dst is replaced by the result.
In 3 operand format, src is ANDed with the ones
complement of mask and dst is replaced by the result.
16.13 - BICPSW
Purpose: Bit clear PSW - clear trap enables
Format: opcode mask.rw
Operation: PSW = {PSW AND {NOT mask}}
C. Codes: N = N AND {NOT mask<3>}; Z = Z AND {NOT mask<2>}
V = V AND {NOT mask<1>}; C = C AND {NOT mask<0>}
Exceptions: Reserved operand
Opcode: B8 BICPSW Bit clear PSW
Description: The PSW is ANDed with the complement of mask and PSW
is replaced by the result.
16.14 - BISxx
Purpose: Bit set - perform logical inclusive OR of two
integers
Format: opcode mask.rx,dst.mx ;2 operand
opcode mask.rx,src.rx,dst.rx ;3 operand
Operation: dst = dst OR mask ;2 operand
dst = src OR mask ;3 operand
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C
Exceptions: None
Opcodes: 88 BISB2 Bit set byte, 2 operand
89 BISB3 Bit set byte, 3 operand
A8 BISW2 Bit set word, 2 operand
A9 BISW3 Bit set word, 3 operand
C8 BISL2 Bit set long, 2 operand
C9 BISL3 Bit set long, 3 operand
Description: In 2 operand format, dst is ORed with mask and dst
is replaced by the result. In 3 operand format, src
is ORed with mask and dst is replaced by the result.
16.15 - BISPSW
Purpose: Bit set PSW - set trap enables
Format: opcode mask.rw
Operation: PSW = PSW OR mask
C. Codes: N = N OR mask<3>; Z = Z OR mask<2>
V = V OR mask<1>; C = C OR mask<0>
Exceptions: Reserved operand
Opcode: B8 BISPSW Bit set PSW
Description: The PSW is ORed with mask and PSW is replaced by the
result.
16.16 - BITx
Purpose: Test a set of bits for all zero
Format: opcode mask.rx,src.rx
Operation: tmp = {src AND mask}
C. Codes: N = {tmp LSS 0}, Z = {tmp EQL 0}, V = 0, C = C
Exceptions: None
Opcodes: 93 BITB Bit test byte
B3 BITW Bit test word
D3 BITL Bit test long
Description: mask is ANDed with src. Both operands are unaffected.
The only action is to affect the condition codes.
16.17 - BLBx
Purpose: Branch on low bit - test bit
Format: opcode src.rl,displ.bb
Operation: teststate = if {BLBS} then 1 else 0; if src<0>
EQL teststate then PC = {PC + SEXT (displ)}
C. Codes: Not affected
Exceptions: None
Opcodes: E8 BLBS Branch on low bit set
E9 BLBC Branch on low bit clear
Description: The LSB of src is tested and if it is equal to the
test state indicated by the instruction, the branch
is taken.
16.18 - BPT
Purpose: Breakpoint trap - stop for debugging
Format: opcode
Operation: PSL<TP> = 0; {breakpoint fault}
C. Codes: N = 0, Z = 0, V = 0, C = 0
Exceptions: None
Opcode: 03 BPT Breakpoint fault
Description: This instruction is used, together with the T-bit,
to implement debugging facilities.
16.19 - BRx
Purpose: Transfer control (branch)
Format: opcode displ.bx
Operation: PC = PC + SEXT (displ)
C. Codes: Not affected
Exceptions: None
Opcodes: 11 BRB Branch with byte displacement
31 BRW Branch with word displacement
16.20 - BSBx
Purpose: Branch to subroutine - transfer control to subroutine
Format: opcode displ.bx
Operation: -(SP) = PC; PC = {PC + SEXT (displ)}
C. Codes: Not affected
Exceptions: None
Opcodes: 10 BSBB Branch to sub., byte displ.
30 BSBW Branch to sub., word displ.
Description: PC is pushed onto the stack as a longword and the
branch is taken.
16.21 - BUGx
Purpose: bugcheck
Operation: {fault to report error}
C. Codes: not affected
Exceptions: Reserved instruction
Opcodes: FEFF BUGW Bugcheck with word message identifier
FDFF BUGL Bugcheck with longword message id
Description: The hardware treats these opcodes as RESERVED to
Digital and faults. The VAX/VMS operating system
treats these as requests to report software-detected
errors. The in-line message identifier is zero
extended to a longword and interpreted as a
condition value. If the process is privileged to
report bugs, a log entry is made. If the process is
not privileged, a reserved instruction is signalled.
16.22 - CALLG
Purpose: Call with general argument list - invoke a procedure
with actual arguments from anywhere in memory
Format: opcode arglist.ab,dst.ab
Operation: {align stack}; {create stack frame}; {set arithmetic
trap enables}; {set new values of AP, FP, PC}
C. Codes: N = 0, Z = 0, V = 0, C = 0
Exceptions: Reserved operand
Opcode: FA CALLG Call proc., general arglist
Description: SP is saved in a temporary (tmp) and then bits 1:0
of SP are cleared so the stack is longword aligned.
The procedure entry mask (pointed to by dst) is
scanned from bit 11 to bit 0 and the contents of the
registers whose numbers correspond to set bits in
the mask are pushed on the stack as longwords. Next
AP, FP and the current PC are pushed onto the stack
as longwords. The condition codes are cleared. A
longword containing the saved two low bits of SP in
bits 31:30 (tmp), 0 in bits 29:28, the low 12 bits
of the entry mask in bits 27:16 and the PSW in bits
15:0 with T cleared is pushed on the stack. A
longword 0 is pushed on the stack (for the condition
handler). FP is replaced by SP, AP is replaced by
arglist. The trap enables in PSW are set to a known
state. Integer and decimal overflow are set
according to bits 14 and 15 of the entry mask
respectively. The floating underflow bit is cleared
and the T-bit is unaffected. PC is replaced by dst +
2, skipping the entry mask and transferring control
to the byte beyond the mask.
16.23 - CALLS
Purpose: Call with stack argument list - invoke a procedure
with actual arguments on the stack
Format: opcode numarg.rl,dst.ab
Operation: {push arg count}; {align stack}; {create stack
frame}; {set arithmetic trap enables}; {set new
values of AP, FP, PC}
C. Codes: N = 0, Z = 0, V = 0, C = 0
Exceptions: Reserved operand
Opcode: FB CALLS Call proc. with stack arglist
Description: numarg is pushed on the stack as a longword (byte 0
contains the number of arguments, the high-order 24
bits are used by Digital software), SP is saved in a
temporary (tmp) and then bits 1:0 of SP are cleared
so the stack is longword aligned. The procedure
entry mask (pointed to by dst) is scanned from bit
11 to bit 0 and the contents of the registers whose
numbers correspond to set bits in the mask are
pushed on the stack as longwords. AP, FP and the
current PC are pushed onto the stack as longwords.
The condition codes are cleared. A longword
containing the saved two low bits of SP in bits
31:30 (tmp), 1 in bit 29, a 0 in bit 28, the low 12
bits of the entry mask in bits 27:16 and the PSW in
bits 15:0 with T cleared is pushed on the stack. A
longword 0 is pushed on the stack (for the condition
handler address within the procedure). FP is
replaced by SP, AP is set to the saved SP (value of
SP after numarg was pushed. The trap enables in PSW
are set to a known state. Integer and decimal
overflow are set according to bits 14 and 15 of the
entry mask respectively. The floating underflow bit
is cleared and the T-bit is unaffected. PC is
replaced by dst + 2, skipping the entry mask and
transferring control to the byte beyond the mask.
16.24 - CASEx
Purpose: Perform multi-way branching depending on arithmetic
input
Format: opcode selector.rx,base.rx,limit.rx,disp[0].bw,...,
disp[limit].bw
Operation: tmp = selector - base; PC = PC + if tmp LEQU limit
then SEXT (displ[tmp]) else {2 + 2*ZEXT (limit)}
C. Codes: N = {tmp LSS limit}, Z = {tmp EQL limit}, V = 0,
C = {tmp LSSU limit}
Exceptions: None
Opcodes: 8F CASEB Case byte
AF CASEW Case word
CF CASEL Case long
Description: base is subtracted from selector and tmp is replaced
by the result. The temporary tmp is compared with
limit and if it is less than or equal (unsigned) a
branch displacement is selected by tmp added to PC
and PC is replaced by the result. Otherwise 2 *
(limit+1) is added to PC and the result is placed
in PC. This causes PC to be moved past the table of
branch displacements. The condition codes are always
affected by the comparison of tmp with limit.
16.25 - CHMx
Purpose: Request the services of more privileged software
by changing the process mode
Format: opcode code.rw
Operation: tmp1 = {mode selected by opcode (K = 0, E = 1,
S = 2, U = 3)}; tmp2 = MINU(tmp1,PSL<CUR_MOD>);
{maximize privilege}; tmp3 = SEXT(code); if
{PSL<IS> EQLU 1} then HALT; PSL<CUR_MOD>_SP = SP
tmp4 = tmp2_sp; PROBEW (from tmp4 - 1 to tmp4 - 12
with mode = tmp2); if {access violation} then
{initiate access violation fault}; if {translation
not valid} then {initiate translation not valid};
{initiate CHMx exception with new_mode = tmp2
and parameter = tmp3 using 40 + tmp1*4 as SCB offset
using tmp4 as the new SP and not storing SP again}
C. Codes: N = 0, Z = 0, V = 0, C = 0
Exceptions: Halt
Opcodes: BC CHMK Change mode to kernel
BD CHME Change mode to executive
BE CHMS Change mode to supervisor
BF CHMU Change mode to user
Description: Change mode instructions allow processes to change
their access mode in a controlled manner. The
instructions only increase privilege. A change in
mode also results in a change of stack pointers;
the old pointer is saved, the new pointer is loaded.
The PSL, PC and any code passed by the instruction
are pushed on the new stack. The code is sign
extended. The destination mode selected by the
opcode is used to select a vector from the System
Control Block. Software convention reserves the
negative code values to customers, positive
code values to Digital.
16.26 - CLRx
Purpose: Clear or zero a scalar quantity
Format: opcode dst.wx
Operation: dst = 0
C. Codes: N = 0, Z = 1, V = 0, C = 0
Exceptions: None
Opcodes: 94 CLRB Clear byte
B4 CLRW Clear word
D4 CLRL Clear long
7C CLRQ Clear quad
7CFD CLRO Clear octa
D4 CLRF Clear F_floating
7C CLRD Clear D_floating
7C CLRG Clear G_floating
7CFD CLRH Clear H_floating
Description: The destination operand is replaced by 0.
16.27 - CMPx
Purpose: Arithmetic comparison between two scalar quantities
Format: opcode scr1.rx,src2.rx
Operation: src1 - src2
C. Codes: N = {src1 LSS src2}, Z = {src1 EQL src2},
V = 0, C = {src1 LSSU src2} (integer),
C = 0 (floating)
Exceptions: None (integer), reserved operand (floating)
Opcodes: 91 CMPB Compare byte
B1 CMPW Compare word
D1 CMPL Compare long
51 CMPF Compare F_floating
71 CMPD Compare D_floating
51FD CMPG Compare G_floating
71FD CMPH Compare H_floating
Description: src1 is compared with src2. The only action is to
affect the condition codes.
16.28 - CMPCx
Purpose: Compare two character strings
Format: opcode len.rw,src1addr.ab,src2addr.ab ;3 operand
opcode src1len.rw,src1addr.ab,fill.rb ;5 operand
src2len.rw,src2addr.ab
Operation: {compare two strings with optional filling}
C. Codes: [final codes reflect last affecting of codes
in the operation.]
N = {{first byte} LSS {second byte}}, Z =
{{first byte} EQL {second byte}}, V = 0,
C = {{first byte} LSSU {second byte}}
Exceptions: None
Opcodes: 29 CMPC3 Compare character 3 operand
2D CMPC5 Compare character 5 operand
Description: In 3-operand format the bytes of string 1 specified
by len and src1addr are compared with string 2
specified by len and src2addr. In 5-operand format
the bytes of string 1 specified by src1len and
src1addr are compared with string 2 specified by
src2len and src2addr. If one string is longer than
the other the shorter string is conceptually
extended by appending bytes with the value of fill
to the end. Comparison proceeds until all the bytes
have been examined or inequality is detected.
Condition codes are affected by the last character
comparison.
Notes: After execution of CMPC3:
R0 = number of bytes remaining in string 1 (including
byte that terminated comparison); R0 is 0
only is strings are equal
R1 = address of the byte in string 1 that
terminated comparison; if strings are equal,
address of one byte beyond string 1
R2 = R0
R3 = address of the byte in string 2 that
terminated comparison; if strings are equal,
address of one byte beyond string 2
After execution of CMPC5:
R0 = number of bytes remaining in string 1 (including
byte that terminated comparison); R0 is 0
only if string1 and string 2 are of equal length
or string 1 was exhausted before comparison
terminated
R1 = address of the byte in string 1 that
terminated comparison; if comparison did not
terminate before string 1 exhausted,
address of one byte beyond string 1
R2 = number of bytes remaining in string 2 (including
byte that terminated comparison); R2 is 0 only
if string 1 and string 2 are of equal length or
string 2 was exhausted before comparison terminated
R3 = address of the byte in string 2 that
terminated comparison; if conmparison did not
terminate before string 2 was exhausted,
address of one byte beyond string 2
16.29 - CMPPx
Purpose: Compare two packed decimal strings and set the
condition codes
Format: opcode len.rw,scr1addr.ab,src2addr.ab ;3 operand
opcode src1len.rw,src1addr.ab,
src2len.rw,src2addr.ab ;4 operand
Operation: ({src1addr + ZEXT(len/2)}:src1addr) =
({src2addr + ZEXT(len/2)}:src2addr) ;3 operand
({src1addr + ZEXT(src1len/2)}:src1addr =
({arc2addr + ZEXT(src2len/2)}:src2addr ;4 operand
C. Codes: N = {{src1 string} LSS {src2 string}}, V = 0,
Z = {{src1 string} EQL {src2 string}}, C = 0
Exceptions: Reserved operand
Opcodes: 35 CMPP3 Compare packed 3 operand
37 CMPP4 Compare packed 4 operand
Description: In 3-operand format, the source 1 string specified
by src1addr and len is compared with the source 2
string specified by the src2addr and len. In
4-operand format, the source 1 string is specified
by src1addr and src1len, the source 2 string by
src2addr and src2len. The only action in either
case is to affect the condition codes.
Notes: After execution of CMPP3 or CMPP4:
R0 = 0
R1 = address of the byte containing the
most-significant digit of string 1
R2 = 0
R3 = address of the byte containing the
most-significant digit of string 2
16.30 - CMPxV
Purpose: Compare field - compare bit field to integer
Format: opcode pos.rl,size.rb,base.rb,src.rl
Operation: FIELD (pos, size, base) - src
C. Codes: N = {field LSS src}, Z = {field EQL src},
V = 0, C = {field LSSU src}
Exceptions: Reserved operand
Opcodes: EC CMPV Compare field
ED CMPZV Compare zero-extended field
Description: The field specified by pos, base and size is
compared with the source operand. For CMPV, src is
compared with the sign extended field. For CMPZV,
src is compared with the zero extended field. The
only action is to affect the condition codes.
16.31 - CRC
Purpose: Calculate cyclic redundancy check for software
or communications checking
Format: opcode tbl.ab,inicrc.rl,strlen.rw,stream.ab
Operation: R0 = CRC_accumulation (initial value - inicrc,
polynomial table - tbl, data stream - (stream,
strlen))
C. Codes: N = {R0 LSS 0}, Z = {R0 EQL 0}, V = 0, C = C
Exceptions: None
Opcodes: 0B CRC Cyclic redundancy check
Description: The CRC of the data stream pointed to by stream
and of length strlen is calculated. The initial
CRC is given by inicrc and is normally 0 or -1
unless the CRC is calculated in several steps.
R0 is replaced by the result. If the polynomial
is less than order -32, the result must be
extracted from R0. The CRC polynomial is expressed
by the contents of the 16-longword table.
16.32 - CVTxx
Purpose: Convert a signed quantity to a different signed
data type
Format: opcode src.rx,dst.wy
Operation: dst = conversion or src
C. Codes: N = dst LSS 0, Z = dst EQL 0, C = 0
V = {src cannot be represented in dst}
Exceptions: Integer/floating overflow, reserved operand
Opcodes: See table below:
from/to |Byte |Word |Long |F_float|D_float|G_float|H_float|
--------|------|------|------|------|------|-------|-------|
Byte | |99 x|98 x|4C e|6C e|4CFD e|6CFD e|
Word |33 t| |32 x|4D e|6D e|4DFD e|6DFD e|
Long |F6 t|F7 t| |4E r|6E e|4EFD e|6EFD e|
F_float |48 t|49 t|4A t| |56 e|99FD e|98FD e|
D_float |68 t|69 t|6A t|76 r| | |32FD e|
G_float |48FD t|49FD t|4AFD t|33FD r| | |56FD e|
H_float |68FD t|69FD t|6AFD t|F6FD r|F7FD r|76FD r| |
--------|------|------|------|------|------|-------|-------|
legend: t - truncate, x - sign extend, e - exact, r - rounded,
4B CVTRFL Convert and round F_floating to long
6B CVTRDL Convert and round D_floating to long
4BFD CVTRGL Convert and round G_floating to long
6BFD CVTRHL Convert and round H_floating to long
16.33 - CVTLP
Purpose: Convert longword to a packed decimal string
Format: opcode src.rl,dstlen.rw,dstaddr.ab
Operation: {dst string} = conversion of src
C. Codes: N = {{dst string} LSS 0}, V = {decimal overflow},
Z = {{dst string} EQL 0}, C = 0
Exceptions: Reserved operand, decimal overflow
Opcode: F9 CVTLP Convert long to packed
Description: src is converted to a packed decimal string and the
destination string operand specified by dstlen and
dstaddr is replaced by the result. dst
and R0-R3 are unpredictable on a reserved operand
abort. Overlapping operands will produce correct
results.
Notes: After execution:
R0 = 0
R1 = 0
R2 = 0
R3 = address of the byte containing the
most-significant digit of the destination string
16.34 - CVTPL
Purpose: Convert a packed decimal string to a longword
Format: opcode srclen.rw,srcaddr.ab,dst.wl
Operation: dst = conversion of {src string}
C. Codes: N = {dst LSS 0}, V = {integer overflow},
Z = {dst EQL 0}, C = 0
Exceptions: Reserved operand, integer overflow
Opcode: 36 CVTPL Convert packed to long
Description: The packed decimal source string src specified by
srclen and srcaddr is converted to a longword and
the result is placed in dst. dst is stored after all
the registers are updated. This means that dst can
be a register. Integer overflow can occur if the
decimal string converts to a value outside a
longword integer range. If this happens dst is
replaced by the low order bits of the correct
result. Overlapping operands will produce correct
results.
Notes: After execution:
R0 = 0
R1 = address of the byte containing the
most-significant digit of the source string
R2 = 0
R3 = 0
16.35 - CVTPS
Purpose: Convert a packed decimal string to leading separate
numeric
Format: opcode srclen.rw,srcaddr.ab,dstlen.rw,dstaddr.ab
Operation: {dst string} = conversion of {src string}
C. Codes: N = {{src string} LSS 0}, V = {decimal overflow},
Z = {{src string} EQL 0}, C = 0
Exceptions: Reserved operand, decimal overflow
Opcode: 08 CVTPS Convert packed to leading separate
Description: The packed decimal source string src specified by
srclen and srcaddr is changed to a leading separate
numeric string and the result is placed in dst as
specified by dstlen and dstaddr. Conversion is
effected by replacing the lowest addressed byte of
dst by the ASCII character "+" or "-", determined by
the sign of the source string. The remaining bytes of
dst are replaced by the ASCII characters that
correspond to the digits in src.
Notes: After execution:
R0 = 0
R1 = address of the byte containing the
most-significant digit of the source string
R2 = 0
R3 = address of the sign byte of the destination
string
16.36 - CVTPT
Purpose: Convert a packed decimal string to trailing numeric
Format: opcode srclen.rw,srcaddr.ab,tbladdr.ab,
dstlen.rw,dstaddr.ab
Operation: {dst string} = conversion of {src string}
C. Codes: N = {{src string} LSS 0}, V = {decimal overflow},
Z = {{src string} EQL 0}, C = 0
Exceptions: Reserved operand, decimal overflow
Opcode: 24 CVTPT Convert packed to trailing numeric
Description: The packed decimal source string src specified by
srclen and srcaddr is converted to a trailing
numeric string and the result is placed in dst as
specified by dstlen and dstaddr. Conversion is
effected by using the highest addressed byte of src
(i.e. the byte containing the sign and least
significant digit) as an unsigned index into a 256
byte table whose 0th entry is specified by tbladdr.
The byte read out of the table replaces the least
significant byte of dst. The remaining bytes of dst
are replaced by the ASCII representations of the
digits in src.
Notes: After execution:
R0 = 0
R1 = address of the byte containing the
most-significant digit of the source string
R2 = 0
R3 = address of the most-significant digit of
the destination string
16.37 - CVTSP
Purpose: Convert a leading separate numeric string to packed
decimal
Format: opcode srclen.rw,srcaddr.ab,dstlen.rw,dstaddr.ab
Operation: {dst string} = conversion of {src string}
C. Codes: N = {{dst string} LSS 0}, V = {decimal overflow},
Z = {{dst string} EQL 0}, C = 0
Exceptions: Reserved operand, decimal overflow
Opcode: 09 CVTSP Convert leading separate to packed
Description: The source leading separate numeric string src
specified by srclen and srcaddr is converted to
a packed decimal string and the result is placed
in dst as specified by dstlen and dstaddr.
Notes: After execution:
R0 = 0
R1 = address of the sign byte of the source string
R2 = 0
R3 = address of the byte containing the
most-significant digit of the destination string
16.38 - CVTTP
Purpose: Convert a trailing numeric string to packed decimal
Format: opcode srclen.rw,srcaddr.ab,tbladdr.ab,
dstlen.rw,dstaddr.ab
Operation: {dst string} = conversion of {src string}
C. Codes: N = {{dst string} LSS 0}, V = {decimal overflow},
Z = {{dst string} EQL 0}, C = 0
Exceptions: Reserved operand, decimal overflow
Opcode: 26 CVTTP Convert trailing numeric to packed
Description: The trailing numeric source string src specified by
srclen and srcaddr is converted to a packed
decimal string and the result is placed in dst as
specified by dstlen and dstaddr. Conversion is
effected by using the highest addressed byte of src
(i.e. the byte containing the sign and least
significant digit) as an unsigned index into a 256
byte table whose 0th entry is specified by tbladdr.
The byte read out of the table replaces the highest
addressed byte of dst. The packed digits of dst
are replaced by the low order four bits of each
ASCII character in src.
Notes: After execution:
R0 = 0
R1 = address of the most-significant digit of
the source string
R2 = 0
R3 = address of the byte containing the
most-significant digit of the destination string
16.39 - DECx
Purpose: Decrement - subtract 1 from an integer
Format: opcode dif.mx
Operation: dif = dif - 1
C. Codes: N = dif LSS 0, Z = dif EQL 0
V = {integer overflow}, C = {borrow from MSB}
Exceptions: Integer overflow
Opcodes: 97 DECB Decrement byte
B7 DECW Decrement word
D7 DECL Decrement long
Description: One is subtracted from the dif operand and the
dif operand is replaced by the result.
16.40 - DIVxx
Purpose: Perform arithmetic division
Format: opcode divr.rx,quo.mx ;2 operand
opcode divr.rx,divd.rx,quo.wx ;3 operand
Operation: quo = quo / divr ;2 operand
quo = divd / divr ;3 operand
C. Codes: N = {quo LSS 0}, Z = {quo EQL 0}, C = 0,
V = {overflow or {divr EQL 0}}
Exceptions: Integer or floating overflow, divide by zero
Floating underflow, reserved operand
Opcodes: 86 DIVB2 Divide byte 2 operand
87 DIVB3 Divide byte 3 operand
A6 DIVW2 Divide word 2 operand
A7 DIVW3 Divide word 3 operand
C6 DIVL2 Divide long 2 operand
C7 DIVL3 Divide long 3 operand
46 DIVF2 Divide F_floating 2 operand
47 DIVF3 Divide F_floating 3 operand
66 DIVD2 Divide D_floating 2 operand
67 DIVD3 Divide D_floating 3 operand
46FD DIVG2 Divide G_floating 2 operand
47FD DIVG3 Divide G_floating 3 operand
66FD DIVH2 Divide H_floating 2 operand
67FD DIVH3 Divide H_floating 3 operand
16.41 - DIVP
Purpose: Divide one packed decimal string by a second
decimal string
Format: opcode divrlen.rw,divraddr.ab,divdlen.rw,
divdaddr.ab,quolen.rw,quoaddr.ab
Operation: {quo string} = {divd string} / {divr string}
C. Codes: N = {{quo string} LSS 0}, V = {decimal overflow},
Z = {{quo string} EQL 0}, C = 0
Exceptions: Reserved operand, decimal overflow, divide by zero
Opcode: 27 DIVP Divide packed
Description: The dividend string specified by divdlen and divdaddr
is divided by the divisor string specified by divrlen
and divraddr. The result of the division is placed in
the quotient string specified by quolen and quoaddr.
Notes: After execution:
R0 = 0
R1 = address of the byte containing the
most-significant digit of the divisor string
R2 = 0
R3 = address of the byte containing the
most-significant digit of the dividend string
R4 = 0
R5 = address of the byte containing the
most-significant digit of the quotient string
16.42 - EDIV
Purpose: Perform extended-precision division
Format: opcode divr.rl,divd.rq,quo.wl,rem.wl
Operation: quo = divd/divr; rem = REM (divd, divr)
C. Codes: N = {quo LSS 0}, Z = {quo EQL 0}, C = 0,
V = {{integer overflow} OR {divr EQL 0}}
Exceptions: Integer overflow, divide by zero
Opcode: 7B EDIV Extended divide
16.43 - EDITPC
Purpose: Edit Packed to Character String
Format: opcode srclen.rw,srcaddr.ab,pattern.ab,dstaddr.ab
Operation:
C. Codes: N = {src string} LSS 0; !N <- 0 if src is -0
Z = {src string} EQL 0; C = {significance}
V = {decimal overflow}; !nonzero digits lost
Exceptions: reserved operand, decimal overflow
Opcode: 38 EDITPC Edit Packed to Character String
Description: The destination string specified by the pattern and
destination address operands is replaced by the edited
version of the source string specified by the source
length and source address operands. The editing is
performed according to the pattern string, starting at
the address pattern and extending until a pattern end
pattern operator (EO$END) is encountered.
The pattern string consists of 1-byte pattern operators.
Some pattern operators take no operands. Some take a
repeat count that is contained in the rightmost nibble
of the pattern operator itself. The rest take a 1-byte
operand that immediately follows the pattern operator.
This operand is either an unsigned integer length or
a byte character.
Notes: After execution:
R0 = length of source string
R1 = address of the byte containing the
most-significant digit of the source string
R2 = 0
R3 = address of the byte containing the EO$END
pattern operator
R4 = 0
R5 = address of one byte beyond the last byte of
teh destination string
16.44 - EMODx
Purpose: Extended multiply and integerize - perform accurate
range reduction of math function arguments
Format: opcode mulr.rx,mulrx.rb,muld.rx,int.wl,fract.wx
Operation: int = {integer part of muld * {mulr'mulrx}};
frac = {fractional part of muld * {mulr'mulrx}}
C. Codes: N = {fract LSS 0}, Z = {fract EQL 0},
V = {integer overflow}, C = 0
Exceptions: Integer or floating overflow, divide by zero
Opcodes: 54 EMODF Ext. mul., integerize F_floating
74 EMODD Ext. mul., integerize D_floating
54FD EMODG Ext. mul., integerize G_floating
74FD EMODH Ext. mul., integerize H_floating
Description: The floating multiplier extension mulrx is concatenated
with the floating point multiplier (mulr) to gain eight
additional low order fraction bits. This is then
multiplied by muld. After multiplication, the integer
portion is extracted and a floating point number is
formed from the fractional part by truncating extra
bits. The integer part is placed in int and the
fractional part in frac.
16.45 - EMUL
Purpose: Perform extended-precision multiplication
Format: opcode mulr.rl,muld.rl,add.rl,prod.wq
Operation: prod = {{muld * mulr} + SEXT (add)}
C. Codes: N = {prod LSS 0}, Z = {prod EQL 0}, V = 0, C = 0
Exceptions: None
Opcode: 7A EMUL Extended multiply
Description: mulr is multiplied by muld to give a double length
is then stored in prod.
16.46 - EXTxV
Purpose: Extract field - moves bit field to integer
Format: opcode pos.rl,size.rb,base.vb,dst.wl
Operation: EXTV: dst = if size NEQU 0 then SEXT (
FIELD (pos, size, base)) else 0
EXTZV: dst = if size NEQU 0 then ZEXT (
FIELD (pos, size, base)) else 0
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C
Exceptions: Reserved operand
Opcodes: EE EXTV Extract field, sign extend
EF EXTZV Extract field, zero extend
Description: For EXTV, dst is replaced by the sign-extended field
specified by pos, size and base. For EXTZV, dst is
replaced by the zero-extended field specified by pos,
size and base. If size is 0 dst is replaced by 0.
16.47 - FFx
Purpose: Find first - locate first bit in bit field
Format: opcode startpos.rl,size.rb,base.vb,findpos.wl
Operation: Find first set or clear bit searching left
across field
C. Codes: N = 0, Z = {bit not found}, V = 0, C = 0
Exceptions: Reserved operand
Opcodes: EB FFC Find first clear
EA FFS Find first set
Description: A field specified by the startpos, size and base
operands is extracted. The field is tested for a
bit in the indicated state starting at bit 0 and
extending to the highest bit in the field. If a
bit in the desired state is found, the findpos
operand is replaced with the bit position and the
Z condition bit is cleared. If no bit in the
indicated state is found, findpos is replaced by
the position relative to base of a bit one to the
left of the specified field and the Z condition
bit is set. If size = 0, findpos is replaced by
startpos and Z is set.
16.48 - HALT
Purpose: Stop processor operation
Format: opcode
Operation: If PSL<current_mode> NEQU kernel then
{reserved to Digital opcode fault}
else
{halt the processor}
C. Codes: N = 0, Z = 0, V = 0, C = 0 (fault)
Unaffected (processor halt)
Exceptions: Reserved to Digital opcode
Opcode: 00 HALT Halt
Description: If process is running in kernel mode, the processor
is halted. Otherwise, an opcode reserved to Digital
fault occurs. This opcode is 0 to trap many branches
to data.
16.49 - INCx
Purpose: Increment - add 1 to an integer
Format: opcode sum.mx
Operation: sum = sum + 1
C. Codes: N = {sum LSS 0}, Z = {sum EQL 0},
V = {integer overflow}, C = {carry from MSB}
Exceptions: Integer overflow
Opcodes: 96 INCB Increment byte
B6 INCW Increment word
D6 INCL Increment long
Description: One is added to the sum operand and the
sum operand is replaced by the result.
16.50 - INDEX
Purpose: Index calculation of arrays of fixed length data, bit
fields and strings
Format: opcode subscript.rl,low.rl,high.rl,size.rl,indexin.rl,
indexout.rl
Operation: indexout = {indexin + subscript}*size; if {subscript
LSS low} or {subscript GTR high} then {subscript
range trap}
C. Codes: N = {indexout LSS 0}, Z = {indexout EQL 0},
V = 0, C = 0
Exceptions: Subscript range
Opcode: 0A INDEX Index
Description: indexin is added to subscript and the sum is multiplied
by size. The result is placed in indexout. If subscript
is less than low or greater than high a subscript range
trap is taken.
16.51 - INSQHI
Purpose: Insert entry into queue at head, interlocked
Format: opcode entry.ab,header.aq
Operation: if {insertion succeded} then
begin
N <- 0;
Z <- (entry) EQL (entry+4); ! First entry in queue
V <- 0;
C <- 0;
end;
else
begin
N <- 0;
Z <- 0;
V <- 0;
C <- 1; ! Secondary interlock failed
end;
Exceptions: Reserved operand
Opcode: 5C INSQHI Insert entry into queue at head, interlocked
Description: The entry specified by the operand entry is
inserted into the queue following the header
specified by pred. If the entry inserted is the
first one in the queue, the Z bit is set; otherwise
it is cleared. The insertion is a noninterruptable
operation. The entire operation is validated before
any portion of it is attempted. The queue will be
left in a consistent state if a memory management
violation occurs.
16.52 - INSQTI
Purpose: Insert entry into queue at tail, interlocked
Format: opcode entry.ab,header.aq
Operation: if {insertion succeded} then
begin
N <- 0;
Z <- (entry) EQL (entry+4); ! First entry in queue
V <- 0;
C <- 0;
end;
else
begin
N <- 0;
Z <- 0;
V <- 0;
C <- 1; ! Secondary interlock failed
end;
Exceptions: Reserved operand
Opcode: 5D INSQTI Insert entry into queue at tail, interlocked
Description: The entry specified by the operand entry is
inserted into the queue preceding the header
specified by pred. If the entry inserted is the
first one in the queue, the Z bit is set; otherwise
it is cleared. The insertion is a noninterruptable
operation. The entire operation is validated before
any portion of it is attempted. The queue will be
left in a consistent state if a memory management
violation occurs.
16.53 - INSQUE
Purpose: Add entry to head or tail of queue
Format: opcode entry.ab,pred.ab
Operation: if {all memory accesses can be completed} then
begin
(entry) = (pred); ;forward link
(entry+4) = pred; ;backward link
((pred)+4) = entry; ;backward successor
(pred) = entry; ;forward predessor
end;
else
begin
{backup instruction};
{initiate fault};
end;
C. Codes: N = {(entry) LSS (entry + 4)}, V = 0,
C = {(entry) LSSU (entry + 4)},
Z = {(entry) EQL (entry + 4)}
Exceptions: None
Opcode: 0E INSQUE Insert entry in queue
Description: The queue entry specified by the operand entry is
inserted into the queue following the entry
specified by pred. If the entry inserted is the
first one in the queue, the Z bit is set; otherwise
it is cleared. The insertion is a noninterruptable
operation. The entire operation is validated before
any portion of it is attempted. The queue will be
left in a consistent state if a memory management
violation occurs.
16.54 - INSV
Purpose: Insert field - moves integer to bit field
Format: opcode src.rl,pos.rl,size.rb,base.vb
Operation: if size NEQU 0 then FIELD (pos, size, base) =
src <{size -1 }>
C. Codes: Not affected
Exceptions: Reserved operand
Opcode: F0 INSV Insert field
Description: The field specified by pos, size and base is
replaced by bits {size-1}:0 of src. If size is 0
no action occurs.
16.55 - JMP
Purpose: Transfer control
Format: opcode dst.ab
Operation: PC = dst
C. Codes: Not affected
Exceptions: None
Opcode: 17 JMP Jump
16.56 - JSB
Purpose: Jump to subroutine - transfer control to subroutine
Format: opcode dst.ab
Operation: -(SP) = PC; PC = dst
C. Codes: Not affected
Exceptions: None
Opcode: 16 JSB Jump to subroutine
Description: PC is pushed onto the stack as a longword and the
jump is taken.
16.57 - LDPCTX
Purpose: Load processor context - restore register and
memory management context
Format: opcode
Operation: if PSL<current-mode> NEQU 0 then {opcode reserved
to Digital fault}; {invalidate per-process
translation buffer entries}; {load process general
registers from process control block}; {load process
map, ASTLVL and PME from PCB}; {save PSL and PC on
stack for subsequent REI}
C. Codes: Not affected
Exceptions: Reserved operand, privileged instruction
Opcodes: 06 LDPCTX Load process context
Description: The process control block is specified by the
internal processor register PCBB (process control
block base). The general registers are loaded from
the PCB, along with the memory management registers
describing the address space. The process entries
in the translation buffer are cleared. Execution is
switched to the kernel stack. The PC and PSL are
moved from the PCB to the stack, suitable for use
by a REI instruction.
16.58 - LOCC
Purpose: To locate a character in a string
Format: opcode char.rb,len.rw,addr.ab
Operation: {compare each character until equal}
C. Codes: N = 0, Z = {R0 EQL 0}, Z = 0, C = 0
Exceptions: None
Opcode: 3A LOCC Locate character
Description: char is compared with the bytes of the string
specified by addr and len. Comparison continues
until char equals the character in the string or
until the string is exhausted. If equality is
detected the Z bit is cleared, otherwise it is set.
Notes: After execution:
R0 = number of bytes remaining in the string
(including located one) if byte located;
otherwise 0
R1 = address of the byte located if located;
otherwise address of one byte beyond the
string
16.59 - MATCHC
Purpose: To find a substring (object) in a character string
Format: opcode objlen.rw,objaddr.ab,srclen.rw,srcaddr.ab
Operation: {compare object substring with srcstring until match}
C. Codes: N = 0, Z = {R0 EQL 0}, Z = 0, C = 0
Exceptions: None
Opcode: 39 MATCHC Match characters
Description: src as specified by srclen and srcaddr is searched
for a substring which matches the object string as
specified by objlen and objaddr. If the substring
is found the Z bit is set, otherwise it is cleared.
The search continues until src is exhausted or
until a match is found.
Notes: After execution:
R0 = if a match occurred, 0; otherwise the number
of bytes in the object string
R1 = if a match occurred, the address of one byte
beyond the object string; that is,
objaddr + objlen; otherwise, the address of
the object string
R2 = if a match occurred, the number of bytes
remaining in the source string; otherwise 0
R3 = if a match occurred, the address of one byte
beyond the last byte matched; otherwise, the
address of one byte beyond the source string;
that is, srcaddr + srclen
For zero-length source and object strings, R3 and R1
contain the source and object addresses, respectively.
If both strings have 0 length or if the object string
has length 0, condition code Z is set and registers
R0-R3 are left just as though the substring were
found.
If the source has 0 length and the object string
has nonzero length, condition code Z is cleared
and registers R0-R3 are left just as though the
substring were not found.
16.60 - MCOMx
Purpose: Move the logical complement of an integer
Format: opcode src.rx,dst.wx
Operation: dst = NOT src
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C
Exceptions: None
Opcodes: 92 MCOMB Move complemented byte
B2 MCOMW Move complemented word
D2 MCOML Move complemented long
Description: The destination operand is replaced by the ones
complement of the source operand.
16.61 - MFPR
Purpose: Move from processor register - access
internal privileged registers
Format: opcode procreg.rl,dst.wl
Operation: if {PSL<current-mode> NEQ 0} then {reserved
instruction fault}; dst = PRS[procreg]
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C
C. Codes not affected if destination is not
replaced.
Exceptions: Reserved operand, privileged instruction
Opcode: DB MFPR Move from processor register
Description: The specified register is stored in dst. The first
operand procreg is a longword that contains the
register number. Execution may have register
specific side effects. A reserved operand fault
can occur if the register does not exist. A
reserved instruction fault will occur if MFPR
is executed in other than kernel mode.
16. 61.1 - Processor Registers
The following table is a summary of the registers accessible in
the privileged register space. Each mnemonic can be used to form
a symbol by prefixing it with "PR$_". The number of a register,
once assigned, will not change across implementations of the VAX
or within an implementation. All unsigned positive number are
reserved to Digital, all negative number are reserved for
customers.
The type column indicates whether the register is read-only,
write-only, or may be both read and written. The scope column
indicates whether the register is maintained on a per-process
basis or a per-CPU basis. The init column indicates whether the
register is set to some predefined initial value. The dashes
mean initialization is optional.
Register Name Mnemonic Number Type Scope Init
Kernel stack pointer KSP 0 R/W PROC ---
Executive stack pointer ESP 1 R/W PROC ---
Supervisor stack pointer SSP 2 R/W PROC ---
User stack pointer USP 3 R/W PROC ---
Interrupt stack pointer ISP 4 R/W CPU ---
P0 base register P0BR 8 R/W PROC ---
P0 length register P0LR 9 R/W PROC ---
P1 base register P1BR 10 R/W PROC ---
P1 length register P1LR 11 R/W PROC ---
System base register SBR 12 R/W CPU ---
System length register SLR 13 R/W CPU ---
Process control block base PCBB 16 R/W PROC ---
System block base SCBB 17 R/W CPU ---
Interrupt level IPL 18 R/W CPU yes
AST level ASTLVL 19 R/W PROC yes
Software interrupt request SIRR 20 W CPU ---
Software interrupt summary SISR 21 R/W CPU yes
Interval clock control ICCS 24 R/W CPU yes
Next interval count NICR 25 W CPU ---
Interval count ICR 26 R CPU ---
Time of year TODR 27 R/W CPU no
Console receiver C/S RXCS 32 R/W CPU yes
Console receiver D/B RXDB 33 R CPU ---
Console transmit C/S TXCS 34 R/W CPU yes
Console transmit D/B TXDB 35 W CPU ---
Memory management enable MAPEN 56 R/W CPU yes
Trans. buf. inval. all TBIA 57 W CPU ---
Trans. buf. inval. single TBIS 58 W CPU ---
Performance monitor enable PMR 61 R/W PROC yes
System identification SID 62 R CPU no
16.62 - MNEGx
Purpose: Move the arithmetic negation of a scalar quantity
Format: opcode src.rx,dst.wx
Operation: dst = -scr
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0 (floating),
V = overflow (integer), C = {dst NEQ 0} (integer),
C = 0 (floating)
Exceptions: Integer overflow, reserved operand (floating)
Opcodes: 8E MNEGB Move negated byte
AE MNEGW Move negated word
CE MNEGL Move negated long
52 MNEGF Move negated F_floating
72 MNEGD Move negated D_floating
52FD MNEGG Move negated G_floating
72FD MNEGH Move negated H_floating
Description: The destination operand is replaced by the
negative of the source operand.
16.63 - MOVx
Purpose: Move a scalar quantity
Format: opcode src.rx,dst.wx
Operation: dst = src
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C
Exceptions: None (integer), reserved operand (floating point)
Opcodes: 90 MOVB Move byte
B0 MOVW Move word
D0 MOVL Move long
7D MOVQ Move quad
7DFD MOVO Move octa
50 MOVF Move F_floating
70 MOVD Move D_floating
50FD MOVG Move G_floating
70FD MOVH Move H_floating
Description: The destination operand is replaced by the source
operand. The source operand is not affected.
16.64 - MOVAx
Purpose: Move address - calculate address of quantity
Format: opcode src.ax,dst.wl
Operation: dst = src
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = 0
Exceptions: None
Opcodes: 9E MOVAB Move address of byte
3E MOVAW Move address of word
DE MOVAL Move address of long
7E MOVAQ Move address of quad
7EFD MOVAO Move address of octa
DE MOVAF Move address of F_floating
7E MOVAD Move address of D_floating
7E MOVAG Move address of G_floating
7EFD MOVAH Move address of H_floating
Description: dst is replaced by the address of src. The context in
which src is evaluated is given by the data type of the
instruction. The operand at the address of src is not
referenced.
16.65 - MOVCx
Purpose: Move character string or block of memory
Format: opcode len.rw,srcaddr.ab,dstaddr.ab ;3 operand
opcode srclen.rw,srcaddr.ab,fill.rb, ;5 operand
dstlen.rw,dstaddr.ab
Operation: {dst string} = {src string}
Exceptions: None
Opcodes: 28 MOVC3 Move character 3 operand
2C MOVC5 Move character 5 operand
Description: dst as specified by dstaddr and len (3 operand) or
dstlen (5 operand) is replaced by src as specified by
srcaddr and len (3 operand) or srclen (5 operand). If
dst is longer than src (5 operand only), the highest
addresses of dst that are not filled by src are
instead filled with fill. If dst is shorter than src,
the copied string is truncated to fit in src. The
operation of the instruction is such that any overlap
of src and dst will not affect the result.
Notes: After execution of MOVC3:
R0 = 0
R1 = address of one byte beyond the source string
R2 = 0
R3 = address of one byte beyond the destination string
R4 = 0
R5 = 0
After execution of MOVC5:
R0 = number of unmoved bytes remaining in the
source string. R0 is nonzero only if source
string is longer than the destination string
R1 = address of one byte beyond the last byte in
source string that was moved
R2 = 0
R3 = address of one byte beyond the destination string
R4 = 0
R5 = 0
16.66 - MOVP
Purpose: Moved a packed decimal string from one memory
location to another
Format: opcode len.rw,srcaddr.ab,dstaddr.ab
Operation: ({dstaddr + ZEXT (len/2)} : dstaddr) =
({srcaddr + ZEXT (len/2)} : srcaddr)
C. Codes: N = {{dst string} LSS 0}, V = 0,
Z = {{dst string} EQL 0}, C = C
Exceptions: Reserved operand
Opcodes: 34 MOVP Move packed
Description: The string dst specified by dstaddr and len is
replaced by the string src specified by srcaddr
and len.
Notes: After execution:
R0 = 0
R1 = address of the byte containing the
most-significant digit of the source string
R2 = 0
R3 = address of the byte containing the
most-significant digit of the destination string
16.67 - MOVPSL
Purpose: Obtain processor status
Format: opcode dst.wl
Operation: dst = PSL
C. Codes: Not affected
Exceptions: None
Opcode: DC MOVPSL Move from PSL
16.68 - MOVTC
Purpose: to move and translate a character string
Format: opcode srclen.rw,srcaddr.ab,fill.rb,tbladdr.ab,
dstlen.rw,dstaddr.ab
C. Codes: N = {srclen LSS dstlen}, Z = {srclen EQL dstlen},
V = 0, C = {srclen LSSU dstlen}
Exceptions: None
Opcode: 2E MOVTC Move translated characters
Description: The source operand string specified by srclen and
srcaddr is translated and replaces the destination
string as specified by dstlen and dstaddr.
Translation is done by using each byte of src as an
index into tbl (a 256 byte array). The selected byte
is placed in dst. If the dst is longer than src, dst
is filled using fill. If dst is shorter than src,
the highest bytes of src are not moved. dst and src
may overlap with no ill effects -- but if dst
overlaps tbl the result is unpredictable.
Notes: After execution:
R0 = number of untranslated bytes remaining in the
source string; R0 is nonzero only if source
string is longer than destination string
R1 = address of one byte beyond the last byte in
source string that was translated
R2 = 0
R3 = address of the translation table
R4 = 0
R5 = address of one byte beyond the destination string
16.69 - MOVTUC
Purpose: To move and translate a character string, handling
escape codes (until character)
Format: opcode srclen.rw,srcaddr.ab,esc.rb,tbladdr.ab,
dstlen.rw,dstaddr.ab
C. Codes: N = {srclen LSS dstlen}, Z = {srclen EQL dstlen},
V = {terminated by escape}, C = {srclen LSSU dstlen}
Exceptions: None
Opcode: 2F MOVTUC Move translated until character
Description: The source operand string specified by srclen and
srcaddr is translated and replaces the destination
string as specified by dstlen and dstaddr. Translation
is done by using each byte of src as an index into
tbl (256 byte array). The selected byte is placed in
dst. Translation continues until a translated byte
equals esc or either string is exhausted. If
translation is terminated by esc, the condtion code
V-bit is set. If dst overlaps src or tbl, dst and the
registers are unpredictable.
Notes: After execution:
R0 = number of bytes remaining in source string
(including the byte that caused the escape);
R0 is 0 only if the entire source string was
translated and moved without escape
R1 = address of the byte that resulted in destination
string exhaustion or escape; or if no exhaustion
or escape, address of one byte beyond the
source string
R2 = 0
R3 = address of the table
R4 = number of bytes remaining in the destination
string
R5 = address of the byte in the destination string
that would have received the translated byte
that caused the escape, or would have received
a translated byte if the source string were
not exhausted; or if no exhaustion or escape,
the address of one byte beyond the destination
string
16.70 - MOVZxx
Purpose: Convert an unsigned integer to a wider unsigned
integer (move zeroed)
Format: opcode src.rx,dst.wy
Operation: dst = ZEXT (src)
C. Codes: N = 0, Z = {dst EQL 0}, V = 0, C = C
Exceptions: None
Opcodes: 9B MOVZBW Move zero-extended byte to word
9A MOVZBL Move zero-extended byte to long
3C MOVZWL Move zero-extended word to long
Description: For MOVZBW, bits 7:0 of dst are replaced by src,
bits 15:8 are zeroed. For MOVZBL, bits 7:0 of
dst are replaced by src, bits 31:8 are zeroed.
For MOVZWL, bits 15:0 of dst are replaced by src,
bits 31:16 are zeroed.
16.71 - MTPR
Purpose: Move to processor register - change
internal privileged registers
Format: opcode src.rl,procreg.rl
Operation: if {PSL<current-mode> NEQ 0} then {reserved
instruction fault}; PRS[procreg] = src
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C
C. Codes not affected if register is not
replaced.
Exceptions: Reserved operand, privileged instruction
Opcode: DA MTPR Move to processor register
Description: The specified register is loaded. The second operand
procreg is a longword that contains the register
number. Execution may have register-specific side
effects. A reserved operand fault can occur if the
register does not exist. A reserved instruction fault
will occur if the instruction is executed in other
than kernel mode. See the instruction MFPR for a list
of processor registers.
16.72 - MULxx
Purpose: Perform arithmetic multiplication
Format: opcode mulr.rx,prod.mx ;2 operand
opcode mulr.rx,muld.rx,prod.wx ;3 operand
Operation: prod = prod * mulr ;2 operand
prod = muld * mulr ;3 operand
C. Codes: N = {prod LSS 0}, Z = {prod EQL 0},
V = {overflow}, C = 0
Exceptions: Integer, floating overflow
Floating underflow, reserved operand
Opcodes: 84 MULB2 Multiply byte 2 operand
85 MULB3 Multiply byte 3 operand
A4 MULW2 Multiply word 2 operand
A5 MULW3 Multiply word 3 operand
C4 MULL2 Multiply long 2 operand
C5 MULL3 Multiply long 3 operand
44 MULF2 Multiply F_floating 2 operand
45 MULF3 Multiply F_floating 3 operand
64 MULD2 Multiply D_floating 2 operand
65 MULD3 Multiply D_floating 3 operand
44FD MULG2 Multiply G_floating 2 operand
45FD MULG3 Multiply G_floating 3 operand
64FD MULH2 Multiply H_floating 2 operand
65FD MULH3 Multiply H_floating 3 operand
16.73 - MULP
Purpose: Multiply one packed decimal string by a second,
result placed in third
Format: opcode mulrlen.rw,mulraddr.ab,muldlen.rw,
muldaddr.ab,prodlen.rw,prodaddr.ab
Operation: {prod string} = {muld string} * {mulr string}
C. Codes: N = {{prod string} LSS 0}, V = {decimal overflow},
Z = {{prod string} EQL 0}, C = 0
Exceptions: Reserved operand, decimal overflow
Opcode: 25 MULP Multiply packed
Description: The multiplicand string muld specified by muldaddr
and muldlen is multiplied by the multiplier string
mulr specified by mulraddr and mulrlen. The product
is placed in the string prod as specified by prodaddr
and prodlen.
Notes: After execution:
R0 = 0
R1 = address of the byte containing the
most-significant digit of the multiplier string
R2 = 0
R3 = address of the byte containing the
most-significant digit of the multiplicand string
R4 = 0
R5 = address of the byte containing the
most-significant digit of the product string
16.74 - NOP
Purpose: No operation is performed
Format: opcode
C. Codes: Not affected
Exceptions: None
Opcode: 01 NOP No Operation
16.75 - POLYx
Purpose: Allows fast calculation of math functions
Format: opcode arg.x,degree.rw,tbladdr.ab
Operation: result = Cdegree (first table entry)
For degree times, loop
result = arg * result
Perform multiply and retain an extended
floating fraction of 31 bits (POLYF) or
63 bits (POLYD). The fraction is truncated
before normalization.
result = result + Cnext (next table entry)
Normalize, round and check for over/
underflow only after the combined multiply/
add sequence.
if overflow then trap.
if underflow then clear result, remember
underflow and continue looping.
C. Codes: N = {R0 LSS 0}, Z = {R0 EQL 0},
V = {floating overflow}, C = 0
Exceptions: Floating overflow/underflow, reserved operand
Opcodes: 55 POLYF Polynomial evaluation F_floating
75 POLYD Polynomial evaluation D_floating
55FD POLYG Polynomial evaluation G_floating
75FD POLYH Polynomial evaluation H_floating
16.76 - POPR
Purpose: Restore multiple registers from stack
Format: opcode mask.rw
Operation: Restore registers in order R14 .. R0
C. Codes: Not affected
Exceptions: None
Opcode: BA POPR Pop registers
Description: The contents of the registers whose number
corresponds to set bits in the mask operand
are replaced by longwords popped from the stack.
R[n] is pushed if mask <n> is set. The mask is
scanned from bit 14 to bit 0. Bit 15 is ignored.
16.77 - PROBEx
Purpose: Probe accessibility - verify arguments
Format: opcode mode.rb,len.rw,base.ab
Operation: probe_mode = MAXU (mode<1:0>, PSL <PRV_MOD>);
condition_codes = {{accessibility of base} AND
{accessibilty of (base + ZEXT (len) - 1)} using
probe_mode}
C. Codes: N = 0, V = 0, C = 0,
Z = {if {accessible} then 0 else 1}
Exceptions: Translation not valid
Opcodes: 0C PROBER Probe read accessibility
0D PROBEW Probe write accessibility
Description: The PROBE instruction checks the read or write
accessibility of the first and last byte specified
by base and the zero extended length -- the bytes
in between are not checked. System software must
check all the pages in between if they are to be
accessed. The protection is checked against the
larger of the modes specified in bits <1:0> of the
mode operand and the previous mode field of the PSL.
Note that probing with a mode operand of 0 is
equivalent to probing the previous mode.
16.78 - PUSHAx
Purpose: Push address - calculate address of quantity
Format: opcode src.ax
Operation: -(SP) = src
C. Codes: N = {result LSS 0}, Z = {result EQL 0}, V = 0, C = 0
Exceptions: None
Opcodes: 9F PUSHAB Push address of byte
3F PUSHAW Push address of word
DF PUSHAL Push address of long
7F PUSHAQ Push address of quad
7FFD PUSHAO Push address of octa
DF PUSHAF Push address of F_floating
7F PUSHAD Push address of D_floating
7F PUSHAG Push address of G_floating
7FFD PUSHAH Push address of H_floating
Description: The address of src is pushed on the stack. The context
in which src is evaluated is given by the data type of
the instruction. The operand at the address of src is
not referenced. PUSHAx is equivalent to
MOVAx src,-(SP) but is shorter.
16.79 - PUSHL
Purpose: Push source operand onto stack
Format: opcode src.rl
Operation: -(SP) = src
C. Codes: N = {src LSS 0}, Z = {src EQL 0}, V = 0, C = C
Exceptions: None
Opcode: DD PUSHL Push long
Description: The long word source operand is pushed on
the stack.
16.80 - PUSHR
Purpose: Save multiple registers on stack
Format: opcode mask.rw
Operation: Save registers in order R0 .. R14
C. Codes: Not affected
Exceptions: None
Opcode: BB PUSHR Push registers
Description: The contents of the registers whose number corresponds
to set bits in the mask operand are pushed on the
stack as longwords. R[n] is pushed if mask <n> is set.
The mask is scanned from bit 14 to bit 0. Bit 15 is
ignored.
16.81 - REI
Purpose: Exit from an exception or interrupt service routine
and control the return
Format: opcode
Operation: tmp1 = (SP)+; tmp2 = (SP)+;
if {tmp2<current_mode> LSSU PSL<current_mode>} OR
{{tmp2<IS> EQLU 1} AND {PSL<IS> EQLU 0}} OR
{{tmp2<IS> EQLU 1} AND
{tmp2<current_mode> NEQU 0}} OR
{{tmp2<IS> EQLU 1} AND {tmp2<IPL> EQLU 0}} OR
{{tmp2<IPL> GRTU 0} AND
{tmp2<current_mode> NEQU 0}} OR
{tmp2<previous_mode> LSSU tmp2<current_mode>} OR
{tmp2<IPL> GTRU PSL<IPL>} OR
{tmp2<PSL_MBZ> NEQU 0} then
{reserved operand fault};
if {tmp2<CM> EQLU 1} AND
{{tmp2<FPD, IS, DV, FU, IV> NEQU 0} OR
{tmp2<current_mode> NEQU 3}} then
{reserved operand fault};
if PSL<IS> EQLU 1 then ISP = SP else
PSL<current_mode>_SP = SP;
if PSL<TP> EQLU 1 then tmp2<TP> = 1;
PC = tmp1;
PSL = tmp2;
if PSL<IS> EQLU 0 then
begin
SP = PSL<current_mode>_SP;
if PSL<current_mode> GEQU ASTLVL
then {request interrupt at IPL 2};
end;
{check for software interrupts}
C. Codes: N = {saved PSL<3>}, Z = {saved PSL<2>},
V = {saved PSL<1>}, C = {saved PSL<0>}
Exceptions: Reserved operand
Opcode: 02 REI Return from exception or interrupt
Description: A longword is popped from the current stack and
held in a temporary PC. A second longword is popped
and held in a temporary PSL. Validity of the popped
PSL is checked. The current stack pointer is saved
and a new stack is selected according to the new
PSL current_mode and IS fields. The level of the
highest privilege AST is checked against the current
access mode to see whether a pending AST can be
delivered. Execution resumes with the instruction
being executed at the time of the exception or
interrupt. Any instruction lookahead in the CPU
is reinitialized.
16.82 - REMQHI
Purpose: Remove entry from queue at head, interlocked
Format: opcode header.aq,addr.wl
Operation: if {removal succeded} then
begin
N <- 0;
Z <- (header) EQL (entry+4);! Queue empty after interval
V <- {queue empty before this instruction};
C <- 0;
end;
else
begin
N <- 0;
Z <- 0;
V <- 1; ! Did not remove anything
C <- 1; ! Secondary interlock failed
end;
Exceptions: Reserved operand
Opcode: 5E REMQHI Remove entry from queue at head, interlocked
Description: If the secondary interlock is clear, the queue entry
following the header is removed from the queue and the
address operand is replaced by the address of the entry
removed. If the queue was empty prior to this instruction,
or if the secondary interlock failed, the V-bit is set;
otherwise it is cleared. If the interlock succeded and the
queue is empty at the end of this instruction, the Z-bit
is set; otherwise it is cleared.
The removal is a noninterruptable operation. The entire
operation is validated before any portion of it is
attempted. The queue will be left in a consistent state
if a memory management violation occurs.
16.83 - REMQTI
Purpose: Remove entry from queue at tail, interlocked
Format: opcode header.aq,addr.wl
Operation: if {removal succeded} then
begin
N <- 0;
Z <- (header+4) EQL 0; ! Queue empty after removal
V <- {queue empty before this instruction};
C <- 0;
end;
else
begin
N <- 0;
Z <- 0;
V <- 1; ! Did not remove anything
C <- 1; ! Secondary interlock failed
end;
Exceptions: Reserved operand
Opcode: 5F REMQTI Remove entry from queue at tail, interlocked
Description: If the secondary interlock is clear, the queue entry
preceding the header is removed from the queue and the
address operand is replaced by the address of the entry
removed. If the queue was empty prior to this instruction,
or if the secondary interlock failed, the V-bit is set;
otherwise it is cleared. If the interlock succeded and the
queue is empty at the end of this instruction, the Z-bit
is set; otherwise it is cleared.
The removal is a noninterruptable operation. The entire
operation is validated before any portion of it is
attempted. The queue will be left in a consistent state
if a memory management violation occurs.
16.84 - REMQUE
Purpose: Remove entry from head or tail of queue
Format: opcode entry.ab,addr.wl
Operation: if {all memory accesses can be completed} then
begin
((entry+4)) = (entry); ((entry)+4) = (entry+4);
addr = entry;
end;
else begin
{backup instruction}; {initiate fault};
end;
C. Codes: N = {(entry) LSS (entry+4)},
Z = {(entry) EQL (entry+4)},
V = {entry EQL (entry + 4)},
C = {(entry) LSSU (entry+4)}
Exceptions: None
Opcode: 0F REMQUE Remove entry from queue
Description: The queue entry specified by entry is removed from
the queue. The address operand is replaced by the
address of the entry removed. If there way no entry
in the queue to be removed, the condition code V is
set; otherwise it is cleared. The removal is a
noninterruptable operation. The entire operation is
validated before any part is executed. If a memory
management exception occurs the queue is left in a
consistent state.
16.85 - RET
Purpose: Return from called procedure
Format: opcode
Operation: {restore SP from FP}; {restore registers};
{drop stack alignment};
{if CALLS, remove arglist}; {restore PSW}
C. Codes: N = tmp1<3>, Z = tmp1<2>, V = tmp1<1>,
C = tmp1<0>
Exceptions: Reserved operand
Opcode: 04 RET Return from procedure
Description: SP is replaced with FP plus 4. A longword containing
stack alignment in bits 31:30, a CALLS/CALLG flag in
bit 29, the low 12 bits of the procedure entry mask
in bits 27:16 and a saved PSW in bits 15:0 is popped
from the stack and saved in a temporary (tmp1). PC,
FP and AP are replaced by longwords popped from the
stack. A register restore mask is formed from bits
27:16 of tmp1. Scanning from bit 0 to bit 11 of tmp1,
the contents of the registers whose numbers are
indicated by set bits in the restore mask are
replaced by longwords popped from the stack. SP is
incremented by bits 31:30 of tmp1. PSW is replaced by
bits 15:0 of tmp1. If bit 29 of tmp1 is 1 (indicating
a CALLS was used) a longword containing the number of
arguments is popped from the stack. Four times the
unsigned value of the low byte of this longword is
added to SP and SP is replaced by the result.
16.86 - ROTL
Purpose: Rotate of integer
Format: opcode cnt.rb,src.rl,dst.wl
Operation: dst = src rotated cnt bits
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C
Exceptions: None
Opcode: 9C ROTL Rotate long
Description: The source operand is rotated logically by the number
of bits specified by the count operand and the
destination is replaced by the result. The source
operand is unaffected. A positive count rotates to the
left, a negative to the right. A 0 count leaves the
value unaffected.
16.87 - RSB
Purpose: Return from subroutine -
return control from subroutine
Format: opcode
Operation: PC = (SP)+
C. Codes: Not affected
Exceptions: None
Opcode: 05 RSB Return from subroutine
16.88 - SBWC
Purpose: Subtract with carry - perform extended-precision
subtraction
Format: opcode sub.rl,dif.ml
Operation: dif = dif - sub - C
C. Codes: N = {dif LSS 0}, Z = {dif EQL 0},
V = {integer overflow}, C = {borrow from MSB}
Exceptions: Integer overflow
Opcode: D9 SBWC Subtract with carry
16.89 - SCANC
Purpose: To find one of a set of characters in a string
Format: opcode len.rw,addr.ab,tbladdr.ab,mask.rb
Operation: {mask each character until not zero}
C. Codes: N = 0, Z = {R0 EQL 0}, Z = 0, C = 0
Exceptions: None
Opcode: 2A SCANC Scan characters
Description: The bytes of the string specified by addr and len are
used to index into a 256 byte table pointed to by
tbladdr. The byte selected from the table is ANDed
with mask. The operand proceeds until the result of
the AND is nonzero or all the bytes of the string
have been exhausted. If a nonzero AND result is
detected, the Z bit is cleared; otherwise, the Z bit
is set.
Notes: After execution:
R0 = number of bytes remaining in the string
(including the byte that produced the
nonzero AND result); R0 is 0 only if
there was no nonzero result
R1 = address of the byte that produced the
nonzero AND result, if no nonzero result,
address of one byte beyond the string
R2 = 0
R3 = address of the table
If the string has 0 length, condition code Z is set
just as though the entire string were scanned.
16.90 - SKPC
Purpose: To skip a character in a string
Format: opcode char.rb,len.rw,addr.ab
Operation: {compare each character until not equal}
C. Codes: N = 0, Z = {R0 EQL 0}, Z = 0, C = 0
Exceptions: None
Opcode: 3B SKPC Scan characters
Description: char is compared with the bytes of the string
specified by addr and len. Comparison continues until
char does not equal the character in the string or
until the string is exhausted. If inequality is
detected, the Z bit is cleared; otherwise, the Z bit
is set.
Notes: After execution:
R0 = number of bytes remaining in the string
(including the unequal one) if unequal byte
located; otherwise 0
R1 = address of the byte located if byte located;
otherwise address of one byte beyond the string
If the string has 0 length, condition code Z is set
just as though each byte of the entire string were
equal to the character.
16.91 - SOBGxx
Purpose: Subtract one and branch - decrement integer loop count
and loop
Format: opcode index.ml,displ.bb
Operation: index = index - 1; if {{SOBGEQ} and {index GEQ 0}} or
{{SOBGTR} and {index GTR 0}} then
PC = PC + SEXT (displ)
C. Codes: N = {index LSS 0}, Z = {index EQL 0},
V = {integer overflow}, C = C
Exceptions: Integer overflow
Opcodes: F4 SOBGEQ Subtract one, branch greater or equal
F5 SOBGTR Subtract one, branch greater than
16.92 - SPANC
Purpose: To skip a set of characters in a string
Format: opcode len.rw,addr.ab,tbladdr.ab,mask.rb
Operation: {mask each character until zero}
C. Codes: N = 0, Z = {R0 EQL 0}, V = 0, C = 0
Exceptions: None
Opcode: 2B SPANC Span characters
Description: The bytes of the string specified by addr and len are
used to index into a 256 byte table pointed to by
tbladdr. The byte selected from the table is ANDed
with mask. The operand proceeds until the result of
the AND is zero or all the bytes of the string have
been exhausted. If a zero AND result is detected, the
Z bit is cleared; otherwise, the Z bit is set.
Notes: After execution:
R0 = number of bytes remaining in the string
(including the byte that produced the
0 AND result); R0 is 0 only if
there was no 0 AND result
R1 = address of the byte that produced the
0 AND result, if no nonzero result,
address of one byte beyond the string
R2 = 0
R3 = address of the table
If the string has 0 length, condition code Z is set
just as though the entire string were spanned
16.93 - SUBxx
Purpose: Perform arithmetic subtraction
Format: opcode sub.rx,dif.mx ;2 operand
opcode sub.rx,min.rx,dif.wx ;3 operand
Operation: dif = dif - sub ;2 operand
dif = min - sub ;3 operand
C. Codes: N = {dif LSS 0}, Z = {dif EQL 0},
V = {overflow}, C = 0 (floating),
C = {borrow from MSB (integer)}
Exceptions: Integer/floating overflow, floating
underflow, reserved operand
Opcodes: 82 SUBB2 Subtract byte 2 operand
83 SUBB3 Subtract byte 3 operand
A2 SUBW2 Subtract word 2 operand
A3 SUBW3 Subtract word 3 operand
C2 SUBL2 Subtract long 2 operand
C3 SUBL3 Subtract long 3 operand
42 SUBF2 Subtract F_floating 2 operand
43 SUBF3 Subtract F_floating 3 operand
62 SUBD2 Subtract D_floating 2 operand
63 SUBD3 Subtract D_floating 3 operand
42FD SUBG2 Subtract G_floating 2 operand
43FD SUBG3 Subtract G_floating 3 operand
62FD SUBH2 Subtract H_floating 2 operand
63FD SUBH3 Subtract H_floating 3 operand
16.94 - SUBPx
Purpose: Subtract one packed decimal string from a second
Format: opcode sublen.rw,subaddr.ab,
diflen.rw,difaddr.ab ;4 operand
opcode sublen.rw,subaddr.ab,minlen.rw,
minaddr.ab,diflen.rw,difaddr.ab ;6 operand
Operation: {dif string} = {dif string} - {sub string} ;4 operand
{dif string} = {min string} - {sub string} ;6 operand
C. Codes: N = {{dif string} LSS 0}, V = {decimal overflow},
Z = {{dif string} EQL 0}, C = 0
Exceptions: Reserved operand, decimal overflow
Opcode: 25 SUBP4 Subtract packed 4 operand
23 SUBP6 Subtract packed 6 operand
Description: sub as specified by subaddr and sublen is subtracted
from dif as specified by difaddr and diflen (in 4
operand form) or min as specified by minaddr and
minlen (in 6 operand form) and the result is placed
in dif.
Notes: After execution of SUBP4:
R0 = 0
R1 = address of the byte containing the
most-significant digit of the subtrahend string
R2 = 0
R3 = address of the byte containing the
most-significant digit of the difference string
After execution of SUBP6:
R0 = 0
R1 = address of the byte containing the
most-significant digit of the subtrahend string
R2 = 0
R3 = address of the byte containing the
most-significant digit of the minuend string
R4 = 0
R5 = address of the byte containing the
most-significant digit of the difference string
16.95 - SVPCTX
Purpose: Save processor context - save register and
memory management context
Format: opcode
Operation: if PSL<current-mode> NEQU 0 then {opcode reserved
to Digital fault}; {save process general registers
in the process control block}; {remove PSL and PC
from stack and save in PCB}; {switch to interrupt
stack}
C. Codes: Not affected
Exceptions: Reserved operand, privileged instruction
Opcodes: 07 SVPCTX Load process context
Description: The process control block is specified by the
internal processor register PCBB (process control
block base). The general registers are saved in
the PCB. If the current stack in use is the kernel
stack, execution is changed to the interrupt
stack.
16.96 - TSTx
Purpose: Arithmetic compare of a scalar to 0.
Format: opcode src.rx
Operation: src - 0
C. Codes: N = {src LSS 0}, Z = {src EQL 0}, V = 0, C = 0
Exceptions: None (integer), reserved operand (floating)
Opcodes: 95 TSTB Test byte
B5 TSTW Test word
D5 TSTL Test long
53 TSTF Test F_floating
73 TSTD Test D_floating
53FD TSTG Test G_floating
73FD TSTH Test H_floating
Description: The condition codes are affected according to
the values of src.
16.97 - XFC
Purpose: Extended function call - provides customer-defined
extensions to the instruction set
Format: opcode
Operation: {XFC fault}
C. Codes: N = 0, Z = 0, V = 0, C = 0
Exceptions: Opcode reserved to customer, customer reserved
exception
Opcodes: FC XFC Extended function call
Description: This instruction requests services of nonstandard
microcode or software. If no special microcode is
loaded, then an exception is generated to a kernel
mode software simulator. Typically the byte after
the XFC would request a specific service. Parameters
would be passed either as normal operands or in the
registers.
16.98 - XORxx
Purpose: Perform logical exclusive OR of two integers
Format: opcode mask.rx,dst.mx ;2 operand
opcode mask.rx,src.rx,dst.rx ;3 operand
Operation: dst = dst XOR mask ;2 operand
dst = src XOR mask ;3 operand
C. Codes: N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C
Exceptions: None
Opcodes: 88 XORB2 Exclusive OR byte, 2 operand
89 XORB3 Exclusive OR byte, 3 operand
A8 XORW2 Exclusive OR word, 2 operand
A9 XORW3 Exclusive OR word, 3 operand
C8 XORL2 Exclusive OR long, 2 operand
C9 XORL3 Exclusive OR long, 3 operand
Description: In 2 operand format, dst is XORed with mask and dst
is replaced by the result. In 3 operand format, src
is XORed with mask and dst is replaced by the result.
| 17 - Operand Formats |
Operands for instructions identify the memory locations or
the registers that are used by the machine operation. These
operands specify the addressing mode for the instruction.
17.1 - Absolute
The address specified is the address of the operand. The address
is stored as an absolute virtual address (compare relative mode,
where the address is stored as a displacement from the PC).
Absolute mode can be used with index mode.
@#address
address
An expression specifying an address.
17.2 - Autodecrement
The processor decrements the contents of the register by the size
of the operand data type; then the register contains the address
of the operand. The processor decrements the register by 1, 2, 4,
8, or 16 for byte, word, longword, quadword, or
octaword operands, respectively. Autodecrement mode can be used
with index mode.
-(Rn)
-(AP)
-(FP)
-(SP)
n
A number in the range of 0 through 12.
17.3 - Autoincrement
The register contains the address of the operand. After
evaluating the operand address contained in the register,
the processor increments the contents of the register by 1, 2, 4,
8, or 16 for a byte, word, longword, quadword, or
octaword respectively. Autoincrement mode can be used with index
mode.
(Rn)+
(AP)+
(FP)+
(SP)+
n
A number in the range of 0 through 12.
17.4 - Autoincrement deferred
The register contains an address that is the address of the
operand address (a pointer to the operand). After evaluating
the operand address, the processor increments the contents of the
register by 4 (the size in bytes of an address). Autoincrement
deferred mode can be used with index mode.
@(Rn)+
@(AP)+
@(FP)+
@(SP)+
n
A number in the range of 0 through 12
17.5 - Branch
The address is stored as an implied displacement from the PC.
This mode can be used only in branch instructions. The
displacement for conditional branch instructions and the BRB
instruction is stored in a byte. The displacement for the BRW
instruction is stored in a word (two bytes). A byte displacement
allows a range of 127 bytes forward and 128 bytes backward. A
word displacement allows a range of 32767 bytes forward and 32768
bytes backward. The displacement is relative to the updated PC,
the byte past the byte or word where the displacement is
stored.
address
address
An expression that represents an address.
17.6 - Displacement
The contents of the register plus the displacement (sign-extended
to a longword) produce the address of the operand. Displacement
mode can be used with index mode.
displ(Rn)
displ(AP)
displ(FP)
displ(SP)
n
A number in the range of 0 through 12.
displ
An expression specifying a displacement; the expression can
be preceded by one of the following displacement length
specifiers, which indicate the number of bytes needed to store the
displacement.
B^ Displacement requires one byte.
W^ Displacement requires one word (two bytes).
L^ Displacement requires one longword (four bytes).
If no displacement length specifier precedes the expression, and
the value of the expression is known, the assembler chooses the
smallest number of bytes (one, two, or four) needed to store the
displacement. If no length specifier precedes the expression, and
the value of the expression is unknown, the assembler reserves one
word (two bytes) for the displacement. Note that if the
displacement is either relocatable or defined later in the source
program, the assembler considers it unknown. If the actual
displacement does not fit in the memory reserved, the Linker
displays an error message.
17.7 - Displacement deferred
The contents of the register plus the displacement (sign-extended
to a longword) produce the address of the operand address (a
pointer to the operand). Displacement deferred mode can be used
with index mode.
@displ(Rn)
@displ(AP)
@displ(FP)
@displ(SP)
n
A number in the range of 0 through 12.
displ
An expression specifying a displacement; the expression can
be preceded by one of the following displacement length
specifiers, which indicate the number of bytes needed to store the
displacement.
B^ Displacement requires one byte.
W^ Displacement requires one word (two bytes).
L^ Displacement requires one longword (four bytes).
If no displacement length specifier precedes the expression, and
the value of the expression is known, the assembler chooses the
smallest number of bytes (one, two, or four) needed to store the
displacement. If no length specifier precedes the expression, and
the value of the expression is unknown, the assembler reserves one
word (two bytes) for the displacement. Note that if the
displacement is either relocatable or defined later in the source
program, the assembler considers it unknown. If the actual
displacement does not fit in the memory reserved, the Linker
displays an error message.
17.8 - General
The address you specify is the address of the operand. The
Linker converts the addressing mode to either relative or absolute
mode. If the address is relocatable, the Linker converts
general mode to relative mode. If the address is absolute,
the Linker converts general mode to absolute mode. You should use
general mode to write position-independent code when you do not
know whether the address is relocatable or absolute. A general
addressing mode operand requires five bytes of storage. You can
use general mode with index mode.
G^address
address
An expression specifying an address.
17.9 - Immediate or Literal
In both immediate and literal mode, the literal specified is
the operand. In immediate mode, the operand is stored in a byte,
word, or longword following the operand specifier. In literal
mode, the operand specifier is the operand.
#literal
The assembler selects immediate or literal mode, depending on
the value of the literal.
^I#literal
This forces immediate mode.
^S#literal
This forces literal mode. The value of the literal must be
an integer in the range 0 through 63, or one of a limited
set of floating-point numbers.
17.10 - Indexed
Index mode is a general register mode that can be used only
in combination with another mode (the base mode). The base mode
can be any addressing mode except register, immediate, literal,
index, or branch. The assembler first evaluates the base mode to
get the base address. To get the operand address, the assembler
multiplies the contents of the index register by the number of
bytes of the operand data type, then adds the result to the base
address.
base-mode[Rx]
base-mode[AP]
base-mode[FP]
base-mode[SP]
base-mode
Any addressing mode except register, immediate, literal, index,
or branch, specifying the base address.
x
A number in the range 0 through 12, specifying the index register.
17.11 - Register
The register contains the operand.
Rn
AP
FP
SP
n
A number in the range 0-12.
For quadword, D_floating, G_floating, or variable-bit field
operands, the operand is the contents of register n
concatenated with the contents of register n+1. For octaword and
H_floating operands, the operand is the contents of register n
concatenated with the contents of registers n+1, n+2, and n+3. In
each of these cases, the least significant bytes of the
operand are in register n and the most significant bytes are in
the highest register used.
The results of the operation are unpredictable if PC is used
in register mode or if the use of a large data type extends the
operand into the PC.
17.12 - Register deferred
The register contains the address of the operand. Register
deferred mode can be used with index mode.
(Rn)
(AP)
(FP)
(SP)
n
A number in the range of 0 through 12.
17.13 - Relative
The address specified is the address of the operand. The
assembler stores the address as a displacement from the PC.
Relative mode can be used with index mode.
address
address
An expression specifying an address; the expression can be
preceded by one of the following displacement length
specifiers, which indicate the number of bytes needed to store the
displacement.
B^ Displacement requires one byte.
W^ Displacement requires one word (two bytes).
L^ Displacement requires one longword (four bytes).
If no displacement length specifier precedes the address
expression, and the value of the expression is known, the
assembler chooses the smallest number of bytes (one, two, or four)
needed to store the displacement. If no length
specifier precedes the address expression, and the value of the
expression is unknown, the assembler uses the default
displacement length. If the address expression is either defined
later in the program or defined in another program section, the
assembler considers the value unknown.
17.14 - Relative deferred
The address specified is the address of the operand address
(a pointer to the operand). The assembler stores the address
specified as a displacement from the PC. Relative deferred mode
can be used with index mode.
@address
address
An expression specifying an address; the expression can be
preceded by one of the following displacement length
specifiers, which indicate the number of bytes needed to store the
displacement.
B^ Displacement requires one byte.
W^ Displacement requires one word (two bytes).
L^ Displacement requires one longword (four bytes).
If no displacement length specifier precedes the address
expression, and the value of the expression is known, the
assembler chooses the smallest number of bytes (one, two, or four)
needed to store the displacement. If no length
specifier precedes the address expression, and the value of the
expression is unknown, the assembler uses the default
displacement length. If the address expression is either defined
later in the program or defined in another program section, the
assembler considers the value unknown.
| 18 - Vector Instructions |
18.1 - Assembler Notation
The assembler notation uses a format that is different from the
operand specifiers for the vector instructions. The number and
order of operands is not the same as the instruction-stream format.
For example, vector-to-vector addition is denoted by the assembler
as "VVADDL V1, V2, V3" instead of "VVADDL X123". The assembler
always generates immediate addressing mode (I#constant) for vector
control word operands. The assembler notation for vector
instructions uses opcode qualifiers to select whether vector
processor exception conditions are enabled or disabled, and to
select the value of cntrl<MTF> in masked, VMERGE, and IOTA
operations. The appropriate opcode is followed by a slash (/). The
following qualifiers are supported:
o The qualifier U enables floating underflow. The qualifier V
enables integer overflow. Both of these qualifiers set cntrl<EXC>.
The default is no vector processor exception conditions are
enabled.
o The qualifier 0 denotes masked operation on elements for which
the Vector Mask Register (VMR) bit is 0. The qualifier 1 denotes
masked operation on elements for which the VMR bit is 1. Both
qualifiers set cntrl<MOE>. The default is no masked operations.
o For the VMERGE and IOTA instructions only, the qualifier 0
denotes cntrl<MTF> is 0. The qualifier 1 denotes cntrl<MTF> is 1.
Cntrl<MTF> is 1 by default. Cntrl<MOE> is not set in this case.
o For the VLD and VGATH instructions only, the qualifier M
indicates modify intent (cntrl<MI> is 1). The default is no modify
intent (cntrl<MI> is 0).
The following examples use several of these qualifiers:
VVADDF/1 V0, V1, V2 ;Operates on elements with mask bit set
VVMULD/0 V0, V1, V2 ;Operates on elements with mask bit clear
VVADDL/V V0, V1, V2 ;Enables exception conditions
(integer overflow here)
VVSUBG/U0 V0, V1, V2 ;Enables floating underflow and
;Operates on elements with mask bit clear
VLDL/M base,#4,V1 ;Indicates Modify Intent
18.2 - IOTA
Generate Compressed Iota Vector
Format:
IOTA [/0|1] stride, Vc
Architecture
Format
opcode cntrl.rw, stride.rl
opcodes
EDFD IOTA Generate Compressed Iota Vector
vector_control_word
1 1 1 1 1
5 4 3 2 1 8 7 4 3 0
+-+-+-+-+-------+-------+-------+
| |M| | | | | |
|0|T|0|0| 0 | 0 | Vc |
| |F| | | | | |
+-+-+-+-+-------+-------+-------+
exceptions
None.
operation
j <- 0
tmp <- 0
FOR i <- 0 TO VLR-1
BEGIN
IF {VMR<i> EQL MTF} THEN
BEGIN
Vc[j]<31:0> <- tmp<31:0>
j <- j + 1
END
tmp <- tmp + stride
END
VCR <- j !return vector count
18.3 - MFVP
Move from Vector Processor
Format:
{ MFVCR }
{ MFVLR }
{ MFVMRLO }
{ } dst
{ MFVMRHI }
{ SYNCH }
{ MSYNCH }
{ }
Architecture
Format
opcode regnum.rw, dst.wl
opcodes
31FD MFVP Move from Vector Processor
vector_control_word
None.
exceptions
None.
operation
CASE regnum OF
0: dst <- ZEXT{VCR}
1: dst <- ZEXT{VLR}
2: dst <- VMR<31:0>
3: dst <- VMR<63:32>
4: SYNC
dst <- UNPREDICTABLE
5: MSYNC
dst <- UNPREDICTABLE
>5: Reserved
END
MFVP instructions that specify reserved values of the regnum
operand produce UNPREDICTABLE results.
18.4 - MTVP
Move to Vector Processor
Format:
{ MTVCR }
{ MTVLR }
{ MTVMRLO } src
{ }
{ MTVMRHI }
Architecture
Format
opcode regnum.rw, src.rl
opcodes
A9FD MTVP Move to Vector Processor
vector_control_word
None.
exceptions
None.
operation
CASE regnum OF
0: VCR <- src
1: VLR <- src
2: VMR<31:0> <- src
3: VMR<63:32> <- src
>3: Reserved
END
Move to Vector Processor instructions that specify reserved values
of the regnum operand produce UNPREDICTABLE results.
18.5 - VADD
Vector Floating Add
Format:
vector + vector:
{ VVADDF }
{ VVADDD } [/U[0|1]] Va, Vb, Vc
{ VVADDG }
{ }
scalar + vector:
{ VSADDF }
{ VSADDD } [/U[0|1]] scalar, Vb, Vc
{ VSADDG }
{ }
Architecture
Format
vector + vector:
opcode cntrl.rw
scalar + vector (F_floating):
opcode cntrl.rw, addend.rl
scalar + vector (D_ and G_floating):
opcode cntrl.rw, addend.rq
opcodes
84FD VVADDF Vector Vector Add F_Floating
85FD VSADDF Vector Scalar Add F_Floating
86FD VVADDD Vector Vector Add D_Floating
87FD VSADDD Vector Scalar Add D_Floating
82FD VVADDG Vector Vector Add G_Floating
83FD VSADDG Vector Scalar Add G_Floating
vector_control_word
1 1 1 1 1
5 4 3 2 1 8 7 4 3 0
+-+-+-+-+-------+-------+-------+
|M|M|E| | Va | | |
|O|T|X|0| or | Vb | Vc |
|E|F|C| | 0 | | |
+-+-+-+-+-------+-------+-------+
exceptions
floating overflow
floating reserved operand
floating underflow
operation
FOR i <- 0 TO VLR-1
IF {{MOE EQL 0} OR {{MOE EQL 1} AND {VMR<i> EQL
BEGIN
IF VVADDF THEN
Vc[i]<31:0> <- Va[i]<31:0> + Vb[i]<31:0>
IF VSADDF THEN
Vc[i]<31:0> <- addend + Vb[i]<31:0>
IF VVADDD OR VVADDG THEN
Vc[i] <- Va[i] + Vb[i]
IF VSADDD OR VSADDG THEN
Vc[i] <- addend + Vb[i]
END
18.6 - VADDL
Vector Integer Add
Format:
vector + vector:
VVADDL [/0|1] Va, Vb, Vc
scalar + vector:
VSADDL [/0|1] scalar, Vb, Vc
Architecture
Format
vector + vector: opcode cntrl.rw
scalar + vector: opcode cntrl.rw, addend.rl
opcodes
80FD VVADDL Vector Vector Add Longword
81FD VSADDL Vector Scalar Add Longword
vector_control_word
1 1 1 1 1
5 4 3 2 1 8 7 4 3 0
+-+-+-+-+-------+-------+-------+
|M|M|E| | Va | | |
|O|T|X|0| or | Vb | Vc |
|E|F|C| | 0 | | |
+-+-+-+-+-------+-------+-------+
exceptions
integer overflow
operation
FOR i <- 0 TO VLR-1
IF {{MOE EQL 0} OR {{MOE EQL 1} AND {VMR<i> EQL MTF}}} THEN
BEGIN
IF VVADDL THEN
Vc[i]<31:0> <- Va[i]<31:0> + Vb[i]<31:0>
IF VSADDL THEN
Vc[i]<31:0> <- addend + Vb[i]<31:0>
END
18.7 - VBIC, VBIS, and VXOR
Vector Logical Functions
Format:
vector op vector:
{ VVBISL }
{ VVXORL } [/V[0|1]] Va, Vb, Vc
{ VVBICL }
{ }
vector op scalar:
{ VSBISL }
{ VSXORL } [/V[0|1]] scalar, Vb, Vc
{ VSBICL }
{ }
Architecture
Format
vector op vector: opcode cntrl.rw
vector op scalar: opcode cntrl.rw, src.rl
opcodes
C8FD VVBISL Vector Vector Bit Set Longword
E8FD VVXORL Vector Vector Exclusive-OR Longword
CCFD VVBICL Vector Vector Bit Clear Longword
C9FD VSBISL Vector Scalar Bit Set Longword
E9FD VSXORL Vector Scalar Exclusive-OR Longword
CDFD VSBICL Vector Scalar Bit Clear Longword
vector_control_word
1 1 1 1 1
5 4 3 2 1 8 7 4 3 0
+-+-+-+-+-------+-------+-------+
|M|M| | | Va | | |
|O|T|0|0| or | Vb | Vc |
|E|F| | | 0 | | |
+-+-+-+-+-------+-------+-------+
exceptions
None.
operation
FOR i <- 0 TO VLR-1
IF {{MOE EQL 0} OR {{MOE EQL 1} AND {VMR<i> EQL MTF}}} THEN
BEGIN
IF VVBISL THEN
Vc[i]<31:0> <- Va[i]<31:0> OR Vb[i]<31:0>
IF VSBISL THEN
Vc[i]<31:0> <- src OR Vb[i]<31:0>
IF VVXORL THEN
Vc[i]<31:0> <- Va[i]<31:0> XOR Vb[i]<31:0>
IF VSXORL THEN
Vc[i]<31:0> <- src XOR Vb[i]<31:0>
IF VVBICL THEN
Vc[i]<31:0> <- {NOT Va[i]<31:0>} AND Vb[i]<31:0>
IF VSBICL THEN
Vc[i]<31:0> <- {NOT src} AND Vb[i]<31:0>
Vc[i]<63:32> <- Vb[i]<63:32>
END
18.8 - VCMP
Vector Floating Compare
Format:
{ VVGTRF }
{ VVGTRD }
{ VVGTRG }
{ }
{ VVEQLF }
{ VVEQLD }
{ VVEQLG }
{ }
{ VVLSSF }
{ VVLSSD }
{ VVLSSG }
vector - vector: { } [/U[0|1]] Va, Vb
{ VVLEQF }
{ VVLEQD }
{ VVLEQG }
{ }
{ VVNEQF }
{ VVNEQD }
{ VVNEQG }
{ }
{ VVGEQF }
{ VVGEQD }
{ VVGEQG }
{ }
{ VSGTRF }
{ VSGTRD }
{ VSGTRG }
{ }
{ VSEQLF }
{ VSEQLD }
{ VSEQLG }
{ }
{ VSLSSF }
{ VSLSSD }
{ VSLSSG }
scalar - vector: { } [/U[0|1]] src, Vb
{ VSLEQF }
{ VSLEQD }
{ VSLEQG }
{ }
{ VSNEQF }
{ VSNEQD }
{ VSNEQG }
{ }
{ VSGEQF }
{ VSGEQD }
{ VSGEQG }
{ }
Architecture
Format
vector - vector:
opcode cntrl.rw
scalar - vector (F_floating):
opcode cntrl.rw, src.rl
scalar - vector (D_ and G_floating):
opcode cntrl.rw, src.rq
opcodes
C4FD VVCMPF Vector Vector Compare F_floating
C5FD VSCMPF Vector Scalar Compare F_floating
C6FD VVCMPD Vector Vector Compare D_floating
C7FD VSCMPD Vector Scalar Compare D_floating
C2FD VVCMPG Vector Vector Compare G_floating
C3FD VSCMPG Vector Scalar Compare G_floating
vector_control_word
1 1 1 1 1
5 4 3 2 1 8 7 4 3 0
+-+-+-+-+-------+-------+-------+
|M|M| | | Va | | cmp |
|O|T|0|0| or | Vb | func |
|E|F| | | 0 | | |
+-+-+-+-+-------+-------+-------+
The condition being tested is determined by cntrl<2:0>, as
follows:
Value of
cntrl<2:0> Meaning
0 Greater than
1 Equal
2 Less than
3 Reserved
4 Less than or equal
5 Not equal
6 Greater than or equal
7 Reserved
NOTE
Cntrl<3> should be zero; if it is set, the results of the
instruction are UNPREDICTABLE.
exceptions
floating reserved operand
operation
FOR i <- 0 TO VLR-1
IF {{MOE EQL 0} OR {{MOE EQL 1} AND {VMR<i> EQL MTF}}} THEN
BEGIN
IF VVCMPF THEN
IF Va[i]<31:0> SIGNED_RELATION Vb[i]<31:0> THEN
VMR<i> <- 1
ELSE
VMR<i> <- 0
IF VVCMPD OR VVCMPG THEN
IF Va[i] SIGNED_RELATION Vb[i] THEN
VMR<i> <- 1
ELSE
VMR<i> <- 0
IF VSCMPF THEN
IF src SIGNED_RELATION Vb[i]<31:0> THEN
VMR<i> <- 1
ELSE
VMR<i> <- 0
IF VSCMPD OR VSCMPG THEN
IF src SIGNED_RELATION Vb[i] THEN
VMR<i> <- 1
ELSE
VMR<i> <- 0
END
18.9 - VCMPL
Vector Integer Compare
Format:
vector - vector:
{ VVGTRL }
{ VVEQLL }
{ VVLSSL }
{ } [/0|1] Va, Vb
{ VVLEQL }
{ VVNEQL }
{ VVGEQL }
{ }
scalar - vector:
{ VSGTRL }
{ VSEQLL }
{ VSLSSL }
{ } [/0|1] src, Vb
{ VSLEQL }
{ VSNEQL }
{ VSGEQL }
{ }
Architecture
Format
vector + vector: opcode cntrl.rw
scalar + vector: opcode cntrl.rw, addend.rl
opcodes
80FD VVADDL Vector Vector Add Longword
81FD VSADDL Vector Scalar Add Longword
vector_control_word
1 1 1 1 1
5 4 3 2 1 8 7 4 3 0
+-+-+-+-+-------+-------+-------+
|M|M|E| | Va | | |
|O|T|X|0| or | Vb | Vc |
|E|F|C| | 0 | | |
+-+-+-+-+-------+-------+-------+
exceptions
integer overflow
operation
FOR i <- 0 TO VLR-1
IF {{MOE EQL 0} OR {{MOE EQL 1} AND {VMR<i> EQL MTF}}} THEN
BEGIN
IF VVADDL THEN
Vc[i]<31:0> <- Va[i]<31:0> + Vb[i]<31:0>
IF VSADDL THEN
Vc[i]<31:0> <- addend + Vb[i]<31:0>
END
18.10 - VDIV
Vector Floating Divide
Format:
vector/vector:
{ VVDIVF }
{ VVDIVD } [/U[0|1]] Va, Vb, Vc
{ VVDIVG }
{ }
scalar/vector:
{ VSDIVF }
{ VSDIVD } [/U[0|1]] scalar, Vb, Vc
{ VSDIVG }
{ }
Architecture
Format
vector/vector:
opcode cntrl.rw
scalar/vector (F_floating):
opcode cntrl.rw, divd.rl
scalar/vector (D_ and G_floating):
opcode cntrl.rw, divd.rq
opcodes
ACFD VVDIVF Vector Vector Divide F_floating
ADFD VSDIVF Vector Scalar Divide F_floating
AEFD VVDIVD Vector Vector Divide D_floating
AFFD VSDIVD Vector Scalar Divide D_floating
AAFD VVDIVG Vector Vector Divide G_floating
ABFD VSDIVG Vector Scalar Divide G_floating
vector_control_word
1 1 1 1 1
5 4 3 2 1 8 7 4 3 0
+-+-+-+-+-------+-------+-------+
|M|M|E| | Va | | |
|O|T|X|0| or | Vb | Vc |
|E|F|C| | 0 | | |
+-+-+-+-+-------+-------+-------+
exceptions
floating divide by zero
floating overflow
floating reserved operand
floating underflow
operation
FOR i <- 0 TO VLR-1
IF {{MOE EQL 0} OR {{MOE EQL 1} AND {VMR<i> EQL MTF}}} THEN
BEGIN
IF VVDIVF THEN
Vc[i]<31:0> <- Va[i]<31:0> / Vb[i]<31:0>
IF VSDIVF THEN
Vc[i]<31:0> <- divd / Vb[i]<31:0>
IF VVDIVD OR VVDIVG THEN
Vc[i] <- Va[i] / Vb[i]
IF VSDIVD OR VSDIVG THEN
Vc[i] <- divd / Vb[i]
END
18.11 - VGATH
Gather Memory Data into Vector Register
Format:
VGATHL [/M[0|1]] base, Vb, Vc
VGATHQ [/M[0|1]] base, Vb, Vc
Architecture
Format
opcode cntrl.rw, base.ab
opcodes
35FD VGATHL Gather Longword Vector from Memory to Vector
Register
37FD VGATHQ Gather Quadword Vector from Memory to Vector
Register
vector_control_word
1 1 1 1 1
5 4 3 2 1 8 7 4 3 0
+-+-+-+-+-------+-------+-------+
|M|M|M| | | | |
|O|T|I|0| 0 | Vb | Vc |
|E|F| | | | | |
+-+-+-+-+-------+-------+-------+
exceptions
access control violation
translation not valid
vector alignment
operation
FOR i <- 0 TO VLR-1
BEGIN
addr <- base + Vb[i]<31:0>
IF {{MOE EQL 0} OR {{MOE EQL 1} AND {VMR<i> EQL MTF}}} THEN
BEGIN
IF {addr unaligned} THEN
{Vector Alignment Exception}
IF VGATHL THEN
Vc[i] <- (addr)<31:0>
IF VGATHQ THEN
Vc[i] <- (addr)<63:0>
END
END
18.12 - VLD
Load Memory Data into Vector Register
Format:
VLDL [/M[0|1]] base, stride, Vc
VLDQ [/M[0|1]] base, stride, Vc
Architecture
Format
opcode cntrl.rw, base.ab, stride.rl
opcodes
34FD VLDL Load Longword Vector from Memory to Vector
Register
36FD VLDQ Load Quadword Vector from Memory to Vector
Register
vector control word
1 1 1 1 1
5 4 3 2 1 8 7 4 3 0
+-+-+-+-+-------+-------+-------+
|M|M|M| | | | |
|O|T|I|0| 0 | 0 | Vc |
|E|F| | | | | |
+-+-+-+-+-------+-------+-------+
exceptions
access control violation
translation not valid
vector alignment
operation
addr <- base
FOR i <- 0 TO VLR-1
BEGIN
IF {{MOE EQL 0} OR {{MOE EQL 1} AND {VMR<i> EQL MTF}}} THEN
BEGIN
IF {addr unaligned} THEN
{Vector Alignment Exception}
IF VLDL THEN
Vc[i] <- (addr)<31:0>
IF VLDQ THEN
Vc[i] <- (addr)<63:0>
END
addr <- addr + stride !Increment by stride
END
18.13 - VMERGE
Vector Merge
Format:
vector vector merge:
VVMERGE [/0|1] Va, Vb, Vc
vector scalar merge:
{ VSMERGE }
{ VSMERGEF }
{ VSMERGED } [/0|1] src, Vb, Vc
{ }
{ VSMERGEG }
Architecture
Format
vector-vector: opcode cntrl.rw
vector-scalar: opcode cntrl.rw,src.rq
opcodes
EEFD VVMERGE Vector Vector Merge
EFFD VSMERGE Vector Scalar Merge
vector_control_word
1 1 1 1 1
5 4 3 2 1 8 7 4 3 0
+-+-+-+-+-------+-------+-------+
| |M| | | Va | | |
|0|T|0|0| or | Vb | Vc |
| |F| | | 0 | | |
+-+-+-+-+-------+-------+-------+
exceptions
None.
operation
FOR i <- 0 TO VLR-1
BEGIN
IF VVMERGE THEN
IF {VMR<i> EQL MTF} THEN
Vc[i] <- Va[i]
ELSE
Vc[i] <- Vb[i]
IF VSMERGE THEN
IF {VMR<i> EQL MTF} THEN
Vc[i] <- src
ELSE
Vc[i] <- Vb[i]
END
18.14 - VMUL
Vector Floating Multiply
Format:
vector * vector:
{ VVMULF }
{ VVMULD } [/U[0|1]] Va, Vb, Vc
{ VVMULG }
{ }
scalar * vector:
{ VSMULF }
{ VSMULD } [/U[0|1]] scalar, Vb, Vc
{ VSMULG }
{ }
Architecture
Format
vector * vector:
opcode cntrl.rw
scalar * vector (F_floating):
opcode cntrl.rw, mulr.rl
scalar * vector (D_ and G_floating):
opcode cntrl.rw, mulr.rq
opcodes
A4FD VVMULF Vector Vector Multiply F_floating
A5FD VSMULF Vector Scalar Multiply F_floating
A6FD VVMULD Vector Vector Multiply F_floating
A7FD VSMULD Vector Scalar Multiply D_floating
A2FD VVMULG Vector Vector Multiply G_floating
A3FD VSMULG Vector Scalar Multiply G_floating
vector_control_word
1 1 1 1 1
5 4 3 2 1 8 7 4 3 0
+-+-+-+-+-------+-------+-------+
|M|M|E| | Va | | |
|O|T|X|0| or | Vb | Vc |
|E|F|C| | 0 | | |
+-+-+-+-+-------+-------+-------+
exceptions
floating overflow
floating reserved operand
floating underflow
operation
FOR i <- 0 TO VLR-1
IF {{MOE EQL 0} OR {{MOE EQL 1} AND {VMR<i> EQL MTF}}} THEN
BEGIN
IF VVMULF THEN
Vc[i]<31:0> <- Va[i]<31:0> * Vb[i]<31:0>
IF VSMULF THEN
Vc[i]<31:0> <- mulr * Vb[i]<31:0>
IF VVMULD OR VVMULG THEN
Vc[i] <- Va[i] * Vb[i]
IF VSMULD OR VSMULG THEN
Vc[i] <- mulr * Vb[i]
END
18.15 - VMULL
Vector Integer Multiply
Format:
vector * vector:
VVMULL [/V[0|1]] Va, Vb, Vc
scalar * vector:
VSMULL [/V[0|1]] scalar, Vb, Vc
Architecture
Format
vector * vector: opcode cntrl.rw
scalar * vector: opcode cntrl.rw, mulr.rl
opcodes
A0FD VVMULL Vector Vector Multiply Longword
A1FD VSMULL Vector Scalar Multiply Longword
vector_control_word
1 1 1 1 1
5 4 3 2 1 8 7 4 3 0
+-+-+-+-+-------+-------+-------+
|M|M|E| | Va | | |
|O|T|X|0| or | Vb | Vc |
|E|F|C| | 0 | | |
+-+-+-+-+-------+-------+-------+
exceptions
integer overflow
operation
FOR i <- 0 TO VLR-1
IF {{MOE EQL 0} OR {{MOE EQL 1} AND {VMR<i> EQL MTF}}} THEN
BEGIN
IF VVMULL THEN
Vc[i]<31:0> <- Va[i]<31:0> * Vb[i]<31:0>
IF VSMULL THEN
Vc[i]<31:0> <- mulr * Vb[i]<31:0>
END
18.16 - VSCAT
Scatter Vector Register Data into Memory
Format:
VSCATL [/0|1] Vc, base, Vb
VSCATQ [/0|1] Vc, base, Vb
Architecture
Format
opcode cntrl.rw, base.ab
opcodes
9DFD VSCATL Scatter Longword Vector from Vector Register to
Memory
9FFD VSCATQ Scatter Quadword Vector from Vector Register to
Memory
vector_control_word
1 1 1 1 1
5 4 3 2 1 8 7 4 3 0
+-+-+-+-+-------+-------+-------+
|M|M| | | | | |
|O|T|0|0| 0 | Vb | Vc |
|E|F| | | | | |
+-+-+-+-+-------+-------+-------+
exceptions
access control violation
translation not valid
vector alignment
modify
operation
FOR i <- 0 TO VLR-1
BEGIN
addr <- base + Vb[i]<31:0>
IF {{MOE EQL 0} OR {{MOE EQL 1} AND {VMR<i> EQL MTF}}} THEN
BEGIN
IF {addr unaligned} THEN
{Vector Alignment Exception}
IF VSCATL THEN
(addr)<31:0> <- Vc[i]<31:0>
IF VSCATQ THEN
(addr)<63:0> <- Vc[i]
END
END
18.17 - VSL
Vector Shift Logical
Format:
vector shift count:
{ VVSRLL }
{ VVSLLL } [/V[0|1]] Va, Vb, Vc
{ }
scalar shift count:
{ VSSRLL }
{ VSSLLL } [/V[0|1]] cnt, Vb, Vc
{ }
Architecture
Format
vector shift count: opcode cntrl.rw
scalar shift count: opcode cntrl.rw, cnt.rl
opcodes
E0FD VVSRLL Vector Vector Shift Right Logical Longword
E4FD VVSLLL Vector Vector Shift Left Logical Longword
E1FD VSSRLL Vector Scalar Shift Right Logical Longword
E5FD VSSLLL Vector Scalar Shift Left Logical Longword
vector_control_word
1 1 1 1 1
5 4 3 2 1 8 7 4 3 0
+-+-+-+-+-------+-------+-------+
|M|M| | | Va | | |
|O|T|0|0| or | Vb | Vc |
|E|F| | | 0 | | |
+-+-+-+-+-------+-------+-------+
exceptions
None.
operation
FOR i <- 0 TO VLR-1
IF {{MOE EQL 0} OR {{MOE EQL 1} AND {VMR<i> EQL MTF}}} THEN
BEGIN
IF VVSRLL THEN
Vc[i]<31:0> <- RIGHT_SHIFT(Vb[i]<31:0>, Va[i]<4:0>)
IF VVSLLL THEN
Vc[i]<31:0> <- LEFT_SHIFT(Vb[i]<31:0>, Va[i]<4:0>)
IF VSSRLL THEN
Vc[i]<31:0> <- RIGHT_SHIFT(Vb[i]<31:0>, cnt<4:0>)
IF VSSLLL THEN
Vc[i]<31:0> <- LEFT_SHIFT(Vb[i]<31:0>, cnt<4:0>)
END
18.18 - VST
Store Vector Register Data into Memory
Format:
VSTL [/0|1] Vc, base, stride
VSTQ [/0|1] Vc, base, stride
Architecture
Format
opcode cntrl.rw, base.ab, stride.rl
opcodes
9CFD VSTL Store Longword Vector from Vector Register to
Memory
9EFD VSTQ Store Quadword Vector from Vector Register to
Memory
vector_control_word
1 1 1 1 1
5 4 3 2 1 8 7 4 3 0
+-+-+-+-+-------+-------+-------+
|M|M| | | | | |
|O|T|0|0| 0 | 0 | Vc |
|E|F| | | | | |
+-+-+-+-+-------+-------+-------+
exceptions
access control violation
translation not valid
vector alignment
modify
operation
addr <- base
FOR i <- 0 TO VLR-1
BEGIN
IF {{MOE EQL 0} OR {{MOE EQL 1} AND {VMR<i> EQL MTF}}} THEN
BEGIN
IF {addr unaligned} THEN
{Vector Alignment Exception}
IF VSTL THEN
(addr)<31:0> <- Vc[i]<31:0>
IF VSTQ THEN
(addr)<63:0> <- Vc[i]
END
addr <- addr + stride !Increment by stride
END
18.19 - VSUB
Vector Floating Subtract
Format:
vector - vector:
{ VVSUBF }
{ VVSUBD } [/U[0|1]] Va, Vb, Vc
{ VVSUBG }
{ }
scalar - vector:
{ VSSUBF }
{ VSSUBD } [/U[0|1]] scalar, Vb, Vc
{ VSSUBG }
{ }
Architecture
Format
vector - vector:
opcode cntrl.rw
scalar - vector (F_floating):
opcode cntrl.rw, min.rl
scalar - vector (D_ and G_floating):
opcode cntrl.rw, min.rq
opcodes
8CFD VVSUBF Vector Vector Subtract F_floating
8DFD VSSUBF Vector Scalar Subtract F_floating
8EFD VVSUBD Vector Vector Subtract D_floating
8FFD VSSUBD Vector Scalar Subtract D_floating
8AFD VVSUBG Vector Vector Subtract G_floating
8BFD VSSUBG Vector Scalar Subtract G_floating
vector_control_word
1 1 1 1 1
5 4 3 2 1 8 7 4 3 0
+-+-+-+-+-------+-------+-------+
|M|M|E| | Va | | |
|O|T|X|0| or | Vb | Vc |
|E|F|C| | 0 | | |
+-+-+-+-+-------+-------+-------+
exceptions
floating overflow
floating reserved operand
floating underflow
operation
FOR i <- 0 TO VLR-1
IF {{MOE EQL 0} OR {{MOE EQL 1} AND {VMR<i> EQL MTF}}} THEN
BEGIN
IF VVSUBF THEN
Vc[i]<31:0> <- Va[i]<31:0> - Vb[i]<31:0>
IF VSSUBF THEN
Vc[i]<31:0> <- min - Vb[i]<31:0>
IF VVSUBD OR VVSUBG THEN
Vc[i] <- Va[i] - Vb[i]
IF VSSUBD OR VSSUBG THEN
Vc[i] <- min - Vb[i]
END
18.20 - VSUBL
Vector Integer Subtract
Format:
vector - vector:
VVSUBL [/V[0|1]] Va, Vb, Vc
scalar - vector:
VSSUBL [/V[0|1]] scalar, Vb, Vc
Architecture
Format
vector - vector: opcode cntrl.rw
scalar - vector: opcode cntrl.rw, min.rl
opcodes
88FD VVSUBL Vector Vector Subtract Longword
89FD VSSUBL Vector Scalar Subtract Longword
vector_control_word
1 1 1 1 1
5 4 3 2 1 8 7 4 3 0
+-+-+-+-+-------+-------+-------+
|M|M|E| | Va | | |
|O|T|X|0| or | Vb | Vc |
|E|F|C| | 0 | | |
+-+-+-+-+-------+-------+-------+
exceptions
integer overflow
operation
FOR i <- 0 TO VLR-1
IF {{MOE EQL 0} OR {{MOE EQL 1} AND {VMR<i> EQL MTF}}} THEN
BEGIN
IF VVSUBL THEN
Vc[i]<31:0> <- Va[i]<31:0> - Vb[i]<31:0>
IF VSSUBL THEN
Vc[i]<31:0> <- min - Vb[i]<31:0>
END
18.21 - VSYNC
Synchronize Vector Memory Access
Format:
VSYNCH
Architecture
Format
opcode regnum.rw
opcodes
A8FD VSYNC Synchronize Vector Memory Access
vector_control_word
None.
exceptions
None.
operation
CASE regnum 0: VSYNC
>0: Reserved
END
Synchronize Vector Memory Access instructions that specify
reserved values of the regnum operand produce UNPREDICTABLE
results.
18.22 - VVCVT
Vector Convert
Format:
{ VVCVTLF }
{ VVCVTLD }
{ VVCVTLG }
{ }
{ VVCVTFL }
{ VVCVTRFL }
{ VVCVTFD }
{ }
{ VVCVTFG } [/U[0|1]] Vb, Vc
{ VVCVTDL }
{ VVCVTDF }
{ }
{ VVCVTRDL }
{ VVCVTGL }
{ VVCVTGF }
{ }
{ VVCVTRGL }
Architecture
Format
opcode cntrl.rw
opcodes
ECFD VVCVT Vector Convert
vector_control_word
1 1 1 1 1
5 4 3 2 1 8 7 4 3 0
+-+-+-+-+-------+-------+-------+
|M|M|E| | cvt | | |
|O|T|X|0| func | Vb | Vc |
|E|F|C| | | | |
+-+-+-+-+-------+-------+-------+
Cntrl<11:8> specifies the conversion to be performed, as follows:
cntrl<11:8> Meaning
1 1 1 1 CVTRGL (Convert Rounded G_Floating to Longword)
1 1 1 0 Reserved
1 1 0 1 CVTGF (Convert Rounded G_Floating to F_Floating)
1 1 0 0 CVTGL (Convert Truncated G_Floating to Longword)
1 0 1 1 Reserved
1 0 1 0 CVTRD (Convert Rounded D_Floating to Longword)
1 0 0 1 CVTDF (Convert Rounded D_Floating to F_Floating)
1 0 0 0 CVTDL (Convert Truncated D_Floating to Longword)
0 1 1 1 CVTFG (Convert F_Floating to G_Floating (exact))
0 1 1 0 CVTFD (Convert F_Floating to D_Floating (exact))
0 1 0 1 CVTRF (Convert Rounded F_Floating to Longword)
0 1 0 0 CVTFL (Convert Truncated F_Floating to Longword)
0 0 1 1 CVTLG (Convert Longword to G_Floating (exact))
0 0 1 0 CVTLD (Convert Longword to D_Floating (exact))
0 0 0 1 CVTLF (Convert Rounded Longword to F_Floating)
0 0 0 0 Reserved
exceptions
floating overflow
floating reserved operand
floating underflow
integer overflow
operation
FOR i <- 0 TO VLR-1
IF {{MOE EQL 0} OR {{MOE EQL 1} AND {VMR<i> EQL MTF}}} THEN
Vc[i] <- {conversion of Vb[i]}
| 19 - Examples |
1.$ MACRO/LIST CYGNUS, LYRA/OBJECT=LYRAN + MYLIB/LIBRARY
In this example, the MACRO command requests two separate
assemblies. Using MAR as the default file type, MACRO assembles
CYGNUS.MAR to produce CYGNUS.LIS and CYGNUS.OBJ. Then it
assembles LYRA.MAR and creates a listing file named LYRA.LIS
and an object module named LYRAN.OBJ. The default output file
type for a listing is LIS.
The command requests the search of the MYLIB library file in
the current directory for macro definitions.
2.$ MACRO ORION
MACRO assembles the file ORION.MAR and creates an object file
named ORION.OBJ. Executing the command in a batch job causes
MACRO to create a listing file named ORION.LIS.
3.$ MACRO ALPHA/LIST+MYLIB/LIBRARY-
_$ + [TEST]OLDLIB/LIBRARY + []BETA
$ PRINT ALPHA
MACRO concatenates the files ALPHA.MAR and BETA.MAR to produce
an object file named ALPHA.OBJ and a listing file named
ALPHA.LIS. The command line requests the search of libraries
MYLIB.MLB (in the current default directory) and OLDLIB.MLB (in
the directory [TEST]) for macro definitions. When macro calls
are found in BETA.MAR, MACRO searches the libraries OLDLIB,
MYLIB, and the system library STARLET.MLB, in that order, for
the definitions.
The PRINT command prints the listing file ALPHA.LIS.
4.$ MACRO DELTA+TESTLIB/LIBRARY, ALPHA+MYLIB/LIBRARY
MACRO requests two separate assemblies. MACRO searches
TESTLIB.MLB and the system library STARLET.MLB for macro
definitions when macro calls are found in DELTA.MAR, and
searches MYLIB.MLB and the system library STARLET.MLB for macro
definitions when macro calls are found in ALPHA.MAR.
|
|
