VMS Help MACRO, VAX MACRO Assembler, Vector Instructions, Assembler Notation  *Conan The Librarian (sorry for the slow response - running on an old VAX)

    The assembler notation uses a format that is different from the
    operand specifiers for the vector instructions. The number and
    order of operands is not the same as the instruction-stream format.
    For example, vector-to-vector addition is denoted by the assembler
    as "VVADDL V1, V2, V3" instead of "VVADDL X123". The assembler
    always generates immediate addressing mode (I#constant) for vector
    control word operands. The assembler notation for vector
    instructions uses opcode qualifiers to select whether vector
    processor exception conditions are enabled or disabled, and to
    select the value of cntrl<MTF> in masked, VMERGE, and IOTA
    operations. The appropriate opcode is followed by a slash (/). The
    following qualifiers are supported:

    o  The qualifier U enables floating underflow. The qualifier V
       enables integer overflow. Both of these qualifiers set cntrl<EXC>.
       The default is no vector processor exception conditions are
       enabled.

    o  The qualifier 0 denotes masked operation on elements for which
       the Vector Mask Register (VMR) bit is 0. The qualifier 1 denotes
       masked operation on elements for which the VMR bit is 1. Both
       qualifiers set cntrl<MOE>. The default is no masked operations.

    o  For the VMERGE and IOTA instructions only, the qualifier 0
       denotes cntrl<MTF> is 0. The qualifier 1 denotes cntrl<MTF> is 1.
       Cntrl<MTF> is 1 by default. Cntrl<MOE> is not set in this case.

    o  For the VLD and VGATH instructions only, the qualifier M
       indicates modify intent (cntrl<MI> is 1). The default is no modify
       intent (cntrl<MI> is 0).

    The following examples use several of these qualifiers:

        VVADDF/1   V0, V1, V2   ;Operates on elements with mask bit set
        VVMULD/0   V0, V1, V2   ;Operates on elements with mask bit clear
        VVADDL/V   V0, V1, V2   ;Enables exception conditions
                                 (integer overflow here)
        VVSUBG/U0  V0, V1, V2   ;Enables floating underflow and
                                ;Operates on elements with mask bit clear
        VLDL/M     base,#4,V1   ;Indicates Modify Intent