/********************************************************************************************************************************/ /* Created: 15-MAR-2001 23:38:16 by OpenVMS SDL EV1-33 */ /* Source: 15-MAR-2001 23:34:21 _$11$DUA933:[BUILD.SDL]STARDEFQZ.SDI;1 */ /********************************************************************************************************************************/ /*** MODULE $XRVDEF ***/ #ifndef __XRVDEF_LOADED #define __XRVDEF_LOADED 1 #pragma nostandard #ifdef __cplusplus extern "C" { #define __unknown_params ... #else #define __unknown_params #endif #if !defined(__VAXC) && !defined(VAXC) #define __struct struct #define __union union #else #define __struct variant_struct #define __union variant_union #endif #define XRV$_PR_VIADR 157 /* Vector indirect address */ #define XRV$_PR_VIDLO 158 /* Vector indirect data low */ #define XRV$_PR_VIDHI 159 /* Vector indirect data hi */ /*+ */ #define XRV$_VIR_VREG0 0 /* Vector Register 0 */ #define XRV$_VIR_VREG1 64 /* Vector Register 1 */ #define XRV$_VIR_VREG2 128 /* Vector Register 2 */ #define XRV$_VIR_VREG3 192 /* Vector Register 3 */ #define XRV$_VIR_VREG4 256 /* Vector Register 4 */ #define XRV$_VIR_VREG5 320 /* Vector Register 5 */ #define XRV$_VIR_VREG6 384 /* Vector Register 6 */ #define XRV$_VIR_VREG7 448 /* Vector Register 7 */ #define XRV$_VIR_VREG8 512 /* Vector Register 8 */ #define XRV$_VIR_VREG9 576 /* Vector Register 9 */ #define XRV$_VIR_VREG10 640 /* Vector Register 10 */ #define XRV$_VIR_VREG11 704 /* Vector Register 11 */ #define XRV$_VIR_VREG12 768 /* Vector Register 12 */ #define XRV$_VIR_VREG13 832 /* Vector Register 13 */ #define XRV$_VIR_VREG14 832 /* Vector Register 14 */ #define XRV$_VIR_VREG15 960 /* Vector Register 15 */ #define XRV$_VIR_ALU_OP 1088 /* Arithmetic opcode */ #define XRV$_VIR_ALU_SCOP_LO 1096 /* Scalar operand LO */ #define XRV$_VIR_ALU_SCOP_HI 1100 /* Scalar operand HI */ #define XRV$_VIR_ALU_MASK_LO 1100 /* Vector mask LO */ #define XRV$_VIR_ALU_MASK_HI 1104 /* Vector mask HI */ #define XRV$_VIR_ALU_EXC 1108 /* ALU exception reg. */ /* Location 458 reserved */ #define XRV$_VIR_ALU_DIAG_CTRL 1116 /* Diagnostic control */ #define XRV$M_VIR_ALU_DIAG_CTRL_ISL 0x1 #define XRV$M_VIR_ALU_DIAG_CTRL_ISH 0x2 #define XRV$M_VIR_ALU_DIAG_CTRL_IBL 0x4 #define XRV$M_VIR_ALU_DIAG_CTRL_IBH 0x8 #define XRV$M_VIR_ALU_DIAG_CTRL_ICL 0x10 #define XRV$M_VIR_ALU_DIAG_CTRL_ICH 0x20 #define XRV$M_VIR_ALU_DIAG_CTRL_ICI 0x40 #define XRV$M_VIR_ALU_DIAG_CTRL_ABE 0x100 #define XRV$M_VIR_ALU_DIAG_CTRL_CPE 0x200 #define XRV$M_VIR_ALU_DIAG_CTRL_IFO 0x400 #define XRV$_VIR_VERSE_CHIP0 1116 /* Verse Chip 0 reg. */ #define XRV$_VIR_VERSE_CHIP1 1117 /* Verse Chip 1 reg. */ #define XRV$_VIR_VERSE_CHIP2 1118 /* Verse Chip 2 reg. */ #define XRV$_VIR_VERSE_CHIP3 1119 /* Verse Chip 3 reg. */ #define XRV$_VIR_VCTL_CALU 1152 /* Current ALU instr. */ #define XRV$_VIR_VCTL_DALU 1153 /* Defered ALU instr. */ #define XRV$_VIR_VCTL_COP_LO 1154 /* Current ALU oper. LO */ #define XRV$_VIR_VCTL_COP_HI 1155 /* Current ALU oper. HI */ #define XRV$_VIR_VCTL_DOP_LO 1156 /* Defered ALU oper. LO */ #define XRV$_VIR_VCTL_DOP_HI 1157 /* Defered ALU oper. HI */ #define XRV$_VIR_VCTL_LS 1158 /* Load/Store instr. */ #define XRV$_VIR_VCTL_STRIDE 1159 /* Load/Store stride */ #define XRV$_VIR_VCTL_ILL 1160 /* Illegal instruction */ #define XRV$_VIR_VCTL_CSR 1161 /* Controller Status */ #define XRV$M_VIR_VCTL_CSR_LSS 0x1 #define XRV$M_VIR_VCTL_CSR_LSH 0x2 #define XRV$M_VIR_VCTL_CSR_CDS 0x4 #define XRV$M_VIR_VCTL_CSR_CDH 0x8 #define XRV$M_VIR_VCTL_CSR_VIS 0x10 #define XRV$M_VIR_VCTL_CSR_VIH 0x20 #define XRV$M_VIR_VCTL_CSR_ISE 0x40 #define XRV$M_VIR_VCTL_CSR_STF 0x200 #define XRV$M_VIR_VCTL_CSR_ETF 0x400 #define XRV$M_VIR_VCTL_CSR_VHE 0x800 #define XRV$M_VIR_VCTL_CSR_SEE 0x40000 #define XRV$M_VIR_VCTL_CSR_HEE 0x80000 #define XRV$M_VIR_VCTL_CSR_FRL 0x100000 #define XRV$M_VIR_VCTL_CSR_FRH 0x200000 #define XRV$M_VIR_VCTL_CSR_FDL 0x400000 #define XRV$M_VIR_VCTL_CSR_FDH 0x800000 #define XRV$M_VIR_VCTL_CSR_FSE 0x10000000 #define XRV$M_VIR_VCTL_CSR_FVP 0x20000000 #define XRV$M_VIR_VCTL_CSR_IMP 0x80000000 #define XRV$_VIR_MOD_REV 1162 /* Module revision level */ #define XRV$M_VIR_MOD_REV_FIXUP_LS 0x80 #define XRV$_VIR_LSX_P0BR 1280 /* P0 base register */ #define XRV$_VIR_LSX_P0LR 1281 /* P0 length register */ #define XRV$_VIR_LSX_P1BR 1282 /* P1 base register */ #define XRV$_VIR_LSX_P1LR 1283 /* P1 length register */ #define XRV$_VIR_LSX_SBR 1284 /* System base register */ #define XRV$_VIR_LSX_SLR 1285 /* System len. register */ /* 506-507 reserved */ #define XRV$_VIR_LSX_EXC 1288 /* L/S exception reg. */ #define XRV$_VIR_LSX_TBCSR 1289 /* TB control register */ #define XRV$_VIR_LSX_MAPEN 1290 /* Map enable register */ #define XRV$_VIR_LSX_TBIA 1291 /* TB invalidate all */ #define XRV$_VIR_LSX_TBIS 1292 /* TB invalidate single */ /* 50D-50F reserved */ #define XRV$_VIR_LSX_MASKLO 1296 /* Mask register LO */ #define XRV$_VIR_LSX_MASKHI 1297 /* Mask register HI */ #define XRV$_VIR_LSX_STRIDE 1298 /* L/S stride register */ #define XRV$_VIR_LSX_INST 1299 /* L/S instruction */ #define XRV$_VIR_LSX_AGDIAG 1300 /* AG diagnostic reg. */ /* 515-517 reserved */ #define XRV$_VIR_LSX_XBE 1304 /* XMI bus error reg. */ #define XRV$_VIR_LSX_XFADR 1305 /* XMI failed addr reg. */ /* 51A-51F reserved */ #define XRV$_VIR_LSX_CCSR 1312 /* Cache control reg. */ /* 521-527 reserved */ #define XRV$M_VIR_LSX_CCSR_ACT 0x1 #define XRV$M_VIR_LSX_CCSR_CPE 0x200 #define XRV$M_VIR_LSX_CCSR_XSE 0x400 #define XRV$M_VIR_LSX_CCSR_XHE 0x800 #define XRV$M_FILL_7 0x7000 #define XRV$M_VIR_LSX_CCSR_CEE 0x8000 #define XRV$M_VIR_LSX_CCSR_SEE 0x10000 #define XRV$M_VIR_LSX_CCSR_ENA 0x20000 #define XRV$M_VIR_LSX_CCSR_HIT 0x40000 #define XRV$M_VIR_LSX_CCSR_FHT 0x80000 #define XRV$M_VIR_LSX_CCSR_FLU 0x100000 #define XRV$M_FILL_8 0x600000 #define XRV$M_VIR_LSX_CCSR_FRL 0x800000 #define XRV$M_VIR_LSX_CCSR_FDL 0x1000000 #define XRV$M_VIR_LSX_CCSR_FDH 0x2000000 #define XRV$M_VIR_LSX_CCSR_IVS 0x4000000 #define XRV$M_VIR_LSX_CCSR_IPS 0x8000000 #define XRV$M_VIR_LSX_CCSR_DXT 0x10000000 #define XRV$M_VIR_LSX_CCSR_IDV 0x20000000 #define XRV$M_VIR_LSX_CCSR_IDP 0x40000000 #define XRV$M_VIR_LSX_CCSR_DTC 0x80000000 #define XRV$_VIR_LSX_WBDIAG 1320 /* WB diagnostic reg */ #define XRV$_VIR_LSX_VMAC1 1321 /* Memory active start */ #define XRV$_VIR_LSX_VMAC2 1322 /* Memory active check */ /* 52B-51F reserved */ #define XRV$_VIR_LSX_TAG 1328 /* TB tag register */ #define XRV$_VIR_LSX_PTE 1329 /* TB PTE register */ /* 532-53F reserved */ union xrvdef { /*+ */ /* Internal Processor register definitions for XRV Vector Processor */ /*- */ /* Indirect register definitions for XRV Vector Processor */ /*- */ __struct { unsigned xrv$v_vir_alu_diag_ctrl_isl : 1; /* Invert scalar operand parity low */ unsigned xrv$v_vir_alu_diag_ctrl_ish : 1; /* Invert scalar operand parity high */ unsigned xrv$v_vir_alu_diag_ctrl_ibl : 1; /* Invert B parity low */ unsigned xrv$v_vir_alu_diag_ctrl_ibh : 1; /* Invert B parity high */ unsigned xrv$v_vir_alu_diag_ctrl_icl : 1; /* Invert CD bus parity low */ unsigned xrv$v_vir_alu_diag_ctrl_ich : 1; /* Invert CD bus parity high */ unsigned xrv$v_vir_alu_diag_ctrl_ici : 1; /* Invert internally generated CP parity */ unsigned xrv$$$_fill_1 : 1; unsigned xrv$v_vir_alu_diag_ctrl_abe : 1; /* AB parity error */ unsigned xrv$v_vir_alu_diag_ctrl_cpe : 1; /* C bus parity error */ unsigned xrv$v_vir_alu_diag_ctrl_ifo : 1; /* Illegal FAVOR opcode */ unsigned xrv$$$_fill_2 : 21; } xrvr_xrv_vir_alu_diag_ctrl_bits; __struct { unsigned xrv$v_vir_vctl_csr_lss : 1; /* Load store chip soft error */ unsigned xrv$v_vir_vctl_csr_lsh : 1; /* Load store chip hard error */ unsigned xrv$v_vir_vctl_csr_cds : 1; /* Soft internal bus parity error */ unsigned xrv$v_vir_vctl_csr_cdh : 1; /* Hard internal bus parity error */ unsigned xrv$v_vir_vctl_csr_vis : 1; /* VIB bus soft error */ unsigned xrv$v_vir_vctl_csr_vih : 1; /* VIB* bus hard error */ unsigned xrv$v_vir_vctl_csr_ise : 1; /* Illegal sequence error */ unsigned xrv$v_vir_vctl_csr_mcode : 2; /* Machine check code */ unsigned xrv$v_vir_vctl_csr_stf : 1; /* Self test failed */ unsigned xrv$v_vir_vctl_csr_etf : 1; /* Extended test failed */ unsigned xrv$v_vir_vctl_csr_vhe : 1; /* Verse hard error */ unsigned xrv$$$_fill_3 : 6; unsigned xrv$v_vir_vctl_csr_see : 1; /* Soft error enable */ unsigned xrv$v_vir_vctl_csr_hee : 1; /* Hard error enable */ unsigned xrv$v_vir_vctl_csr_frl : 1; /* Force bad RFA low parity */ unsigned xrv$v_vir_vctl_csr_frh : 1; /* Force bad RFA high parity */ unsigned xrv$v_vir_vctl_csr_fdl : 1; /* Force bad CD bus low data parity */ unsigned xrv$v_vir_vctl_csr_fdh : 1; /* Force bad CD bus high data parity */ unsigned xrv$v_vir_vctl_csr_cmod : 2; /* Current mode during error */ unsigned xrv$$$_fill_4 : 2; unsigned xrv$v_vir_vctl_csr_fse : 1; /* Force soft error */ unsigned xrv$v_vir_vctl_csr_fvp : 1; /* Force bad VIB bus parity data parity */ unsigned xrv$$$_fill_5 : 1; unsigned xrv$v_vir_vctl_csr_imp : 1; /* Implementation specific error */ } xrvr_xrv_vir_vctl_csr_bits; __struct { unsigned xrv$v_vir_mod_rev_revision : 7; /* Module revision */ unsigned xrv$v_vir_mod_rev_fixup_ls : 1; /* Load store fixup trigger */ unsigned xrv$$$_fill_6 : 24; } xrvr_xrv_vir_mod_rev_bits; __struct { unsigned xrv$v_vir_lsx_ccsr_act : 1; /* Memory activity */ unsigned xrv$v_vir_lsx_ccsr_lsxrev : 4; /* Load store chip revision */ unsigned xrv$v_vir_lsx_ccsr_nodeid : 4; /* XMI node id */ unsigned xrv$v_vir_lsx_ccsr_cpe : 1; /* Cache parity error */ unsigned xrv$v_vir_lsx_ccsr_xse : 1; /* XMI interface soft error */ unsigned xrv$v_vir_lsx_ccsr_xhe : 1; /* XMI interface hard error */ unsigned xrv$$$_fill_7 : 3; unsigned xrv$v_vir_lsx_ccsr_cee : 1; /* Cache error enable */ unsigned xrv$v_vir_lsx_ccsr_see : 1; /* Soft error enable */ unsigned xrv$v_vir_lsx_ccsr_ena : 1; /* Cache enable */ unsigned xrv$v_vir_lsx_ccsr_hit : 1; /* Cache hit */ unsigned xrv$v_vir_lsx_ccsr_fht : 1; /* Force cache hit */ unsigned xrv$v_vir_lsx_ccsr_flu : 1; /* Invalidate cache */ unsigned xrv$$$_fill_8 : 2; unsigned xrv$v_vir_lsx_ccsr_frl : 1; /* Force bad low RFA parity */ unsigned xrv$v_vir_lsx_ccsr_fdl : 1; /* Force bad low data parity */ unsigned xrv$v_vir_lsx_ccsr_fdh : 1; /* Force bad high data parity */ unsigned xrv$v_vir_lsx_ccsr_ivs : 1; /* Invert valid bit sense */ unsigned xrv$v_vir_lsx_ccsr_ips : 1; /* Invert parity sense */ unsigned xrv$v_vir_lsx_ccsr_dxt : 1; /* Disable XMI transactions */ unsigned xrv$v_vir_lsx_ccsr_idv : 1; /* Invert duplicate tag valid sense */ unsigned xrv$v_vir_lsx_ccsr_idp : 1; /* Invert duplicate tag parity sense */ unsigned xrv$v_vir_lsx_ccsr_dtc : 1; /* Duplicate tag check */ } xrvr_xrv_vir_lsx_ccsr_bits; } ; #if !defined(__VAXC) && !defined(VAXC) #define xrv$v_vir_alu_diag_ctrl_isl xrvr_xrv_vir_alu_diag_ctrl_bits.xrv$v_vir_alu_diag_ctrl_isl #define xrv$v_vir_alu_diag_ctrl_ish xrvr_xrv_vir_alu_diag_ctrl_bits.xrv$v_vir_alu_diag_ctrl_ish #define xrv$v_vir_alu_diag_ctrl_ibl xrvr_xrv_vir_alu_diag_ctrl_bits.xrv$v_vir_alu_diag_ctrl_ibl #define xrv$v_vir_alu_diag_ctrl_ibh xrvr_xrv_vir_alu_diag_ctrl_bits.xrv$v_vir_alu_diag_ctrl_ibh #define xrv$v_vir_alu_diag_ctrl_icl xrvr_xrv_vir_alu_diag_ctrl_bits.xrv$v_vir_alu_diag_ctrl_icl #define xrv$v_vir_alu_diag_ctrl_ich xrvr_xrv_vir_alu_diag_ctrl_bits.xrv$v_vir_alu_diag_ctrl_ich #define xrv$v_vir_alu_diag_ctrl_ici xrvr_xrv_vir_alu_diag_ctrl_bits.xrv$v_vir_alu_diag_ctrl_ici #define xrv$v_vir_alu_diag_ctrl_abe xrvr_xrv_vir_alu_diag_ctrl_bits.xrv$v_vir_alu_diag_ctrl_abe #define xrv$v_vir_alu_diag_ctrl_cpe xrvr_xrv_vir_alu_diag_ctrl_bits.xrv$v_vir_alu_diag_ctrl_cpe #define xrv$v_vir_alu_diag_ctrl_ifo xrvr_xrv_vir_alu_diag_ctrl_bits.xrv$v_vir_alu_diag_ctrl_ifo #define xrv$v_vir_vctl_csr_lss xrvr_xrv_vir_vctl_csr_bits.xrv$v_vir_vctl_csr_lss #define xrv$v_vir_vctl_csr_lsh xrvr_xrv_vir_vctl_csr_bits.xrv$v_vir_vctl_csr_lsh #define xrv$v_vir_vctl_csr_cds xrvr_xrv_vir_vctl_csr_bits.xrv$v_vir_vctl_csr_cds #define xrv$v_vir_vctl_csr_cdh xrvr_xrv_vir_vctl_csr_bits.xrv$v_vir_vctl_csr_cdh #define xrv$v_vir_vctl_csr_vis xrvr_xrv_vir_vctl_csr_bits.xrv$v_vir_vctl_csr_vis #define xrv$v_vir_vctl_csr_vih xrvr_xrv_vir_vctl_csr_bits.xrv$v_vir_vctl_csr_vih #define xrv$v_vir_vctl_csr_ise xrvr_xrv_vir_vctl_csr_bits.xrv$v_vir_vctl_csr_ise #define xrv$v_vir_vctl_csr_mcode xrvr_xrv_vir_vctl_csr_bits.xrv$v_vir_vctl_csr_mcode #define xrv$v_vir_vctl_csr_stf xrvr_xrv_vir_vctl_csr_bits.xrv$v_vir_vctl_csr_stf #define xrv$v_vir_vctl_csr_etf xrvr_xrv_vir_vctl_csr_bits.xrv$v_vir_vctl_csr_etf #define xrv$v_vir_vctl_csr_vhe xrvr_xrv_vir_vctl_csr_bits.xrv$v_vir_vctl_csr_vhe #define xrv$v_vir_vctl_csr_see xrvr_xrv_vir_vctl_csr_bits.xrv$v_vir_vctl_csr_see #define xrv$v_vir_vctl_csr_hee xrvr_xrv_vir_vctl_csr_bits.xrv$v_vir_vctl_csr_hee #define xrv$v_vir_vctl_csr_frl xrvr_xrv_vir_vctl_csr_bits.xrv$v_vir_vctl_csr_frl #define xrv$v_vir_vctl_csr_frh xrvr_xrv_vir_vctl_csr_bits.xrv$v_vir_vctl_csr_frh #define xrv$v_vir_vctl_csr_fdl xrvr_xrv_vir_vctl_csr_bits.xrv$v_vir_vctl_csr_fdl #define xrv$v_vir_vctl_csr_fdh xrvr_xrv_vir_vctl_csr_bits.xrv$v_vir_vctl_csr_fdh #define xrv$v_vir_vctl_csr_cmod xrvr_xrv_vir_vctl_csr_bits.xrv$v_vir_vctl_csr_cmod #define xrv$v_vir_vctl_csr_fse xrvr_xrv_vir_vctl_csr_bits.xrv$v_vir_vctl_csr_fse #define xrv$v_vir_vctl_csr_fvp xrvr_xrv_vir_vctl_csr_bits.xrv$v_vir_vctl_csr_fvp #define xrv$v_vir_vctl_csr_imp xrvr_xrv_vir_vctl_csr_bits.xrv$v_vir_vctl_csr_imp #define xrv$v_vir_mod_rev_revision xrvr_xrv_vir_mod_rev_bits.xrv$v_vir_mod_rev_revision #define xrv$v_vir_mod_rev_fixup_ls xrvr_xrv_vir_mod_rev_bits.xrv$v_vir_mod_rev_fixup_ls #define xrv$v_vir_lsx_ccsr_act xrvr_xrv_vir_lsx_ccsr_bits.xrv$v_vir_lsx_ccsr_act #define xrv$v_vir_lsx_ccsr_lsxrev xrvr_xrv_vir_lsx_ccsr_bits.xrv$v_vir_lsx_ccsr_lsxrev #define xrv$v_vir_lsx_ccsr_nodeid xrvr_xrv_vir_lsx_ccsr_bits.xrv$v_vir_lsx_ccsr_nodeid #define xrv$v_vir_lsx_ccsr_cpe xrvr_xrv_vir_lsx_ccsr_bits.xrv$v_vir_lsx_ccsr_cpe #define xrv$v_vir_lsx_ccsr_xse xrvr_xrv_vir_lsx_ccsr_bits.xrv$v_vir_lsx_ccsr_xse #define xrv$v_vir_lsx_ccsr_xhe xrvr_xrv_vir_lsx_ccsr_bits.xrv$v_vir_lsx_ccsr_xhe #define xrv$v_vir_lsx_ccsr_cee xrvr_xrv_vir_lsx_ccsr_bits.xrv$v_vir_lsx_ccsr_cee #define xrv$v_vir_lsx_ccsr_see xrvr_xrv_vir_lsx_ccsr_bits.xrv$v_vir_lsx_ccsr_see #define xrv$v_vir_lsx_ccsr_ena xrvr_xrv_vir_lsx_ccsr_bits.xrv$v_vir_lsx_ccsr_ena #define xrv$v_vir_lsx_ccsr_hit xrvr_xrv_vir_lsx_ccsr_bits.xrv$v_vir_lsx_ccsr_hit #define xrv$v_vir_lsx_ccsr_fht xrvr_xrv_vir_lsx_ccsr_bits.xrv$v_vir_lsx_ccsr_fht #define xrv$v_vir_lsx_ccsr_flu xrvr_xrv_vir_lsx_ccsr_bits.xrv$v_vir_lsx_ccsr_flu #define xrv$v_vir_lsx_ccsr_frl xrvr_xrv_vir_lsx_ccsr_bits.xrv$v_vir_lsx_ccsr_frl #define xrv$v_vir_lsx_ccsr_fdl xrvr_xrv_vir_lsx_ccsr_bits.xrv$v_vir_lsx_ccsr_fdl #define xrv$v_vir_lsx_ccsr_fdh xrvr_xrv_vir_lsx_ccsr_bits.xrv$v_vir_lsx_ccsr_fdh #define xrv$v_vir_lsx_ccsr_ivs xrvr_xrv_vir_lsx_ccsr_bits.xrv$v_vir_lsx_ccsr_ivs #define xrv$v_vir_lsx_ccsr_ips xrvr_xrv_vir_lsx_ccsr_bits.xrv$v_vir_lsx_ccsr_ips #define xrv$v_vir_lsx_ccsr_dxt xrvr_xrv_vir_lsx_ccsr_bits.xrv$v_vir_lsx_ccsr_dxt #define xrv$v_vir_lsx_ccsr_idv xrvr_xrv_vir_lsx_ccsr_bits.xrv$v_vir_lsx_ccsr_idv #define xrv$v_vir_lsx_ccsr_idp xrvr_xrv_vir_lsx_ccsr_bits.xrv$v_vir_lsx_ccsr_idp #define xrv$v_vir_lsx_ccsr_dtc xrvr_xrv_vir_lsx_ccsr_bits.xrv$v_vir_lsx_ccsr_dtc #endif /* #if !defined(__VAXC) && !defined(VAXC) */ #ifdef __cplusplus } #endif #pragma standard #endif /* __XRVDEF_LOADED */