/********************************************************************************************************************************/ /* Created: 15-MAR-2001 23:38:09 by OpenVMS SDL EV1-33 */ /* Source: 15-MAR-2001 23:34:16 _$11$DUA933:[BUILD.SDL]STARDEFMP.SDI;1 */ /********************************************************************************************************************************/ /*** MODULE $PR9RRDEF ***/ #ifndef __PR9RRDEF_LOADED #define __PR9RRDEF_LOADED 1 #pragma nostandard #ifdef __cplusplus extern "C" { #define __unknown_params ... #else #define __unknown_params #endif #if !defined(__VAXC) && !defined(VAXC) #define __struct struct #define __union union #else #define __struct variant_struct #define __union variant_union #endif #define PR9RR$_ICCS 24 /* Interval Clock Control/Status */ #define ICCS$M_IE 0x40 #define PR9RR$_TODR 27 /* Time of Year Clock */ #define PR9RR$_RXCS 32 /* Console Receiver Control/Status */ #define RXCS$M_RX_IE 0x40 #define RXCS$M_RX_DONE 0x80 #define PR9RR$_RXDB 33 /* Console Receiver Data Buffer */ #define RXDB$M_DATA 0xFF #define RXDB$M_RCV_BRK 0x800 #define RXDB$M_FRM_ERR 0x2000 #define RXDB$M_OVR_ERR 0x4000 #define RXDB$M_ERR_9RR 0x8000 #define PR9RR$_TXCS 34 /* Console Transmit Control/Status */ #define TXCS$M_XMIT_BRK 0x1 #define TXCS$M_LOOPBACK 0x4 #define TXCS$M_TX_IE 0x40 #define TXCS$M_TX_RDY 0x80 #define PR9RR$_TXDB 35 /* Console Transmit Data Buffer */ #define TXDB$M_DATA 0xFF #define PR9RR$_MCESR 38 /* Machine Check Error Register */ #define PR9RR$_ACCS 40 /* Floating Point Accelerator Register */ #define ACCS$M_VECTOR_PRESENT 0x1 #define ACCS$M_FCHIP_PRESENT 0x2 #define ACCS$M_WRITE_EVEN_PARITY 0x80000000 #define PR9RR$_SAVPC 42 /* Console SAVED PC */ #define PR9RR$_SAVPSL 43 /* Console SAVED PSL */ #define SAVPSL$M_HALT_CODE 0x3F00 #define SAVPSL$M_INVALID 0x4000 #define SAVPSL$M_MAPEN 0x8000 #define PR9RR$_TBTAG 47 /* Translation Buffer Tag */ #define PR9RR$_IORESET 55 /* IO BUS RESET */ #define PR9RR$_TBDATA 59 /* Translation Buffer Data */ #define PR9RR$_SID 62 /* System Identification Register */ #define XSID$M_ARCH 0xFF #define XSID$M_SYS_VAR 0xFF00 #define XSID$M_XRPFWREV 0xFF0000 #define PR9RR$_BCBTS 113 /* Backup Cache Tag Store */ #define BCBTS$M_VALID 0x3C #define BCBTS$M_TAG 0x1FFE0000 #define BCBTS$M_PARITY 0x20000000 #define PR9RR$_BCP1TS 114 /* Backup cache primary tag array, first half bits */ #define BCPTS$M_VALID 0x4 #define BCPTS$M_TAG 0x1FFFFFF8 #define BCPTS$M_PARITY 0x20000000 #define PR9RR$_BCP2TS 115 /* Backup cache primary tag array, second half bits */ /* PR9RRBCP2TS_BITS structure fill prefix BCPTS$; */ #define PR9RR$_BCRFR 116 /* Backup Cache Refresh Register */ #define BCRFR$M_PTS 0x1F0 #define BCRFR$M_BTS 0x1FE00 #define PR9RR$_BCIDX 117 /* Backup Cache Index Register */ #define BCIDX$M_BTS 0x1FFC0 #define BCIDX$M_PTS 0x7F0 #define PR9RR$_BCSTS 118 /* Backup Cache Status Register */ #define BCSTS$M_LOCK 0x1 #define BCSTS$M_BTS_PERR 0x2 #define BCSTS$M_P1TS_PERR 0x4 #define BCSTS$M_P2TS_PERR 0x8 #define BCSTS$M_BUS_ERR 0x10 #define BCSTS$M_BTS_COMP 0x20000 #define BCSTS$M_BTS_HIT 0x40000 #define BCSTS$M_P1TS_HIT 0x80000 #define BCSTS$M_P2TS_HIT 0x100000 #define BCSTS$M_CMD 0x1E00000 #define BCSTS$M_IBUS_CYC 0x2000000 #define BCSTS$M_PRED_PAR 0x4000000 #define PR9RR$_BCCTL 119 /* Backup Cache Control Register */ #define BCCTL$M_FRCHIT 0x1 #define BCCTL$M_ENABTS 0x2 #define BCCTL$M_ENAPTS 0x4 #define BCCTL$M_ENARFR 0x8 #define BCCTL$M_RAMSPD 0x10 #define BCCTL$K_RAMSPD 0 /* Use fast RAMs */ #define PR9RR$_BCERR 120 /* Backup Cache Error Address Register */ #define PR9RR$_BCFBTS 121 /* Backup Cache Backup Tag Store Flush Register */ #define BCFBTS$K_FLUSH 0 #define PR9RR$_BCFPTS 122 /* Backup Cache Primary Tag Store Flush Register */ #define BCFPTS$K_FLUSH 0 #define PR9RR$_VINTSR 123 /* Vector interface error status register */ #define VINTSR$M_VECTOR_UNIT_ABSENT 0x1 #define VINTSR$M_VECTOR_UNIT_SERR 0x2 #define VINTSR$M_VECTOR_UNIT_HERR 0x4 #define VINTSR$M_VECTL_VIB_SERR 0x8 #define VINTSR$M_VECTL_VIB_HERR 0x10 #define VINTSR$M_CCHIP_VIB_SERR 0x20 #define VINTSR$M_CCHIP_VIB_HERR 0x40 #define VINTSR$M_BUS_TIMEOUT 0x80 #define VINTSR$M_VECTOR_MODULE_RESET 0x100 #define VINTSR$M_DISABLE_VECT_INTF 0x200 #define PR9RR$_PCTAG 124 /* Primary Cache Tag Store */ #define PCTAG$M_TAG 0x1FFFF800 #define PCTAG$M_PARITY 0x40000000 #define PCTAG$M_VALID 0x80000000 #define PR9RR$_PCIDX 125 /* Primary Cache Index Register */ #define PCIDX$M_IDX 0x7F8 #define PR9RR$_PCERR 126 /* Primary Cache Error Address Register */ #define PR9RR$_PCSTS 127 /* Primary Cache Status Register */ #define PCSTS$M_FRCHIT 0x1 #define PCSTS$M_ENAPTS 0x2 #define PCSTS$M_FLUSH 0x4 #define PCSTS$M_ENARFR 0x8 #define PCSTS$M_HIT 0x10 #define PCSTS$M_INTERRUPT 0x20 #define PCSTS$M_TRAP2 0x40 #define PCSTS$M_TRAP1 0x80 #define PCSTS$M_TAG_PERR 0x100 #define PCSTS$M_DAL_PERR 0x200 #define PCSTS$M_DATA_PERR 0x400 #define PCSTS$M_BUSERR 0x800 #define PCSTS$M_BC_HIT 0x1000 union pr9rrdef { __struct { unsigned iccs$$$_fill_1 : 6; unsigned iccs$v_ie : 1; /* Interrupt enable */ unsigned iccs$v_fill_82 : 1; } pr9rrr_pr9rriccs_bits; __struct { unsigned rxcs$$$_fill_1 : 6; unsigned rxcs$v_rx_ie : 1; /* Interrupt enable */ unsigned rxcs$v_rx_done : 1; /* Receiver done */ } pr9rrr_pr9rrrxcs_bits; __struct { unsigned rxdb$v_data : 8; /* Received data */ unsigned rxdb$$$_fill_1 : 3; unsigned rxdb$v_rcv_brk : 1; /* Break or CTRL/P received */ unsigned rxdb$$$_fill_2 : 1; unsigned rxdb$v_frm_err : 1; /* Framing error */ unsigned rxdb$v_ovr_err : 1; /* Overrun error */ unsigned rxdb$v_err_9rr : 1; /* Error */ } pr9rrr_pr9rrrxdb_bits; __struct { unsigned txcs$v_xmit_brk : 1; /* Transmit break */ unsigned txcs$$$_fill_1 : 1; unsigned txcs$v_loopback : 1; /* Loopback */ unsigned txcs$$$_fill_2 : 3; unsigned txcs$v_tx_ie : 1; /* Interrupt enable */ unsigned txcs$v_tx_rdy : 1; /* Transmitter ready */ } pr9rrr_pr9rrtxcs_bits; __struct { unsigned txdb$v_data : 8; /* Data to transmit */ } pr9rrr_pr9rrtxdb_bits; __struct { unsigned accs$v_vector_present : 1; /* Vector unit present */ unsigned accs$v_fchip_present : 1; /* F-Chip present */ unsigned accs$$$_fill_1 : 29; unsigned accs$v_write_even_parity : 1; /* Write even parity */ } pr9rrr_pr9rraccs_bits; __struct { unsigned savpsl$$$_fill_1 : 8; unsigned savpsl$v_halt_code : 6; /* Halt code */ unsigned savpsl$v_invalid : 1; /* Saved PSL invalid */ unsigned savpsl$v_mapen : 1; /* Saved MAPEN */ } pr9rrr_pr9rrsavpsl_bits; __struct { unsigned sid$v_rvaxrev : 8; /* 9RR chip µcode rev level */ } pr9rrr_pr9rrsid_bits; /* XSID (SYS_TYPE) Register bits */ __struct { unsigned xsid$v_arch : 8; /* Architectural ID (=1) */ unsigned xsid$v_sys_var : 8; /* System Variant (=1) */ unsigned xsid$v_xrpfwrev : 8; /* XRP firmware revision level */ } pr9rrr_pr9rrxsid_bits; __struct { unsigned bcbts$$$_fill_1 : 2; unsigned bcbts$v_valid : 4; /* Four valid bits */ unsigned bcbts$$$_fill_2 : 11; unsigned bcbts$v_tag : 12; /* Cache tag */ unsigned bcbts$v_parity : 1; /* Parity bit */ unsigned bcbts$v_fill_83 : 2; } pr9rrr_pr9rrbcbts_bits; __struct { unsigned bcpts$$$_fill_1 : 2; unsigned bcpts$v_valid : 1; /* Valid bit */ unsigned bcpts$v_tag : 26; /* Cache tag */ unsigned bcpts$v_parity : 1; /* Parity bit */ unsigned bcpts$v_fill_84 : 2; } pr9rrr_pr9rrbcp1ts_bits; /* end PR9RRBCP2TS_BITS; /* Bit definitions are the same as PR9RR$_BCP1TS */ __struct { unsigned bcrfr$$$_fill_1 : 4; unsigned bcrfr$v_pts : 5; /* PTS refresh index */ unsigned bcrfr$v_bts : 8; /* BTS refresh index */ unsigned bcrfr$v_fill_85 : 7; } pr9rrr_pr9rrbcrfr_bits; __union { __struct { unsigned bcidx$$$_fill_1 : 6; unsigned bcidx$v_bts : 11; /* BTS index */ unsigned bcidx$v_fill_86 : 7; } bcidx$r_pr9rrbcidx_bts; __struct { unsigned bcidx$$$_fill_2 : 4; unsigned bcidx$v_pts : 7; /* PTS index */ unsigned bcidx$v_fill_87 : 5; } bcidx$r_pr9rrbcidx_pts; } pr9rrr_pr9rrbcidx_bits; __struct { unsigned bcsts$v_lock : 1; /* Error lock */ unsigned bcsts$v_bts_perr : 1; /* BTS parity error */ unsigned bcsts$v_p1ts_perr : 1; /* P1TS parity error */ unsigned bcsts$v_p2ts_perr : 1; /* P2TS parity error */ unsigned bcsts$v_bus_err : 1; /* Bus error */ unsigned bcsts$$$_fill_1 : 12; unsigned bcsts$v_bts_comp : 1; /* BTS compare */ unsigned bcsts$v_bts_hit : 1; /* BTS hit */ unsigned bcsts$v_p1ts_hit : 1; /* P1TS hit */ unsigned bcsts$v_p2ts_hit : 1; /* P2TS hit */ unsigned bcsts$v_cmd : 4; /* Last DAL command */ unsigned bcsts$v_ibus_cyc : 1; /* I-bus cycle */ unsigned bcsts$v_pred_par : 1; /* Predicted parity */ unsigned bcsts$v_fill_88 : 5; } pr9rrr_pr9rrbcsts_bits; __struct { unsigned bcctl$v_frchit : 1; /* Force hit */ unsigned bcctl$v_enabts : 1; /* Enable BTS (cache on) */ unsigned bcctl$v_enapts : 1; /* Enable PTS (filter on) */ unsigned bcctl$v_enarfr : 1; /* Enable refresh */ unsigned bcctl$v_ramspd : 1; /* Cache RAM speed (0 = 1 cycle, 1 = 2 cycles) */ unsigned bcctl$v_fill_89 : 3; } pr9rrr_pr9rrbcctl_bits; __struct { unsigned vintsr$v_vector_unit_absent : 1; /* Vector unit absent */ unsigned vintsr$v_vector_unit_serr : 1; /* Vector soft error */ unsigned vintsr$v_vector_unit_herr : 1; /* Vector soft error */ unsigned vintsr$v_vectl_vib_serr : 1; /* Vector soft error */ unsigned vintsr$v_vectl_vib_herr : 1; /* Vector soft error */ unsigned vintsr$v_cchip_vib_serr : 1; /* Vector soft error */ unsigned vintsr$v_cchip_vib_herr : 1; /* Vector soft error */ unsigned vintsr$v_bus_timeout : 1; /* Bus timeout during vector transfer */ unsigned vintsr$v_vector_module_reset : 1; /* Vector module reset */ unsigned vintsr$v_disable_vect_intf : 1; /* Vector module reset */ unsigned vintsr$v_fill_90 : 6; } pr9rrr_pr9rrvintsr_bits; __struct { unsigned pctag$$$_fill_1 : 11; unsigned pctag$v_tag : 18; /* Cache tag */ unsigned pctag$$$_fill_2 : 1; unsigned pctag$v_parity : 1; /* Parity bit */ unsigned pctag$v_valid : 1; /* Valid bit */ } pr9rrr_pr9rrpctag_bits; __struct { unsigned pcidx$$$_fill_1 : 3; unsigned pcidx$v_idx : 8; /* Tag index */ unsigned pcidx$v_fill_91 : 5; } pr9rrr_pr9rrpcidx_bits; __struct { unsigned pcsts$v_frchit : 1; /* Force hit */ unsigned pcsts$v_enapts : 1; /* Enable tag store (cache on) */ unsigned pcsts$v_flush : 1; /* Flush cache */ unsigned pcsts$v_enarfr : 1; /* Enable refresh */ unsigned pcsts$v_hit : 1; /* Reference hit */ unsigned pcsts$v_interrupt : 1; /* Error interrupt pending */ unsigned pcsts$v_trap2 : 1; /* Double error lock */ unsigned pcsts$v_trap1 : 1; /* Error lock */ unsigned pcsts$v_tag_perr : 1; /* Tag parity error */ unsigned pcsts$v_dal_perr : 1; /* DAL data parity error */ unsigned pcsts$v_data_perr : 1; /* Data parity error */ unsigned pcsts$v_buserr : 1; /* Bus error */ unsigned pcsts$v_bc_hit : 1; /* Reference hit in Bcache */ unsigned pcsts$v_fill_92 : 3; } pr9rrr_pr9rrpcsts_bits; } ; #if !defined(__VAXC) && !defined(VAXC) #define iccs$v_ie pr9rrr_pr9rriccs_bits.iccs$v_ie #define rxcs$v_rx_ie pr9rrr_pr9rrrxcs_bits.rxcs$v_rx_ie #define rxcs$v_rx_done pr9rrr_pr9rrrxcs_bits.rxcs$v_rx_done #define rxdb$v_data pr9rrr_pr9rrrxdb_bits.rxdb$v_data #define rxdb$v_rcv_brk pr9rrr_pr9rrrxdb_bits.rxdb$v_rcv_brk #define rxdb$v_frm_err pr9rrr_pr9rrrxdb_bits.rxdb$v_frm_err #define rxdb$v_ovr_err pr9rrr_pr9rrrxdb_bits.rxdb$v_ovr_err #define rxdb$v_err_9rr pr9rrr_pr9rrrxdb_bits.rxdb$v_err_9rr #define txcs$v_xmit_brk pr9rrr_pr9rrtxcs_bits.txcs$v_xmit_brk #define txcs$v_loopback pr9rrr_pr9rrtxcs_bits.txcs$v_loopback #define txcs$v_tx_ie pr9rrr_pr9rrtxcs_bits.txcs$v_tx_ie #define txcs$v_tx_rdy pr9rrr_pr9rrtxcs_bits.txcs$v_tx_rdy #define txdb$v_data pr9rrr_pr9rrtxdb_bits.txdb$v_data #define accs$v_vector_present pr9rrr_pr9rraccs_bits.accs$v_vector_present #define accs$v_fchip_present pr9rrr_pr9rraccs_bits.accs$v_fchip_present #define accs$v_write_even_parity pr9rrr_pr9rraccs_bits.accs$v_write_even_parity #define savpsl$v_halt_code pr9rrr_pr9rrsavpsl_bits.savpsl$v_halt_code #define savpsl$v_invalid pr9rrr_pr9rrsavpsl_bits.savpsl$v_invalid #define savpsl$v_mapen pr9rrr_pr9rrsavpsl_bits.savpsl$v_mapen #define sid$v_rvaxrev pr9rrr_pr9rrsid_bits.sid$v_rvaxrev #define xsid$v_arch pr9rrr_pr9rrxsid_bits.xsid$v_arch #define xsid$v_sys_var pr9rrr_pr9rrxsid_bits.xsid$v_sys_var #define xsid$v_xrpfwrev pr9rrr_pr9rrxsid_bits.xsid$v_xrpfwrev #define bcbts$v_valid pr9rrr_pr9rrbcbts_bits.bcbts$v_valid #define bcbts$v_tag pr9rrr_pr9rrbcbts_bits.bcbts$v_tag #define bcbts$v_parity pr9rrr_pr9rrbcbts_bits.bcbts$v_parity #define bcpts$v_valid pr9rrr_pr9rrbcp1ts_bits.bcpts$v_valid #define bcpts$v_tag pr9rrr_pr9rrbcp1ts_bits.bcpts$v_tag #define bcpts$v_parity pr9rrr_pr9rrbcp1ts_bits.bcpts$v_parity #define bcrfr$v_pts pr9rrr_pr9rrbcrfr_bits.bcrfr$v_pts #define bcrfr$v_bts pr9rrr_pr9rrbcrfr_bits.bcrfr$v_bts #define bcidx$v_bts pr9rrr_pr9rrbcidx_bits.bcidx$r_pr9rrbcidx_bts.bcidx$v_bts #define bcidx$v_pts pr9rrr_pr9rrbcidx_bits.bcidx$r_pr9rrbcidx_pts.bcidx$v_pts #define bcsts$v_lock pr9rrr_pr9rrbcsts_bits.bcsts$v_lock #define bcsts$v_bts_perr pr9rrr_pr9rrbcsts_bits.bcsts$v_bts_perr #define bcsts$v_p1ts_perr pr9rrr_pr9rrbcsts_bits.bcsts$v_p1ts_perr #define bcsts$v_p2ts_perr pr9rrr_pr9rrbcsts_bits.bcsts$v_p2ts_perr #define bcsts$v_bus_err pr9rrr_pr9rrbcsts_bits.bcsts$v_bus_err #define bcsts$v_bts_comp pr9rrr_pr9rrbcsts_bits.bcsts$v_bts_comp #define bcsts$v_bts_hit pr9rrr_pr9rrbcsts_bits.bcsts$v_bts_hit #define bcsts$v_p1ts_hit pr9rrr_pr9rrbcsts_bits.bcsts$v_p1ts_hit #define bcsts$v_p2ts_hit pr9rrr_pr9rrbcsts_bits.bcsts$v_p2ts_hit #define bcsts$v_cmd pr9rrr_pr9rrbcsts_bits.bcsts$v_cmd #define bcsts$v_ibus_cyc pr9rrr_pr9rrbcsts_bits.bcsts$v_ibus_cyc #define bcsts$v_pred_par pr9rrr_pr9rrbcsts_bits.bcsts$v_pred_par #define bcctl$v_frchit pr9rrr_pr9rrbcctl_bits.bcctl$v_frchit #define bcctl$v_enabts pr9rrr_pr9rrbcctl_bits.bcctl$v_enabts #define bcctl$v_enapts pr9rrr_pr9rrbcctl_bits.bcctl$v_enapts #define bcctl$v_enarfr pr9rrr_pr9rrbcctl_bits.bcctl$v_enarfr #define bcctl$v_ramspd pr9rrr_pr9rrbcctl_bits.bcctl$v_ramspd #define vintsr$v_vector_unit_absent pr9rrr_pr9rrvintsr_bits.vintsr$v_vector_unit_absent #define vintsr$v_vector_unit_serr pr9rrr_pr9rrvintsr_bits.vintsr$v_vector_unit_serr #define vintsr$v_vector_unit_herr pr9rrr_pr9rrvintsr_bits.vintsr$v_vector_unit_herr #define vintsr$v_vectl_vib_serr pr9rrr_pr9rrvintsr_bits.vintsr$v_vectl_vib_serr #define vintsr$v_vectl_vib_herr pr9rrr_pr9rrvintsr_bits.vintsr$v_vectl_vib_herr #define vintsr$v_cchip_vib_serr pr9rrr_pr9rrvintsr_bits.vintsr$v_cchip_vib_serr #define vintsr$v_cchip_vib_herr pr9rrr_pr9rrvintsr_bits.vintsr$v_cchip_vib_herr #define vintsr$v_bus_timeout pr9rrr_pr9rrvintsr_bits.vintsr$v_bus_timeout #define vintsr$v_vector_module_reset pr9rrr_pr9rrvintsr_bits.vintsr$v_vector_module_reset #define vintsr$v_disable_vect_intf pr9rrr_pr9rrvintsr_bits.vintsr$v_disable_vect_intf #define pctag$v_tag pr9rrr_pr9rrpctag_bits.pctag$v_tag #define pctag$v_parity pr9rrr_pr9rrpctag_bits.pctag$v_parity #define pctag$v_valid pr9rrr_pr9rrpctag_bits.pctag$v_valid #define pcidx$v_idx pr9rrr_pr9rrpcidx_bits.pcidx$v_idx #define pcsts$v_frchit pr9rrr_pr9rrpcsts_bits.pcsts$v_frchit #define pcsts$v_enapts pr9rrr_pr9rrpcsts_bits.pcsts$v_enapts #define pcsts$v_flush pr9rrr_pr9rrpcsts_bits.pcsts$v_flush #define pcsts$v_enarfr pr9rrr_pr9rrpcsts_bits.pcsts$v_enarfr #define pcsts$v_hit pr9rrr_pr9rrpcsts_bits.pcsts$v_hit #define pcsts$v_interrupt pr9rrr_pr9rrpcsts_bits.pcsts$v_interrupt #define pcsts$v_trap2 pr9rrr_pr9rrpcsts_bits.pcsts$v_trap2 #define pcsts$v_trap1 pr9rrr_pr9rrpcsts_bits.pcsts$v_trap1 #define pcsts$v_tag_perr pr9rrr_pr9rrpcsts_bits.pcsts$v_tag_perr #define pcsts$v_dal_perr pr9rrr_pr9rrpcsts_bits.pcsts$v_dal_perr #define pcsts$v_data_perr pr9rrr_pr9rrpcsts_bits.pcsts$v_data_perr #define pcsts$v_buserr pr9rrr_pr9rrpcsts_bits.pcsts$v_buserr #define pcsts$v_bc_hit pr9rrr_pr9rrpcsts_bits.pcsts$v_bc_hit #endif /* #if !defined(__VAXC) && !defined(VAXC) */ #ifdef __cplusplus } #endif #pragma standard #endif /* __PR9RRDEF_LOADED */