/********************************************************************************************************************************/ /* Created: 15-MAR-2001 23:38:09 by OpenVMS SDL EV1-33 */ /* Source: 15-MAR-2001 23:34:16 _$11$DUA933:[BUILD.SDL]STARDEFMP.SDI;1 */ /********************************************************************************************************************************/ /*** MODULE $PR9AQDEF ***/ #ifndef __PR9AQDEF_LOADED #define __PR9AQDEF_LOADED 1 #pragma nostandard #ifdef __cplusplus extern "C" { #define __unknown_params ... #else #define __unknown_params #endif #if !defined(__VAXC) && !defined(VAXC) #define __struct struct #define __union union #else #define __struct variant_struct #define __union variant_union #endif #define PR9AQ$C_CONSIPL 20 /* IPL for all Console Registers */ #define PR9AQ$C_CLKIPL 22 /* IPL for Interval Clock */ #define PR9AQ$C_IP_IPL 22 /* IPL for Interprocessor Interrupts */ #define PR9AQ$_NICR 25 /* Next Interval Count Register */ #define PR9AQ$_ICR 26 /* Interval Counter Register */ #define PR9AQ$_TODR 27 /* Time of Year */ #define PR9AQ$_PME 61 /* Performance Monitor Enable */ #define PR9AQ$_CSWP 66 /* Cache Sweep */ #define PR9AQ$_CRBT 72 /* Console Reboot */ #define PR9AQ$_CPUCNF 106 /* CPU Configuration */ #define PR9AQ$_ICIR 107 /* Interrupt Other Processor */ #define PR9AQ$_RXFCT 108 /* Receive Function Register */ #define PR9AQ$_RXPRM 109 /* Receive Parameter Register */ #define PR9AQ$_TXFCT 110 /* Transmit Function Register */ #define PR9AQ$_TXPRM 111 /* Transmit Parameter Register */ #define PR9AQ$C_CSWP_INIT 1 /* Initiate Cache Sweep */ #define PR9AQ$C_CRBT_CODE 1 /* Reboot Code for CRBT_CODE */ #define PR9AQ$C_TXFCT_GETHDWCTX 1 /* Get Hardware Context */ #define PR9AQ$C_TXFCT_VBFIO 2 /* Virtual Block File I/O */ #define PR9AQ$C_TXFCT_KEEPALIVE 3 /* Keep Alive */ #define PR9AQ$C_TXFCT_SENDDG 4 /* Send Datagram */ #define PR9AQ$C_TXFCT_RETDGSTS 5 /* Return DG Status */ #define PR9AQ$C_TXFCT_SWITCHPRI 6 /* Switch Primary CPU */ #define PR9AQ$C_TXFCT_REBOOTSYS 7 /* Reboot System */ #define PR9AQ$C_TXFCT_CLRWRMSTR 8 /* Clear Warm Start Flag */ #define PR9AQ$C_TXFCT_CLRCLDSTR 9 /* Clear Cold Start Flag */ #define PR9AQ$C_TXFCT_BOOTSEC 10 /* Boot/Reboot Secondary CPU */ #define PR9AQ$C_TXFCT_HLTREMAVL 11 /* Halt CPU, Remove from Available Set */ #define PR9AQ$C_TXFCT_HLTKEPAVL 12 /* Halt CPU, Keep in Available Set */ #define PR9AQ$C_TXFCT_CONSQUIET 14 /* Shut Down Non-Primary Switch XMITs */ #define PR9AQ$C_TXFCT_SETINTMOD 15 /* Set Interrupt Mode */ #define PR9AQ$C_TXFCT_ABORTDL 16 /* Abort Datalink(s) */ #define PR9AQ$C_TXFCT_RESETIO 17 /* Reset I/O System */ #define PR9AQ$C_TXFCT_DSABLVBOX 18 /* Disable VBOX */ #define PR9AQ$C_TXFCT_SETKEPALV 19 /* Set Console Keep-Alive State */ #define PR9AQ$C_TXFCT_ERLENA 20 /* Flush pending errorlog entries */ #define PR9AQ$C_TXFCT_GETSYSTYPE 21 /* Return value of systype register */ #define PR9AQ$C_RXFCT_REMOVECPU 2 /* Remove Processor */ #define PR9AQ$C_RXFCT_ADDCPU 3 /* Add Processor */ #define PR9AQ$C_RXFCT_MARKBADPG 4 /* Mark Memory Page Bad */ #define PR9AQ$C_RXFCT_REQMEMORY 5 /* Request Memory Pages */ #define PR9AQ$C_RXFCT_SNDERLENT 6 /* Send Error Log Entry */ #define PR9AQ$C_RXFCT_SNDOPCMSG 7 /* Send OPCOM Message */ #define PR9AQ$C_RXFCT_GETDGBUF 8 /* Get Datagram Buffer */ #define PR9AQ$C_RXFCT_SENDDG 9 /* Send Datagram */ #define PR9AQ$C_RXFCT_RETDGSTS 10 /* Return DG Status */ #define PR9AQ$C_RXFCT_SETKEPALV 11 /* Set Keep-alive State */ #define PR9AQ$C_RXFCT_ABORTDL 12 /* Abort Datalink(s) */ #define PR9AQ$C_RXFCT_ERRORINT 13 /* Error Interrupt */ #define PR9AQ_XSID$M_ARCH_ID 0xFF #define PR9AQ_XSID$M_VECTOR 0x100 #define PR9AQ_XSID$M_CPUS 0x600 #define PR9AQ_XSID$M_MMODEL 0x1800 #define PR9AQ_XSID$M_SYS_TYPE 0x7F800000 #define PR9AQ$C_SYSTYPE_AQUARIUS 0 #define PR9AQ$C_SYSTYPE_AQUARIUSII 1 #define PR9AQ$C_SYSTYPE_AQUARIUSIII 2 #define PR9AQ$C_SYSTYPE_ARIDUS 8 #define PR9AQ$C_SYSTYPE_ARIDUSII 9 #define PR9AQ$C_SYSTYPE_ARIDUSIII 10 #define PR9AQ$M_CPUCNF_CPU_AVL 0xF #define PR9AQ$M_CPUCNF_CPU_PSED 0xF0 #define PR9AQ$M_CPUCNF_VBOX_AVL 0xF00 #define PR9AQ$M_CPUCNF_XJA_AVL 0xF000 #define PR9AQ$M_CPUCNF_34_BIT 0x10000 #define PR9AQ$M_CPUCNF_PRIMARY 0x60000 #define PR9AQ$M_CPUCNF_RRINTR 0x80000 #define PR9AQ$M_CPUCNF_MMU0_ENA 0x100000 #define PR9AQ$M_CPUCNF_MMU1_ENA 0x200000 #define PR9AQ$M_CPUCNF_ICU0_ENA 0x400000 #define PR9AQ$M_CPUCNF_ICU1_ENA 0x800000 #define PR9AQ$M_CPUCNF_CPU0_CON 0x1000000 #define PR9AQ$M_CPUCNF_CPU0_IE 0x2000000 #define PR9AQ$M_CPUCNF_CPU1_CON 0x4000000 #define PR9AQ$M_CPUCNF_CPU1_IE 0x8000000 #define PR9AQ$M_CPUCNF_CPU2_CON 0x10000000 #define PR9AQ$M_CPUCNF_CPU2_IE 0x20000000 #define PR9AQ$M_CPUCNF_CPU3_CON 0x40000000 #define PR9AQ$M_CPUCNF_CPU3_IE 0x80000000 #define PR9AQ$C_CPUCNF_FLUID -16252688 /* Fluid bits */ /* (CPUx_IE/CPUx_CON/RRINTR/ */ #define PR9AQ$M_TXFCT_STATUS 0x20000000 #define PR9AQ$M_TXFCT_INTENA 0x40000000 #define PR9AQ$M_TXFCT_READY 0x80000000 #define PR9AQ$M_RXFCT_STATUS 0x20000000 #define PR9AQ$M_RXFCT_INTENA 0x40000000 #define PR9AQ$M_RXFCT_VALID 0x80000000 union pr9aqdef { __struct { /* Read only SID register */ unsigned pr9aq$v_sid_serial : 12; /* Processor Serial Number */ unsigned pr9aq$v_sid_plant : 2; /* Mfg Plant Code */ unsigned pr9aq$v_sid_systype2 : 2; /* Expanded system type code */ unsigned pr9aq$v_sid_revlvl : 6; /* System Revision Level */ unsigned pr9aq$v_sid_systype : 2; /* System Type Code */ unsigned pr9aq$v_sid_type : 8; /* CPU Type Code */ } pr9aq$r_pr9aqsid_bits; __struct { unsigned pr9aq_xsid$v_arch_id : 8; /* Timeshare (1) / Server (2) */ unsigned pr9aq_xsid$v_vector : 1; /* Vector capable */ unsigned pr9aq_xsid$v_cpus : 2; /* # CPUs installed -1 */ unsigned pr9aq_xsid$v_mmodel : 2; /* Marketing model type */ unsigned pr9aq_xsid$v_rsvd : 10; /* Reserved */ unsigned pr9aq_xsid$v_sys_type : 8; /* System type */ unsigned pr9aq_xsid$v_fill_93 : 1; } pr9aq$r_pr9aqxsid_bits; __struct { /* CPU Configuration Register */ unsigned pr9aq$v_cpucnf_cpu_avl : 4; /* CPU 0-3 Available */ unsigned pr9aq$v_cpucnf_cpu_psed : 4; /* CPU 0-3 Paused */ unsigned pr9aq$v_cpucnf_vbox_avl : 4; /* CPU 0-3 VBOX Configured and Available */ unsigned pr9aq$v_cpucnf_xja_avl : 4; /* XJA 0-3 Available */ unsigned pr9aq$v_cpucnf_34_bit : 1; /* Addressing Mode = 34 bits */ unsigned pr9aq$v_cpucnf_primary : 2; /* Primary CPU Number */ unsigned pr9aq$v_cpucnf_rrintr : 1; /* Round Robin Interrupts */ unsigned pr9aq$v_cpucnf_mmu0_ena : 1; /* MMU0 Enabled */ unsigned pr9aq$v_cpucnf_mmu1_ena : 1; /* MMU1 Enabled */ unsigned pr9aq$v_cpucnf_icu0_ena : 1; /* ICU0 Enabled */ unsigned pr9aq$v_cpucnf_icu1_ena : 1; /* ICU1 Enabled */ unsigned pr9aq$v_cpucnf_cpu0_con : 1; /* CPU0 Connected */ unsigned pr9aq$v_cpucnf_cpu0_ie : 1; /* CPU0 I/O Interrupts Enabled */ unsigned pr9aq$v_cpucnf_cpu1_con : 1; /* CPU1 Connected */ unsigned pr9aq$v_cpucnf_cpu1_ie : 1; /* CPU1 I/O Interrupts Enabled */ unsigned pr9aq$v_cpucnf_cpu2_con : 1; /* CPU2 Connected */ unsigned pr9aq$v_cpucnf_cpu2_ie : 1; /* CPU2 I/O Interrupts Enabled */ unsigned pr9aq$v_cpucnf_cpu3_con : 1; /* CPU3 Connected */ unsigned pr9aq$v_cpucnf_cpu3_ie : 1; /* CPU3 I/O Interrupts Enabled */ } pr9aq$r_pr9aqcpucnf_bits; /* CPUx_PSED) */ __struct { /* TXFCT register */ unsigned pr9aq$v_txfct_funct : 8; /* Function Code */ unsigned pr9aq$v_txfct_sparam : 16; /* SPARAM */ unsigned pr9aq$v_txfct_spare0 : 5; /* Unused */ unsigned pr9aq$v_txfct_status : 1; /* Status Bit */ unsigned pr9aq$v_txfct_intena : 1; /* Interrupt Enable Bit */ unsigned pr9aq$v_txfct_ready : 1; /* Ready Bit */ } pr9aq$r_pr9aqtxfct_bits; __struct { /* RXFCT register */ unsigned pr9aq$v_rxfct_funct : 8; /* Function Code */ unsigned pr9aq$v_rxfct_sparam : 16; /* SPARAM */ unsigned pr9aq$v_rxfct_spare0 : 5; /* Unused */ unsigned pr9aq$v_rxfct_status : 1; /* Status Bit */ unsigned pr9aq$v_rxfct_intena : 1; /* Interrupt Enable Bit */ unsigned pr9aq$v_rxfct_valid : 1; /* Valid Bit */ } pr9aq$r_pr9aqrxfct_bits; } ; #if !defined(__VAXC) && !defined(VAXC) #define pr9aq$v_sid_serial pr9aq$r_pr9aqsid_bits.pr9aq$v_sid_serial #define pr9aq$v_sid_plant pr9aq$r_pr9aqsid_bits.pr9aq$v_sid_plant #define pr9aq$v_sid_systype2 pr9aq$r_pr9aqsid_bits.pr9aq$v_sid_systype2 #define pr9aq$v_sid_revlvl pr9aq$r_pr9aqsid_bits.pr9aq$v_sid_revlvl #define pr9aq$v_sid_systype pr9aq$r_pr9aqsid_bits.pr9aq$v_sid_systype #define pr9aq$v_sid_type pr9aq$r_pr9aqsid_bits.pr9aq$v_sid_type #define pr9aq_xsid$v_arch_id pr9aq$r_pr9aqxsid_bits.pr9aq_xsid$v_arch_id #define pr9aq_xsid$v_vector pr9aq$r_pr9aqxsid_bits.pr9aq_xsid$v_vector #define pr9aq_xsid$v_cpus pr9aq$r_pr9aqxsid_bits.pr9aq_xsid$v_cpus #define pr9aq_xsid$v_mmodel pr9aq$r_pr9aqxsid_bits.pr9aq_xsid$v_mmodel #define pr9aq_xsid$v_sys_type pr9aq$r_pr9aqxsid_bits.pr9aq_xsid$v_sys_type #define pr9aq$v_cpucnf_cpu_avl pr9aq$r_pr9aqcpucnf_bits.pr9aq$v_cpucnf_cpu_avl #define pr9aq$v_cpucnf_cpu_psed pr9aq$r_pr9aqcpucnf_bits.pr9aq$v_cpucnf_cpu_psed #define pr9aq$v_cpucnf_vbox_avl pr9aq$r_pr9aqcpucnf_bits.pr9aq$v_cpucnf_vbox_avl #define pr9aq$v_cpucnf_xja_avl pr9aq$r_pr9aqcpucnf_bits.pr9aq$v_cpucnf_xja_avl #define pr9aq$v_cpucnf_34_bit pr9aq$r_pr9aqcpucnf_bits.pr9aq$v_cpucnf_34_bit #define pr9aq$v_cpucnf_primary pr9aq$r_pr9aqcpucnf_bits.pr9aq$v_cpucnf_primary #define pr9aq$v_cpucnf_rrintr pr9aq$r_pr9aqcpucnf_bits.pr9aq$v_cpucnf_rrintr #define pr9aq$v_cpucnf_mmu0_ena pr9aq$r_pr9aqcpucnf_bits.pr9aq$v_cpucnf_mmu0_ena #define pr9aq$v_cpucnf_mmu1_ena pr9aq$r_pr9aqcpucnf_bits.pr9aq$v_cpucnf_mmu1_ena #define pr9aq$v_cpucnf_icu0_ena pr9aq$r_pr9aqcpucnf_bits.pr9aq$v_cpucnf_icu0_ena #define pr9aq$v_cpucnf_icu1_ena pr9aq$r_pr9aqcpucnf_bits.pr9aq$v_cpucnf_icu1_ena #define pr9aq$v_cpucnf_cpu0_con pr9aq$r_pr9aqcpucnf_bits.pr9aq$v_cpucnf_cpu0_con #define pr9aq$v_cpucnf_cpu0_ie pr9aq$r_pr9aqcpucnf_bits.pr9aq$v_cpucnf_cpu0_ie #define pr9aq$v_cpucnf_cpu1_con pr9aq$r_pr9aqcpucnf_bits.pr9aq$v_cpucnf_cpu1_con #define pr9aq$v_cpucnf_cpu1_ie pr9aq$r_pr9aqcpucnf_bits.pr9aq$v_cpucnf_cpu1_ie #define pr9aq$v_cpucnf_cpu2_con pr9aq$r_pr9aqcpucnf_bits.pr9aq$v_cpucnf_cpu2_con #define pr9aq$v_cpucnf_cpu2_ie pr9aq$r_pr9aqcpucnf_bits.pr9aq$v_cpucnf_cpu2_ie #define pr9aq$v_cpucnf_cpu3_con pr9aq$r_pr9aqcpucnf_bits.pr9aq$v_cpucnf_cpu3_con #define pr9aq$v_cpucnf_cpu3_ie pr9aq$r_pr9aqcpucnf_bits.pr9aq$v_cpucnf_cpu3_ie #define pr9aq$v_txfct_funct pr9aq$r_pr9aqtxfct_bits.pr9aq$v_txfct_funct #define pr9aq$v_txfct_sparam pr9aq$r_pr9aqtxfct_bits.pr9aq$v_txfct_sparam #define pr9aq$v_txfct_spare0 pr9aq$r_pr9aqtxfct_bits.pr9aq$v_txfct_spare0 #define pr9aq$v_txfct_status pr9aq$r_pr9aqtxfct_bits.pr9aq$v_txfct_status #define pr9aq$v_txfct_intena pr9aq$r_pr9aqtxfct_bits.pr9aq$v_txfct_intena #define pr9aq$v_txfct_ready pr9aq$r_pr9aqtxfct_bits.pr9aq$v_txfct_ready #define pr9aq$v_rxfct_funct pr9aq$r_pr9aqrxfct_bits.pr9aq$v_rxfct_funct #define pr9aq$v_rxfct_sparam pr9aq$r_pr9aqrxfct_bits.pr9aq$v_rxfct_sparam #define pr9aq$v_rxfct_spare0 pr9aq$r_pr9aqrxfct_bits.pr9aq$v_rxfct_spare0 #define pr9aq$v_rxfct_status pr9aq$r_pr9aqrxfct_bits.pr9aq$v_rxfct_status #define pr9aq$v_rxfct_intena pr9aq$r_pr9aqrxfct_bits.pr9aq$v_rxfct_intena #define pr9aq$v_rxfct_valid pr9aq$r_pr9aqrxfct_bits.pr9aq$v_rxfct_valid #endif /* #if !defined(__VAXC) && !defined(VAXC) */ #ifdef __cplusplus } #endif #pragma standard #endif /* __PR9AQDEF_LOADED */