/********************************************************************************************************************************/ /* Created: 15-MAR-2001 23:38:08 by OpenVMS SDL EV1-33 */ /* Source: 15-MAR-2001 23:34:16 _$11$DUA933:[BUILD.SDL]STARDEFMP.SDI;1 */ /********************************************************************************************************************************/ /*** MODULE $PR8SSDEF ***/ #ifndef __PR8SSDEF_LOADED #define __PR8SSDEF_LOADED 1 #pragma nostandard #ifdef __cplusplus extern "C" { #define __unknown_params ... #else #define __unknown_params #endif #if !defined(__VAXC) && !defined(VAXC) #define __struct struct #define __union union #else #define __struct variant_struct #define __union variant_union #endif #define PR8SS$_IPIR 22 /* Interprocessor Interrupt Reg. */ #define PR8SS$_NICR 25 /* Interval Clock Next Interval Register */ #define PR8SS$_ICR 26 /* Interval Clock Interval Count Register */ #define PR8SS$_TODR 27 /* Time Of Day Register */ #define PR8SS$_TBDR 36 /* Translation Buffer Disable Register */ #define PR8SS$_CADR 37 /* Cache Disable Register */ #define PR8SS$_MCESR 38 /* Machine Check Error Summary Register */ #define PR8SS$_ACCS 40 /* Floating Point Accellerator Register */ #define PR8SS$_WCSA 44 /* WCS Address Register */ #define PR8SS$_WCSD 45 /* WCS Data Register */ #define PR8SS$_WCSC 46 /* WCS Cam Register */ #define PR8SS$_PME 61 /* Performance Monitor Enable */ #define PR8SS$_RXCS1 80 /* Serial Line 1 Receive CSR */ #define PR8SS$_RXDB1 81 /* Serial Line 1 Receive Data Buffer */ #define PR8SS$_TXCS1 82 /* Serial Line 1 Transmit CSR */ #define PR8SS$_TXDB1 83 /* Serial Line 1 Transmit Data Buffer */ #define PR8SS$_RXCS2 84 /* Serial Line 2 Receive CSR */ #define PR8SS$_RXDB2 85 /* Serial Line 2 Receive Data Buffer */ #define PR8SS$_TXCS2 86 /* Serial Line 2 Transmit CSR */ #define PR8SS$_TXDB2 87 /* Serial Line 2 Transmit Data Buffer */ #define PR8SS$_RXCS3 88 /* Serial Line 3 Receive CSR */ #define PR8SS$_RXDB3 89 /* Serial Line 3 Receive Data Buffer */ #define PR8SS$_TXCS3 90 /* Serial Line 3 Transmit CSR */ #define PR8SS$_TXDB3 91 /* Serial Line 3 Transmit Data Buffer */ #define PR8SS$_RXCD 92 /* Receive Console Data Register */ #define PR8SS$_CACHEX 93 /* Cache Invalidate Register */ #define PR8SS$_BINID 94 /* BI Node ID Register */ #define PR8SS$_BIINIT 95 /* BI Init Nodes Register */ #define PR8SS$M_SID_SECP 0x100 #define PR8SS$M_RXCS_IE 0x40 #define PR8SS$M_RXCS_DONE 0x80 #define PR8SS$M_RXDB_ERR 0x8000 #define PR8SS$M_TXCS_IE 0x40 #define PR8SS$M_TXCS_RDY 0x80 #define PR8SS$M_TXCS_BRE 0x100 #define PR8SS$_BAUD300 0 /* Baud Rate of 300 */ #define PR8SS$_BAUD600 1 /* Baud Rate of 600 */ #define PR8SS$_BAUD1200 2 /* Baud Rate of 1200 */ #define PR8SS$_BAUD2400 3 /* Baud Rate of 2400 */ #define PR8SS$_BAUD4800 4 /* Baud Rate of 4800 */ #define PR8SS$_BAUD9600 5 /* Baud Rate of 9600 */ #define PR8SS$_BAUD19200 6 /* Baud Rate of 19200 */ #define PR8SS$_BAUD38400 7 /* Baud Rate of 38400 */ #define PR8SS$_BOOTCPU 2 /* Boot CPU Command */ #define PR8SS$_CLRWARM 3 /* Clear Warm-start Flag */ #define PR8SS$_CLRCOLD 4 /* Clear Cold-start Flag */ #define PR8SS$M_CADR_D 0x1 #define PR8SS$M_CADR_H 0x2 #define PR8SS$M_RXCD_BSY 0x8000 union pr8ssdef { __struct { /* Read only SID register */ unsigned pr8ss$v_sid_ucrev : 8; /* Ucode Revision Level */ unsigned pr8ss$v_sid_secp : 1; /* Secondary Patch Bit */ unsigned pr8ss$v_sid_patrev : 10; /* Patch Rev Level */ unsigned pr8ss$v_sid_cpurev : 4; /* CPU Rev level */ unsigned pr8ss$v_sid_v8250 : 1; /* 1=8250 (KA825), 0=8200 (KA820) */ unsigned pr8ss$v_sid_type : 8; /* CPU Type Code */ } pr8ss$r_pr8sssid_bits; __struct { /* Console RCV CSR */ unsigned pr8ss$$_fill_1 : 6; /* */ unsigned pr8ss$v_rxcs_ie : 1; /* Interrupt Enable */ unsigned pr8ss$v_rxcs_done : 1; /* 1=> Char. received */ } pr8ss$r_pr8ssrxcs_bits; __struct { /* Console RCV Data Register */ unsigned pr8ss$v_rxdb_data : 8; /* Received Data */ unsigned pr8ss$$_fill_2 : 7; /* */ unsigned pr8ss$v_rxdb_err : 1; /* Error */ } pr8ss$r_pr8ssrxdb_bits; __struct { /* Console Transmit CSR */ unsigned pr8ss$$_fill_3 : 6; /* */ unsigned pr8ss$v_txcs_ie : 1; /* Interrupt Enable */ unsigned pr8ss$v_txcs_rdy : 1; /* Ready */ unsigned pr8ss$v_txcs_bre : 1; /* (WO) Baud Rate Enable */ unsigned pr8ss$$_fill_4 : 1; /* */ unsigned pr8ss$v_txcs_baud : 3; /* Baud Rate */ /* Values to set baud rates */ unsigned pr8ss$v_fill_77 : 3; } pr8ss$r_pr8sstxcs_bits; __struct { /* Console Transmit Data Register */ unsigned pr8ss$v_txdb_data : 8; /* Data to Transmit */ unsigned pr8ss$v_txdb_id : 4; /* ID - Destination of */ /* transmitted data - */ /* 0=>UART0, F=>Console */ /* command */ /* Possible Console Commands */ unsigned pr8ss$v_fill_78 : 4; } pr8ss$r_pr8sstxdb_bits; __struct { /* Cache Disable Register */ unsigned pr8ss$v_cadr_d : 1; /* Disable Cache */ unsigned pr8ss$v_cadr_h : 1; /* Force 100% Cache Hits */ unsigned pr8ss$v_fill_79 : 6; } pr8ss$r_pr8sscadr_bits; __struct { /* WCS (Patch) Address Reg */ unsigned pr8ss$v_wcsa_data : 8; /* High Order Data Bits */ unsigned pr8ss$$_fill_5 : 8; /* */ unsigned pr8ss$v_wcsa_ramadr : 16; /* Ram Address */ } pr8ss$r_pr8sswcsa_bits; __struct { /* WCS (Patch) CAM Reg */ unsigned pr8ss$$_fill_6 : 8; /* */ unsigned pr8ss$v_wcsc_camadr : 8; /* Cam Address */ unsigned pr8ss$v_wcsc_romadr : 16; /* Rom Address */ } pr8ss$r_pr8sswcsc_bits; __struct { /* Receive Console Data Register */ unsigned pr8ss$v_rxcd_data : 8; /* Received Data */ unsigned pr8ss$v_rxcd_nodeid : 4; /* Sender's Node ID */ unsigned pr8ss$$_fill_7 : 3; /* */ unsigned pr8ss$v_rxcd_bsy : 1; /* Set=>Data has been received */ } pr8ss$r_pr8ssrxcd_bits; __struct { /* Cache Invalidate Register */ unsigned pr8ss$$_fill_8 : 9; /* */ unsigned pr8ss$v_cachex_pfn : 21; /* Physical Page Number */ unsigned pr8ss$v_fill_80 : 2; } pr8ss$r_pr8sscachex_bits; __struct { /* BI Node ID Register */ unsigned pr8ss$v_binid_nid : 4; /* BI Node ID this node */ unsigned pr8ss$v_fill_81 : 4; } pr8ss$r_pr8ssbinid_bits; } ; #if !defined(__VAXC) && !defined(VAXC) #define pr8ss$v_sid_ucrev pr8ss$r_pr8sssid_bits.pr8ss$v_sid_ucrev #define pr8ss$v_sid_secp pr8ss$r_pr8sssid_bits.pr8ss$v_sid_secp #define pr8ss$v_sid_patrev pr8ss$r_pr8sssid_bits.pr8ss$v_sid_patrev #define pr8ss$v_sid_cpurev pr8ss$r_pr8sssid_bits.pr8ss$v_sid_cpurev #define pr8ss$v_sid_v8250 pr8ss$r_pr8sssid_bits.pr8ss$v_sid_v8250 #define pr8ss$v_sid_type pr8ss$r_pr8sssid_bits.pr8ss$v_sid_type #define pr8ss$v_rxcs_ie pr8ss$r_pr8ssrxcs_bits.pr8ss$v_rxcs_ie #define pr8ss$v_rxcs_done pr8ss$r_pr8ssrxcs_bits.pr8ss$v_rxcs_done #define pr8ss$v_rxdb_data pr8ss$r_pr8ssrxdb_bits.pr8ss$v_rxdb_data #define pr8ss$v_rxdb_err pr8ss$r_pr8ssrxdb_bits.pr8ss$v_rxdb_err #define pr8ss$v_txcs_ie pr8ss$r_pr8sstxcs_bits.pr8ss$v_txcs_ie #define pr8ss$v_txcs_rdy pr8ss$r_pr8sstxcs_bits.pr8ss$v_txcs_rdy #define pr8ss$v_txcs_bre pr8ss$r_pr8sstxcs_bits.pr8ss$v_txcs_bre #define pr8ss$v_txcs_baud pr8ss$r_pr8sstxcs_bits.pr8ss$v_txcs_baud #define pr8ss$v_txdb_data pr8ss$r_pr8sstxdb_bits.pr8ss$v_txdb_data #define pr8ss$v_txdb_id pr8ss$r_pr8sstxdb_bits.pr8ss$v_txdb_id #define pr8ss$v_cadr_d pr8ss$r_pr8sscadr_bits.pr8ss$v_cadr_d #define pr8ss$v_cadr_h pr8ss$r_pr8sscadr_bits.pr8ss$v_cadr_h #define pr8ss$v_wcsa_data pr8ss$r_pr8sswcsa_bits.pr8ss$v_wcsa_data #define pr8ss$v_wcsa_ramadr pr8ss$r_pr8sswcsa_bits.pr8ss$v_wcsa_ramadr #define pr8ss$v_wcsc_camadr pr8ss$r_pr8sswcsc_bits.pr8ss$v_wcsc_camadr #define pr8ss$v_wcsc_romadr pr8ss$r_pr8sswcsc_bits.pr8ss$v_wcsc_romadr #define pr8ss$v_rxcd_data pr8ss$r_pr8ssrxcd_bits.pr8ss$v_rxcd_data #define pr8ss$v_rxcd_nodeid pr8ss$r_pr8ssrxcd_bits.pr8ss$v_rxcd_nodeid #define pr8ss$v_rxcd_bsy pr8ss$r_pr8ssrxcd_bits.pr8ss$v_rxcd_bsy #define pr8ss$v_cachex_pfn pr8ss$r_pr8sscachex_bits.pr8ss$v_cachex_pfn #define pr8ss$v_binid_nid pr8ss$r_pr8ssbinid_bits.pr8ss$v_binid_nid #endif /* #if !defined(__VAXC) && !defined(VAXC) */ #ifdef __cplusplus } #endif #pragma standard #endif /* __PR8SSDEF_LOADED */