/********************************************************************************************************************************/
/* Created: 15-MAR-2001 23:38:08 by OpenVMS SDL EV1-33     */
/* Source:  15-MAR-2001 23:34:16 _$11$DUA933:[BUILD.SDL]STARDEFMP.SDI;1 */
/********************************************************************************************************************************/
/*** MODULE $PR8PSDEF ***/
#ifndef __PR8PSDEF_LOADED
#define __PR8PSDEF_LOADED 1
 
#pragma nostandard
 
#ifdef __cplusplus
    extern "C" {
#define __unknown_params ...
#else
#define __unknown_params
#endif
 
#if !defined(__VAXC) && !defined(VAXC)
#define __struct struct
#define __union union
#else
#define __struct variant_struct
#define __union variant_union
#endif
 
#define PR8PS$M_RXDB_P0AVL 0x1
#define PR8PS$M_RXDB_P1AVL 0x2
#define PR8PS$M_RXDB_P2AVL 0x4
#define PR8PS$M_RXDB_P3AVL 0x8
#define PR8PS$M_RXDB_DKEY 0x10
#define PR8PS$M_RXDB_VKEY 0x20
union pr8psdef {
    __struct  {                         /* Read only SID register           */
        unsigned pr8ps$v_sid_serial : 15; /* Processor Serial Number        */
        unsigned pr8ps$v_sid_cpurev : 7; /* CPU Revision Level              */
        unsigned pr8ps$v_sid_cpunum : 2; /* CPU number (0-3)                */
        unsigned pr8ps$v_sid_type : 8;  /* CPU Type Code                    */
        } pr8ps$r_pr8pssid_bits;
/*                                                                          */
/*	Bit definitions for data returned by the GET_CPU_INFO console command */
/*	through the RXDB IPR.                                               */
/*                                                                          */
    __struct  {                         /*                                  */
        unsigned pr8ps$v_rxdb_p0avl : 1; /* Processor 0 avail               */
        unsigned pr8ps$v_rxdb_p1avl : 1; /* Processor 1 avail               */
        unsigned pr8ps$v_rxdb_p2avl : 1; /* Processor 2 avail               */
        unsigned pr8ps$v_rxdb_p3avl : 1; /* Processor 3 avail               */
        unsigned pr8ps$v_rxdb_dkey : 1; /* Diag key                         */
        unsigned pr8ps$v_rxdb_vkey : 1; /* VMS key                          */
        unsigned pr8ps$v_rxdb_primid : 2; /* Processor num of primary       */
        } pr8ps$r_pr8psrxdb_bits1;
/*                                                                          */
/* Definitions for Polarstar REVR2                                          */
/*                                                                          */
    __struct  {                         /* Read only REVR2 register         */
        unsigned pr8ps$v_revr2_pclk : 4; /* PCLK revision level             */
        unsigned pr8ps$v_revr2_bkpln : 4; /* Backplane revision             */
        unsigned pr8ps$v_revr2_cnsrv : 8; /* Console Revision Level         */
        unsigned pr8ps$v_revr2_uwcs : 8; /* WCS Revision Level              */
        unsigned pr8ps$v_revr2_ucode : 8; /* Microcode Revision Level       */
        } pr8ps$r_pr8psrevr2_bits;
    } ;
 
#if !defined(__VAXC) && !defined(VAXC)
#define pr8ps$v_sid_serial pr8ps$r_pr8pssid_bits.pr8ps$v_sid_serial
#define pr8ps$v_sid_cpurev pr8ps$r_pr8pssid_bits.pr8ps$v_sid_cpurev
#define pr8ps$v_sid_cpunum pr8ps$r_pr8pssid_bits.pr8ps$v_sid_cpunum
#define pr8ps$v_sid_type pr8ps$r_pr8pssid_bits.pr8ps$v_sid_type
#define pr8ps$v_rxdb_p0avl pr8ps$r_pr8psrxdb_bits1.pr8ps$v_rxdb_p0avl
#define pr8ps$v_rxdb_p1avl pr8ps$r_pr8psrxdb_bits1.pr8ps$v_rxdb_p1avl
#define pr8ps$v_rxdb_p2avl pr8ps$r_pr8psrxdb_bits1.pr8ps$v_rxdb_p2avl
#define pr8ps$v_rxdb_p3avl pr8ps$r_pr8psrxdb_bits1.pr8ps$v_rxdb_p3avl
#define pr8ps$v_rxdb_dkey pr8ps$r_pr8psrxdb_bits1.pr8ps$v_rxdb_dkey
#define pr8ps$v_rxdb_vkey pr8ps$r_pr8psrxdb_bits1.pr8ps$v_rxdb_vkey
#define pr8ps$v_rxdb_primid pr8ps$r_pr8psrxdb_bits1.pr8ps$v_rxdb_primid
#define pr8ps$v_revr2_pclk pr8ps$r_pr8psrevr2_bits.pr8ps$v_revr2_pclk
#define pr8ps$v_revr2_bkpln pr8ps$r_pr8psrevr2_bits.pr8ps$v_revr2_bkpln
#define pr8ps$v_revr2_cnsrv pr8ps$r_pr8psrevr2_bits.pr8ps$v_revr2_cnsrv
#define pr8ps$v_revr2_uwcs pr8ps$r_pr8psrevr2_bits.pr8ps$v_revr2_uwcs
#define pr8ps$v_revr2_ucode pr8ps$r_pr8psrevr2_bits.pr8ps$v_revr2_ucode
#endif		/* #if !defined(__VAXC) && !defined(VAXC) */
 
/*                                                                          */
/* Definitions for extended Polarstar commands                              */
/*                                                                          */
#define TXDB$K_BOOT_CPU_0 20            /* 14 - Boot CPU 0                  */
#define TXDB$K_BOOT_CPU_1 21            /* 15 - Boot CPU 1                  */
#define TXDB$K_BOOT_CPU_2 22            /* 16 - Boot CPU 2                  */
#define TXDB$K_BOOT_CPU_3 23            /* 17 - Boot CPU 3                  */
#define TXDB$K_DISAB_CPU_0 24           /* 18 - Disable CPU 0               */
#define TXDB$K_DISAB_CPU_1 25           /* 19 - Disable CPU 1               */
#define TXDB$K_DISAB_CPU_2 26           /* 1A - Disable CPU 2               */
#define TXDB$K_DISAB_CPU_3 27           /* 1B - Disable CPU 3               */
#define TXDB$K_FNP_CPU_0 28             /* 1C - Force Next Primary to be CPU 0 */
#define TXDB$K_FNP_CPU_1 29             /* 1D - Force Next Primary to be CPU 1 */
#define TXDB$K_FNP_CPU_2 30             /* 1E - Force Next Primary to be CPU 2 */
#define TXDB$K_FNP_CPU_3 31             /* 1F - Force Next Primary to be CPU 3 */
#define TXDB$K_CSA1_INFO 32             /* 20 - Get info on CSA1 [not implemented] */
#define TXDB$K_CSA2_INFO 33             /* 21 - Get info on CSA2 [not implemented] */
#define TXDB$K_CSA3_INFO 34             /* 22 - Get info on CSA3            */
 
#ifdef __cplusplus
    }
#endif
#pragma standard
 
#endif /* __PR8PSDEF_LOADED */