/********************************************************************************************************************************/ /* Created: 15-MAR-2001 23:38:06 by OpenVMS SDL EV1-33 */ /* Source: 15-MAR-2001 23:34:16 _$11$DUA933:[BUILD.SDL]STARDEFMP.SDI;1 */ /********************************************************************************************************************************/ /*** MODULE $PR730DEF ***/ #ifndef __PR730DEF_LOADED #define __PR730DEF_LOADED 1 #pragma nostandard #ifdef __cplusplus extern "C" { #define __unknown_params ... #else #define __unknown_params #endif #if !defined(__VAXC) && !defined(VAXC) #define __struct struct #define __union union #else #define __struct variant_struct #define __union variant_union #endif #define PR730$_NICR 25 /* INTERVAL CLOCK NEXT INTERVAL REGISTER */ #define PR730$_ICR 26 /* INTERVAL CLOCK INTERVAL COUNT REGISTER */ #define PR730$_TODR 27 /* TIME OF DAY REGISTER */ #define PR730$_ACCS 40 /* ACCELERATOR CONTROL STATUS REGISTER */ #define PR730$_ACCR 41 /* ACCELERATOR RESERVED */ #define PR730$_PME 61 /* PERFORMANCE MONITOR ENABLE */ #define PR730$_CMIERR 23 /* CMI ERROR SUMMARY REGISTER */ #define PR730$_CSRS 28 /* CONSOLE BLK STORE RCV STATUS */ #define PR730$_CSRD 29 /* CONSOLE BLK STORE RCV DATA */ #define PR730$_CSTS 30 /* CONSOLE BLK STORE XMIT STATUS */ #define PR730$_CSTD 31 /* CONSOLE BLK STORE XMIT DATA */ #define PR730$_TBDR 36 /* TB DISABLE REGISTER */ #define PR730$_CADR 37 /* CACHE DISABLE REGISTER */ #define PR730$_MCESR 38 /* MACHINE CHECK ERROR SUMMARY REG */ #define PR730$_CAER 39 /* CACHE ERROR REGISTER */ #define PR730$_UBRESET 55 /* UNIBUS I/O RESET REGISTER */ #ifdef __cplusplus } #endif #pragma standard #endif /* __PR730DEF_LOADED */