/********************************************************************************************************************************/ /* Created: 15-MAR-2001 23:38:07 by OpenVMS SDL EV1-33 */ /* Source: 15-MAR-2001 23:34:16 _$11$DUA933:[BUILD.SDL]STARDEFMP.SDI;1 */ /********************************************************************************************************************************/ /*** MODULE $PR560DEF ***/ #ifndef __PR560DEF_LOADED #define __PR560DEF_LOADED 1 #pragma nostandard #ifdef __cplusplus extern "C" { #define __unknown_params ... #else #define __unknown_params #endif #if !defined(__VAXC) && !defined(VAXC) #define __struct struct #define __union union #else #define __struct variant_struct #define __union variant_union #endif #ifndef __PR560DEF_LOADED #define __PR560DEF_LOADED 1 #define PR560$K_REVISION 1 /* Revision number of this file */ /* In the definitions below, registers are annotated with one of the following */ /* symbols: */ /* */ /* RW - The register may be read and written */ /* RO - The register may only be read */ /* WO - The register may only be written */ /* */ /* For RO and WO registers, all bits and fields within the register are also */ /* read-only or write-only. For RW registers, each bit or field within */ /* the register is annotated with one of the following: */ /* */ /* RW - The bit/field may be read and written */ /* RO - The bit/field may be read; writes are ignored */ /* WO - The bit/field may be written; reads return an UNPREDICTABLE result. */ /* WZ - The bit/field may be written; reads return a 0 */ /* WC - The bit/field may be read; writes cause state to clear */ /* RC - The bit/field may be read, which also causes state to clear; writes are ignored */ #define PR560$_IPL 18 /* Interrupt Priority Level (RW) */ #define PR560$_ICCS 24 /* Interval Clock Control/Status (RW) */ #define ICCS560$M_RUN 0x1 #define ICCS560$M_XFR 0x10 #define ICCS560$M_SGL 0x20 #define ICCS560$M_IE 0x40 #define ICCS560$M_TINT 0x80 #define ICCS560$M_ERR 0x80000000 #define PR560$_NICR 25 /* Next Interval Count (WO) */ #define PR560$_ICR 26 /* Interval Count (RO) */ #define PR560$_TODR 27 /* Time Of Year Register (RW) */ #define PR560$_MCESR 38 /* Machine check error register (WO) */ #define PR560$_SAVPC 42 /* Console saved PC (RO) */ #define PR560$_SAVPSL 43 /* Console saved PSL (RO) */ #define SAVPSL560$M_PSL_LO 0xFF #define SAVPSL560$M_HALTCODE 0x3F00 #define SAVPSL560$K_ERR_HLTPIN 2 /* HALT_L pin asserted */ #define SAVPSL560$K_ERR_PWRUP 3 /* Initial powerup */ #define SAVPSL560$K_ERR_INTSTK 4 /* Interrupt stack not valid */ #define SAVPSL560$K_ERR_DOUBLE 5 /* Machine check during exception processing */ #define SAVPSL560$K_ERR_HLTINS 6 /* Halt instruction in kernel mode */ #define SAVPSL560$K_ERR_ILLVEC 7 /* Illegal SCB vector (bits<1:0>=11) */ #define SAVPSL560$K_ERR_WCSVEC 8 /* WCS SCB vector (bits<1:0>=10) */ #define SAVPSL560$K_ERR_CHMFI 10 /* CHMx on interrupt stack */ #define SAVPSL560$K_ERR_IE0 16 /* ACV/TNV during machine check processing */ #define SAVPSL560$K_ERR_IE1 17 /* ACV/TNV during KSNV processing */ #define SAVPSL560$K_ERR_IE2 18 /* Machine check during machine check processing */ #define SAVPSL560$K_ERR_IE3 19 /* Machine check during KSNV processing */ #define SAVPSL560$K_ERR_IE_PSL_101 25 /* PSL<26:24>=101 during interrupt or exception */ #define SAVPSL560$K_ERR_IE_PSL_110 26 /* PSL<26:24>=110 during interrupt or exception */ #define SAVPSL560$K_ERR_IE_PSL_111 27 /* PSL<26:24>=111 during interrupt or exception */ #define SAVPSL560$K_ERR_REI_PSL_101 29 /* PSL<26:24>=101 during REI */ #define SAVPSL560$K_ERR_REI_PSL_110 30 /* PSL<26:24>=110 during REI */ #define SAVPSL560$K_ERR_REI_PSL_111 31 /* PSL<26:24>=111 during REI */ #define SAVPSL560$K_ERR_SELFTEST_FAILED 63 /* Powerup self test failed */ #define SAVPSL560$M_INVALID 0x4000 #define SAVPSL560$M_MAPEN 0x8000 #define SAVPSL560$M_PSL_HI 0xFFFF0000 #define PR560$_PME 61 /* Performance monitoring enable (RW) */ /* Ebox registers. */ #define PR560$_INTSYS 122 /* Interrupt system status register (RW) */ #define INTSYS560$M_SISR 0xFFFE #define INTSYS560$M_INT_ID 0x1F0000 #define INTSYS560$K_INT_ID_HALT 31 /* Halt pin */ #define INTSYS560$K_INT_ID_PWRFL 30 /* Power fail */ #define INTSYS560$K_INT_ID_H_ERR 29 /* Hard error */ #define INTSYS560$K_INT_ID_INT_TIM 28 /* Interval timer */ #define INTSYS560$K_INT_ID_PMON 27 /* Performance monitor */ #define INTSYS560$K_INT_ID_S_ERR 26 /* Soft error */ #define INTSYS560$K_INT_ID_IRQ3 23 /* IPL 17 device interrupt */ #define INTSYS560$K_INT_ID_IRQ2 22 /* IPL 16 device interrupt */ #define INTSYS560$K_INT_ID_IRQ1 21 /* IPL 15 device interrupt */ #define INTSYS560$K_INT_ID_IRQ0 20 /* IPL 14 device interrupt */ #define INTSYS560$K_INT_ID_SISR15 15 /* SISR<15> */ #define INTSYS560$K_INT_ID_SISR14 14 /* SISR<14> */ #define INTSYS560$K_INT_ID_SISR13 13 /* SISR<13> */ #define INTSYS560$K_INT_ID_SISR12 12 /* SISR<12> */ #define INTSYS560$K_INT_ID_SISR11 11 /* SISR<11> */ #define INTSYS560$K_INT_ID_SISR10 10 /* SISR<10> */ #define INTSYS560$K_INT_ID_SISR9 9 /* SISR<9> */ #define INTSYS560$K_INT_ID_SISR8 8 /* SISR<8> */ #define INTSYS560$K_INT_ID_SISR7 7 /* SISR<7> */ #define INTSYS560$K_INT_ID_SISR6 6 /* SISR<6> */ #define INTSYS560$K_INT_ID_SISR5 5 /* SISR<5> */ #define INTSYS560$K_INT_ID_SISR4 4 /* SISR<4> */ #define INTSYS560$K_INT_ID_SISR3 3 /* SISR<3> */ #define INTSYS560$K_INT_ID_SISR2 2 /* SISR<2> */ #define INTSYS560$K_INT_ID_SISR1 1 /* SISR<1> */ #define INTSYS560$K_INT_ID_NO_INT 0 /* No interrupt */ #define INTSYS560$M_INT_TIM_RESET 0x1000000 #define INTSYS560$M_S_ERR_RESET 0x8000000 #define INTSYS560$M_PMON_RESET 0x10000000 #define INTSYS560$M_HALT_RESET 0x80000000 #define PR560$_PMFCNT 123 /* Performance monitoring facility count register (RW) */ #define PMFCNT560$M_PMCTR0 0xFFFF #define PMFCNT560$M_PMCTR1 0xFFFF0000 #define PR560$_PCSCR 124 /* Patchable control store control register (RW) */ #define PCSCR560$M_PAR_PORT_DIS 0x100 #define PCSCR560$M_PCS_ENB 0x200 #define PCSCR560$M_PCS_WRITE 0x400 #define PCSCR560$M_RWL_SHIFT 0x800 #define PCSCR560$M_DATA 0x1000 #define PCSCR560$M_NONSTANDARD_PATCH 0x800000 #define PCSCR560$M_PATCH_REV 0x1F000000 #define PR560$_ECR 125 /* Ebox control register (RW) */ #define ECR560$M_VECTOR_PRESENT 0x1 #define ECR560$M_FBOX_ENABLE 0x2 #define ECR560$M_TIMEOUT_EXT 0x4 #define ECR560$M_FBOX_ST4_BYPASS_ENABLE 0x8 #define ECR560$M_TIMEOUT_OCCURRED 0x10 #define ECR560$M_TIMEOUT_TEST 0x20 #define ECR560$M_TIMEOUT_CLOCK 0x40 #define ECR560$M_FBOX_TEST_ENABLE 0x2000 #define ECR560$M_PMF_ENABLE 0x10000 #define ECR560$M_PMF_MUX 0x60000 #define ECR560$K_MUX_IBOX 0 /* Select Ibox */ #define ECR560$K_MUX_EBOX 1 /* Select Ebox */ #define ECR560$K_MUX_MBOX 2 /* Select Mbox */ #define ECR560$K_MUX_CBOX 3 /* Select Cbox */ #define ECR560$M_PMF_EMUX 0x380000 #define ECR560$K_EMUX_S3_STALL 0 /* Measure S3 stall against total cycles */ #define ECR560$K_EMUX_EM_PA_STALL 1 /* Measure EM+PA queue stall against total cycles */ #define ECR560$K_EMUX_CPI 2 /* Measure instructions retired against total cycles */ #define ECR560$K_EMUX_STALL 3 /* Measure total stalls against total cycles */ #define ECR560$K_EMUX_S3_STALL_PCT 4 /* Measure S3 stall against total stalls */ #define ECR560$K_EMUX_EM_PA_STALL_PCT 5 /* Measure EM+PA queue stall against total stalls */ #define ECR560$K_EMUX_UWORD 7 /* Count microword increments */ #define ECR560$M_PMF_LFSR 0x400000 #define ECR560$M_PMF_CLEAR 0x80000000 #define PR560$_MTBTAG 126 /* Mbox TB tag fill (WO) */ #define PR560$_MTBPTE 127 /* Mbox TB PTE fill (WO) */ /* Cbox registers. */ #define PR560$_BIU_CTL 160 /* Cbox control register (RW) */ #define BIU_CTL560$M_BC_EN 0x1 #define BIU_CTL560$M_ECC 0x2 #define BIU_CTL560$K_ECC_ECC 1 /* select ECC mode */ #define BIU_CTL560$K_ECC_PARITY 0 /* select Parity mode */ #define BIU_CTL560$M_OE 0x4 #define BIU_CTL560$M_BC_FHIT 0x8 #define BIU_CTL560$M_BC_SPD 0x30 #define BIU_CTL560$K_BC_SPD_2X 0 /* 2x cpu cycle */ #define BIU_CTL560$K_BC_SPD_3X 1 /* 3x cpu cycle */ #define BIU_CTL560$K_BC_SPD_4X 2 /* 4x cpu cycle */ #define BIU_CTL560$M_PCACHE_MODE 0x100 #define BIU_CTL560$M_QW_IO_RD 0x200 #define BIU_CTL560$M_PV 0x400 #define BIU_CTL560$M_IO_MAP 0x6000 #define BIU_CTL560$M_BC_SIZE 0x70000000 #define BIU_CTL560$K_BC_SIZE_128KB 0 /* Select 128KB Bcache */ #define BIU_CTL560$K_BC_SIZE_256KB 1 /* Select 256KB Bcache */ #define BIU_CTL560$K_BC_SIZE_512KB 2 /* Select 512KB Bcache */ #define BIU_CTL560$K_BC_SIZE_1MB 3 /* Select 1MB Bcache */ #define BIU_CTL560$K_BC_SIZE_2MB 4 /* Select 2MB Bcache */ #define BIU_CTL560$K_BC_SIZE_4MB 5 /* Select 4MB Bcache */ #define BIU_CTL560$K_BC_SIZE_8MB 6 /* Select 8MB Bcache */ #define BIU_CTL560$M_WS_IO 0x80000000 #define PR560$_DIAG_CTL 161 /* Diag control register (RW) */ #define DIAG_CTL560$M_TODR_TEST 0x40 #define DIAG_CTL560$M_TODR_INC 0x80 #define DIAG_CTL560$M_PACK_DISABLE 0x800 #define DIAG_CTL560$M_MAB_EN 0x1000 #define DIAG_CTL560$M_DISABLE_ECC_ERR 0x8000 #define DIAG_CTL560$M_PM_HIT_TYPE 0xE00000 #define DIAG_CTL560$M_PM_ACCESS_TYPE 0x7000000 #define DIAG_CTL560$M_SW_ECC 0x8000000 #define PR560$_BC_TAG 162 /* Bcache error tag (RO) */ #define BC_TAG560$M_HIT 0x800 #define BC_TAG560$M_TAGCTL_V 0x1000 #define BC_TAG560$M_TAGCTL_D 0x2000 #define BC_TAG560$M_TAGCTL_S 0x4000 #define BC_TAG560$M_TAGCTL_P 0x8000 #define BC_TAG560$M_TAG_P 0x10000 #define PR560$_BIU_STAT 164 /* Bcache error data status (WC) */ #define BIU_STAT560$M_BIU_HERR 0x1 #define BIU_STAT560$M_BIU_SERR 0x2 #define BIU_STAT560$M_BC_TPERR 0x4 #define BIU_STAT560$M_BC_TCPERR 0x8 #define BIU_STAT560$M_BIU_DSP_CMD 0x70 #define BIU_STAT560$K_WRITE_UNLOCK_IO 0 /* WRITE_UNLOCK_IO cmd */ #define BIU_STAT560$K_IREAD 1 /* IREAD cmd */ #define BIU_STAT560$K_IREAD_IO 1 /* IREAD_IO cmd */ #define BIU_STAT560$K_WRITE 2 /* WRITE cmd */ #define BIU_STAT560$K_IO_WRITE 2 /* IO_WRITE cmd */ #define BIU_STAT560$K_WRITE_UNLOCK 3 /* WRITE_UNLOCK cmd */ #define BIU_STAT560$K_DREAD 4 /* DREAD cmd */ #define BIU_STAT560$K_DREAD_IO 5 /* DREAD_IO cmd */ #define BIU_STAT560$K_DREAD_LOCK 6 /* DREAD_LOCK cmd */ #define BIU_STAT560$K_DREAD_LOCK_IO 6 /* DREAD_LOCK_IO cmd */ #define BIU_STAT560$M_BIU_SEO 0x80 #define BIU_STAT560$M_FILL_ECC 0x100 #define BIU_STAT560$M_FILL_CRD 0x200 #define BIU_STAT560$M_BIU_DPERR 0x400 #define BIU_STAT560$M_FILL_IRD 0x800 #define BIU_STAT560$M_FILL_SEO 0x4000 #define BIU_STAT560$M_RAZ 0x8000 #define BIU_STAT560$M_FILL_DSP_CMD 0xF0000 #define BIU_STAT560$K_F_IREAD 2 /* IREAD cmd */ #define BIU_STAT560$K_F_IREAD_IO 3 /* IREAD_IO cmd */ #define BIU_STAT560$K_F_WRITE_UNLOCK_IO 1 /* WRITE_UNLOCK_IO cmd */ #define BIU_STAT560$K_F_IO_WRITE 5 /* WRITE_IO cmd */ #define BIU_STAT560$K_F_WRITE 6 /* WRITE cmd */ #define BIU_STAT560$K_F_WRITE_UNLOCK 7 /* WRITE_UNLOCK cmd */ #define BIU_STAT560$K_F_DREAD 8 /* DREAD cmd 100X */ #define BIU_STAT560$K_F_DREAD2 9 /* DREAD cmd 100X */ #define BIU_STAT560$K_F_DREAD_IO 10 /* DREAD_IO cmd */ #define BIU_STAT560$K_F_DREAD_LOCK 12 /* DREAD_LOCK cmd */ #define BIU_STAT560$K_F_DREAD_LOCK_IO 13 /* DREAD_LOCK_IO cmd */ #define BIU_STAT560$M_LST_WRT 0x100000 #define BIU_STAT560$M_RSVD 0xFE00000 #define BIU_STAT560$M_BIU_ADDR 0x30000000 #define BIU_STAT560$M_FILL_ADDR 0xC0000000 #define PR560$_BIU_ADDR 166 /* error address associated with BIU errors (RO) */ #define PR560$_FILL_SYN 168 /* Syndrome bits associated with bad quadword during fill (RO) */ #define PR560$_FILL_ADDR 170 /* error address associated with FILL errors (RO) */ #define PR560$_STC_RESULT 172 /* Result of last store conditional (RW) */ #define STC_RESULT560$M_PASS 0x4 #define PR560$_BEDECC 174 /* Alternate source of ECC check bits (W) */ #define PR560$_CHALT 176 /* Console HALT register (RW) */ /* Serial line I/O registers */ #define PR560$_SIO 178 /* Serial line I/O register (RW) */ #define SIO560$M_SIO_IN 0x1 #define SIO560$M_SIO_OUT 0x2 #define PR560$_SOE_IE 180 /* Serial line I/O register (RW) */ #define SOE560$M_SROM_OE 0x1 #define SOE560$M_SROM_FAST 0x2 #define SOE560$M_WAFER_ROW_COL_ID 0xFFF00000 #define PR560$_QW_PACK 184 /* Pack next two longword writes (WO) */ #define PR560$_CLR_IO_PACK 185 /* Clear QW IO Pack (WO) */ /* Ibox registers. */ #define PR560$_VMAR 208 /* VIC memory address register (RW) */ #define VMAR560$M_LW 0x4 #define VMAR560$M_SUB_BLOCK 0x18 #define VMAR560$M_ROW_INDEX 0x7E0 #define VMAR560$M_ADDR 0xFFFFF800 #define PR560$_VTAG 209 /* VIC tag register (RW) */ #define VTAG560$M_V 0xF #define VTAG560$M_DP 0xF0 #define VTAG560$M_TP 0x100 #define VTAG560$M_TAG 0xFFFFF800 #define PR560$_VDATA 210 /* VIC data register (RW) */ #define PR560$_ICSR 211 /* Ibox control and status register (RW) */ #define ICSR560$M_ENABLE 0x1 #define ICSR560$M_LOCK 0x4 #define ICSR560$M_DPERR 0x8 #define ICSR560$M_TPERR 0x10 #define PR560$_BPCR 212 /* Ibox branch prediction control register (RW) */ #define BPCR560$M_HISTORY 0xF #define BPCR560$M_MISPREDICT 0x20 #define BPCR560$M_FLUSH_BHT 0x40 #define BPCR560$M_FLUSH_CTR 0x80 #define BPCR560$M_LOAD_HISTORY 0x100 #define BPCR560$M_BPU_ALGORITHM 0xFFFF0000 #define BPCR560$K_BPU_ALGORITHM 65226 /* default value for BPU_ALGORITHM field */ #define PR560$_BPC 214 /* Ibox Backup PC (RO) */ #define PR560$_BPCUNW 215 /* Ibox Backup PC with RLOG unwind (RO) */ /* Mbox internal memory management registers. */ #define PR560$_MP0BR 224 /* Mbox P0 base register (RW) */ #define PR560$_MP0LR 225 /* Mbox P0 length register (RW) */ #define PR560$_MP1BR 226 /* Mbox P1 base register (RW) */ #define PR560$_MP1LR 227 /* Mbox P1 length register (RW) */ #define PR560$_MSBR 228 /* Mbox system base register (RW) */ #define PR560$_MSLR 229 /* Mbox system length register (RW) */ #define PR560$_MMAPEN 230 /* Mbox memory management enable (RW) */ /* Mbox registers. */ #define PR560$_PAMODE 231 /* Mbox physical address mode (RW) */ #define PAMODE560$M_MODE 0x1 #define PAMODE560$K_PA_30 0 /* 30-bit PA mode */ #define PAMODE560$K_PA_32 1 /* 32-bit PA mode */ #define PR560$_MMEADR 232 /* Mbox memory management fault address (RO) */ #define PR560$_MMEPTE 233 /* Mbox memory management fault PTE address (RO) */ #define PR560$_MMESTS 234 /* Mbox memory management fault status (RO) */ #define MMESTS560$M_LV 0x1 #define MMESTS560$M_PTE_REF 0x2 #define MMESTS560$M_M 0x4 #define MMESTS560$M_FAULT 0xC000 #define MMESTS560$K_FAULT_ACV 1 /* ACV fault */ #define MMESTS560$K_FAULT_TNV 2 /* TNV fault */ #define MMESTS560$K_FAULT_M0 3 /* M=0 fault */ #define MMESTS560$M_SRC 0x1C000000 #define MMESTS560$M_LOCK 0xE0000000 #define PR560$_TBADR 236 /* Mbox TB parity error address (RO) */ #define PR560$_TBSTS 237 /* Mbox TB parity error status (RW) */ #define TBSTS560$M_LOCK 0x1 #define TBSTS560$M_DPERR 0x2 #define TBSTS560$M_TPERR 0x4 #define TBSTS560$M_EM_VAL 0x8 #define TBSTS560$M_CMD 0x1F0 #define TBSTS560$M_SRC 0xE0000000 #define SRC560$_EBOX_ERROR 0 /* Fault was EBOX reference */ #define SRC560$_IBOX_ERROR 4 /* Fault was IBOX reference */ #define SRC560$_IREAD_ERROR 6 /* Fault was IREAD reference */ #define SRC560$_MBOX_ERROR 7 /* Fault was MBOX reference */ /* Mbox Pcache registers */ #define PR560$_PCADR 242 /* Mbox Pcache parity error address (RO) */ #define PR560$_PCSTS 244 /* Mbox Pcache parity error status (RW) */ #define PCSTS560$M_LOCK 0x1 #define PCSTS560$M_DPERR 0x2 #define PCSTS560$M_RIGHT_BANK 0x4 #define PCSTS560$M_LEFT_BANK 0x8 #define PCSTS560$M_CMD 0x1F0 #define PCSTS560$M_PTE_ER_WR 0x200 #define PCSTS560$M_PTE_ER 0x400 #define PR560$_PCCTL 248 /* Mbox Pcache control (RW) */ #define PCCTL560$M_D_ENABLE 0x1 #define PCCTL560$M_I_ENABLE 0x2 #define PCCTL560$M_FORCE_HIT 0x4 #define PCCTL560$M_BANK_SEL 0x8 #define PCCTL560$M_P_ENABLE 0x10 #define PCCTL560$M_PMM 0xE0 #define PCCTL560$M_ELEC_DISABLE 0x100 #define PCCTL560$M_RED_ENABLE 0x200 #define PR560$_PCTAG 25165824 /* First of 256 Pcache tag IPRs (RW) */ #define PR560$_PCTAG_MAX 25173984 /* Last of 256 Pcache tag IPRs */ #define PCTAG560$_IPR_INCR 32 /* Increment between Pcache tag IPR numbers */ #define PCTAG560$_IPR_NUM 256 /* Number of Pcache tag IPRs */ #define PCTAG560$M_A 0x1 #define PCTAG560$M_V 0x1E #define PCTAG560$M_P 0x20 #define PCTAG560$M_TAG 0xFFFFF000 #define PCTAGA560$M_INDEX 0xFE0 #define PCTAGA560$M_B 0x1000 #define PR560$_PCDAP 29360128 /* First of 1024 Pcache data parity IPRs (RW) */ #define PR560$_PCDAP_MAX 29368312 /* Last of 1024 Pcache data parity IPRs */ #define PCDAP560$_IPR_INCR 8 /* Increment between Pcache data parity IPR numbers */ #define PCDAP560$_IPR_NUM 1024 /* Number of Pcache data parity IPRs */ #define PCDAP560$M_DATA_PARITY 0xFF union pr560def { /* Architecturally-defined registers which have different characteristics */ /* on this CPU. */ __struct { unsigned iccs560$v_run : 1; /* Run control (RW) */ unsigned iccs560$$$_fill_1 : 3; /* */ unsigned iccs560$v_xfr : 1; /* Transfer control (WO) */ unsigned iccs560$v_sgl : 1; /* Increment ICR (WO) */ unsigned iccs560$v_ie : 1; /* Interrupt Enable (RW) */ unsigned iccs560$v_tint : 1; /* Overflow interrupt (WC) */ unsigned iccs560$$$_fill_2 : 23; /* */ unsigned iccs560$v_err : 1; /* Overflow w/ INT set error(WC) */ } pr560r_pr560iccs_bits; __struct { unsigned savpsl560$v_psl_lo : 8; /* Saved PSL bits <7:0> */ unsigned savpsl560$v_haltcode : 6; /* Halt code containing one of the following values */ unsigned savpsl560$v_invalid : 1; /* Invalid SAVPSL if = 1 */ unsigned savpsl560$v_mapen : 1; /* MAPEN<0> */ unsigned savpsl560$v_psl_hi : 16; /* Saved PSL bits <31:16> */ } pr560r_pr560savpsl_bits; __struct { unsigned intsys560$$$_fill_1 : 1; unsigned intsys560$v_sisr : 15; /* SISR<15:1> (RW) */ unsigned intsys560$v_int_id : 5; /* ID of highest pending interrupt (RO) */ unsigned intsys560$$$_fill_2 : 3; unsigned intsys560$v_int_tim_reset : 1; /* Interval timer interrupt reset (WC) */ unsigned intsys560$$$_fill_3 : 2; unsigned intsys560$v_s_err_reset : 1; /* Soft error interrupt reset (WC) */ unsigned intsys560$v_pmon_reset : 1; /* Performance monitoring interrupt reset (WC) */ unsigned intsys560$$$_fill_4 : 2; /* */ unsigned intsys560$v_halt_reset : 1; /* Halt pin interrupt reset (WC) */ } pr560r_pr560intsys_bits; __struct { unsigned pmfcnt560$v_pmctr0 : 16; /* PMCTR0 word */ unsigned pmfcnt560$v_pmctr1 : 16; /* PMCTR1 word */ } pr560r_pr560pmfcnt_bits; __struct { unsigned pcscr560$$$_fill_1 : 8; unsigned pcscr560$v_par_port_dis : 1; /* Disable parallel port control of scan chain (WO) */ unsigned pcscr560$v_pcs_enb : 1; /* Enable use of patchable control store (WO) */ unsigned pcscr560$v_pcs_write : 1; /* Write scan chain to patchable control store (WO) */ unsigned pcscr560$v_rwl_shift : 1; /* Shift read-write latch scan chain by one bit (WO) */ unsigned pcscr560$v_data : 1; /* Data to be shifted into the PCS scan chain (WO) */ unsigned pcscr560$$$_fill_2 : 10; unsigned pcscr560$v_nonstandard_patch : 1; /* Non-standard patch bit (RW) */ unsigned pcscr560$v_patch_rev : 5; /* Patch revision number (RW) */ unsigned pcscr560$$$_fill_3 : 3; } pr560r_pr560pcscr_bits; __struct { unsigned ecr560$v_vector_present : 1; /* Vector unit present (RW) */ unsigned ecr560$v_fbox_enable : 1; /* Fbox enabled (RW) */ unsigned ecr560$v_timeout_ext : 1; /* Select external timebase for S3 stall timeout timer (RW) */ unsigned ecr560$v_fbox_st4_bypass_enable : 1; /* Fbox stage 4 conditional bypass enable (RW) */ unsigned ecr560$v_timeout_occurred : 1; /* S3 stall timeout occurred (WC) */ unsigned ecr560$v_timeout_test : 1; /* Select test mode for S3 stall timeout (RW) */ unsigned ecr560$v_timeout_clock : 1; /* Clock S3 timeout (RO) */ unsigned ecr560$$$_fill_1 : 6; /* */ unsigned ecr560$v_fbox_test_enable : 1; /* Enable test of Fbox (RW) */ unsigned ecr560$$$_fill_2 : 2; unsigned ecr560$v_pmf_enable : 1; /* Performance monitoring facility enable (RW) */ unsigned ecr560$v_pmf_mux : 2; /* Performance monitoring facility master select (RW) */ unsigned ecr560$v_pmf_emux : 3; /* Performance monitoring facility Ebox mux select (RW) */ unsigned ecr560$v_pmf_lfsr : 1; /* Performance monitoring facility Wbus LFSR enable (RW) */ unsigned ecr560$$$_fill_3 : 8; unsigned ecr560$v_pmf_clear : 1; /* Clear performance monitoring hardware counters (WO) */ } pr560r_pr560ecr_bits; /* Mbox TB registers. */ /* These registers are for testability and diagnostics use only. */ /* They should not be referenced in normal operation. */ __struct { unsigned biu_ctl560$v_bc_en : 1; /* Enable Bcache (RW) */ unsigned biu_ctl560$v_ecc : 1; /* ECC/Parity select (RW) */ unsigned biu_ctl560$v_oe : 1; /* CE pins not asserted during RAM write cycles (RW) */ unsigned biu_ctl560$v_bc_fhit : 1; /* Force Bcache hit (RW) */ unsigned biu_ctl560$v_bc_spd : 2; /* Bcache speed (RW) */ unsigned biu_ctl560$$$_fill_1 : 2; /* */ unsigned biu_ctl560$v_pcache_mode : 1; /* P Cache mode (RW) */ unsigned biu_ctl560$v_qw_io_rd : 1; /* I/O space alignment control (RW) */ unsigned biu_ctl560$v_pv : 1; /* PV mode control (RW) */ unsigned biu_ctl560$$$_fill_2 : 2; unsigned biu_ctl560$v_io_map : 2; /* I/O mapping range (RW) */ unsigned biu_ctl560$$$_fill_3 : 13; unsigned biu_ctl560$v_bc_size : 3; /* Bcache size (RW) */ unsigned biu_ctl560$v_ws_io : 1; /* Workstation IO mapping (RW) */ } pr560r_pr560biu_ctl_bits; /* Cbox registers, continued */ __struct { unsigned diag_ctl560$$$_fill_1 : 6; /* */ unsigned diag_ctl560$v_todr_test : 1; /* Enables TODR test mode (RW) */ unsigned diag_ctl560$v_todr_inc : 1; /* Increment TODR (RW) */ unsigned diag_ctl560$$$_fill_2 : 3; /* */ unsigned diag_ctl560$v_pack_disable : 1; /* Disable write packing (RW) */ unsigned diag_ctl560$v_mab_en : 1; /* MAB enable (RW) */ unsigned diag_ctl560$$$_fill_3 : 2; /* */ unsigned diag_ctl560$v_disable_ecc_err : 1; /* Disable ECC error reporting (RW) */ unsigned diag_ctl560$$$_fill_4 : 5; /* */ unsigned diag_ctl560$v_pm_hit_type : 3; /* Selects Bcache hit type (RW) */ unsigned diag_ctl560$v_pm_access_type : 3; /* Selects Bcache access type (RW) */ unsigned diag_ctl560$v_sw_ecc : 1; /* Enable use of IPR_BEDECC (RW) */ unsigned diag_ctl560$$$_fill_5 : 4; } pr560r_pr560diag_ctl_bits; __struct { unsigned bc_tag560$$$_fill_1 : 11; /* */ unsigned bc_tag560$v_hit : 1; /* Tag match (RO) */ unsigned bc_tag560$v_tagctl_v : 1; /* tag valid bit (RO) */ unsigned bc_tag560$v_tagctl_d : 1; /* tag dirty bit (RO) */ unsigned bc_tag560$v_tagctl_s : 1; /* tag shared bit (RO) */ unsigned bc_tag560$v_tagctl_p : 1; /* tag status parity bit (RO) */ unsigned bc_tag560$v_tag_p : 1; /* tag parity bit (RO) */ unsigned bc_tag560$v_tag : 15; /* tag (RO) */ } pr560r_pr560bc_tag_bits; /* Cbox registers, continued */ __struct { unsigned biu_stat560$v_biu_herr : 1; /* Hard_Error on cACK (WC) */ unsigned biu_stat560$v_biu_serr : 1; /* Soft_Error on cACK (WC) */ unsigned biu_stat560$v_bc_tperr : 1; /* Tag Parity error in tag address RAM (WC) */ unsigned biu_stat560$v_bc_tcperr : 1; /* Tag Parity error in tag control RAM (WC) */ unsigned biu_stat560$v_biu_dsp_cmd : 3; /* Cbox cycle type (RO) */ unsigned biu_stat560$v_biu_seo : 1; /* second BIU or BC error (WC) */ unsigned biu_stat560$v_fill_ecc : 1; /* ECC error on Pcache fill data (WC) */ unsigned biu_stat560$v_fill_crd : 1; /* ECC error was correctable (WC) */ unsigned biu_stat560$v_biu_dperr : 1; /* BIU parity error (WC) */ unsigned biu_stat560$v_fill_ird : 1; /* error during I stream fill (RO) */ unsigned biu_stat560$v_fill_qw : 2; /* Quadword within Pcache FILL hexaword which had a FILL error (RO) */ unsigned biu_stat560$v_fill_seo : 1; /* second FILL error (WC) */ unsigned biu_stat560$v_raz : 1; /* Read as ZERO */ unsigned biu_stat560$v_fill_dsp_cmd : 4; /* Cbox cmd which resulted in FILL error (RO) */ unsigned biu_stat560$v_lst_wrt : 1; /* Lost write error (WC) */ unsigned biu_stat560$v_rsvd : 7; /* reserved bits */ unsigned biu_stat560$v_biu_addr : 2; /* BIU ADDR bits 33:32 (RO) */ unsigned biu_stat560$v_fill_addr : 2; /* FILL ADDR bits 33:32 (RO) */ } pr560r_pr560biu_stat_bits; __struct { unsigned biu_addr560$v_fill_1 : 5; unsigned biu_addr560$v_address : 27; /* Physical error address */ } pr560r_pr560biu_addr_bits; __struct { unsigned fill_syn560$v_lo : 7; /* ECC syndrome bits for low longword */ unsigned fill_syn560$v_hi : 7; /* ECC syndrome bits for high longword */ unsigned fill_syn560$v_fill_1 : 18; } pr560r_pr560fill_syn_bits; /* Cbox registers, continued */ __struct { unsigned fill_addr560$v_fill_1 : 5; unsigned fill_addr560$v_address : 27; /* Physical error address */ } pr560r_pr560fill_addr_bits; __struct { unsigned stc_result560$$$_fill_1 : 2; unsigned stc_result560$v_pass : 1; /* Store Conditional passed */ unsigned stc_result560$$$_fill_2 : 29; } pr560r_pr560stc_result_bits; __struct { unsigned bedecc560$v_lo : 7; /* BEDECC bits for low longword */ unsigned bedecc560$v_hi : 7; /* BEDECC bits for high longword */ unsigned bedecc560$v_fill_1 : 18; } pr560r_pr560bedecc_bits; /* Console dispatch structure */ __struct { unsigned sio560$v_sio_in : 1; /* Serial line/SROM input (RO) */ unsigned sio560$v_sio_out : 1; /* Serial line/SROM clock output (WO) */ unsigned sio560$$$_fill_1 : 30; } pr560r_pr560sio_bits; __struct { unsigned soe560$v_srom_oe : 1; /* SROM output enable (WO) */ unsigned soe560$v_srom_fast : 1; /* Use fast version of SROM (RO) */ unsigned soe560$$$_fill_1 : 18; unsigned soe560$v_wafer_row_col_id : 12; /* Wafer/Row/Col_ID (RO) */ } pr560r_pr560soe_ie_bits; __struct { unsigned vmar560$$$_fill_1 : 2; unsigned vmar560$v_lw : 1; /* longword within quadword (WO) */ unsigned vmar560$v_sub_block : 2; /* sub-block indicator (RW) */ unsigned vmar560$v_row_index : 6; /* cache row index (RW) */ unsigned vmar560$v_addr : 21; /* error address (RO) */ } pr560r_pr560vmar_bits; __struct { unsigned vtag560$v_v : 4; /* data valid bits (RW) */ unsigned vtag560$v_dp : 4; /* data parity bits (RW) */ unsigned vtag560$v_tp : 1; /* tag parity bit (RW) */ unsigned vtag560$$$_fill_1 : 2; /* unused bits (ones) (RW) */ unsigned vtag560$v_tag : 21; /* tag (RW) */ } pr560r_pr560vtag_bits; __struct { unsigned icsr560$v_enable : 1; /* VIC enable bit (RW) */ unsigned icsr560$$$_fill_1 : 1; unsigned icsr560$v_lock : 1; /* Register is locked due to an error (WC) */ unsigned icsr560$v_dperr : 1; /* Data parity error (RO) */ unsigned icsr560$v_tperr : 1; /* Tag parity error (RO) */ unsigned icsr560$$$_fill_2 : 27; } pr560r_pr560icsr_bits; __struct { unsigned bpcr560$v_history : 4; /* branch history bits */ unsigned bpcr560$$$_fill_1 : 1; unsigned bpcr560$v_mispredict : 1; /* history of last branch */ unsigned bpcr560$v_flush_bht : 1; /* flush branch history table */ unsigned bpcr560$v_flush_ctr : 1; /* flush branch hist addr counter */ unsigned bpcr560$v_load_history : 1; /* write new history to array */ unsigned bpcr560$$$_fill_2 : 7; /* unused bits (must be zero) */ unsigned bpcr560$v_bpu_algorithm : 16; /* branch prediction algorithm */ } pr560r_pr560bpcr_bits; /* The following two registers are for testability and diagnostics use only. */ /* They should not be referenced in normal operation. */ /* These registers are for testability and diagnostics use only. */ /* In normal operation, the equivalent architecturally-defined registers */ /* should be used instead. */ __struct { unsigned pamode560$v_mode : 1; /* Addressing mode(1 = 32bit addressing) (RW) */ unsigned pamode560$$$_fill_1 : 31; } pr560r_pr560pamode_bits; __struct { unsigned mmests560$v_lv : 1; /* ACV fault due to length violation */ unsigned mmests560$v_pte_ref : 1; /* ACV/TNV fault occurred on PPTE reference */ unsigned mmests560$v_m : 1; /* Reference had write or modify intent */ unsigned mmests560$$$_fill_1 : 11; unsigned mmests560$v_fault : 2; /* Fault type, one of the following: */ unsigned mmests560$$$_fill_2 : 10; unsigned mmests560$v_src : 3; /* Shadow copy of LOCK bits (see SRC560$ constants below) */ unsigned mmests560$v_lock : 3; /* Lock status (see SRC560$ constant below) */ } pr560r_pr560mmests_bits; __struct { unsigned tbsts560$v_lock : 1; /* Register is locked due to an error (WC) */ unsigned tbsts560$v_dperr : 1; /* Data parity error (RO) */ unsigned tbsts560$v_tperr : 1; /* Tag parity error (RO) */ unsigned tbsts560$v_em_val : 1; /* EM latch was valid when error occurred (RO) */ unsigned tbsts560$v_cmd : 5; /* S5 command when TB parity error occured (RO) */ unsigned tbsts560$$$_fill_1 : 20; unsigned tbsts560$v_src : 3; /* Source of original reference (see SRC560$ constants below) (RO) */ } pr560r_pr560tbsts_bits; /* Constants for reference type used in MMESTS and TBSTS above */ __struct { unsigned pcsts560$v_lock : 1; /* Register is locked due to an error (WC) */ unsigned pcsts560$v_dperr : 1; /* Data parity error occurred (RO) */ unsigned pcsts560$v_right_bank : 1; /* Right bank tag parity error occurred (RO) */ unsigned pcsts560$v_left_bank : 1; /* Left bank tag parity error occurred (RO) */ unsigned pcsts560$v_cmd : 5; /* S6 command when Pcache parity error occured (RO) */ unsigned pcsts560$v_pte_er_wr : 1; /* Hard error on PTE DREAD occurred (orig ref was WRITE) (WC) */ unsigned pcsts560$v_pte_er : 1; /* Hard error on PTE DREAD occurred (WC) */ unsigned pcsts560$$$_fill_1 : 21; } pr560r_pr560pcsts_bits; __struct { unsigned pcctl560$v_d_enable : 1; /* Enable for invalidate, D-stream read/write/fill (RW) */ unsigned pcctl560$v_i_enable : 1; /* Enable for invalidate, I-stream read/fill (RW) */ unsigned pcctl560$v_force_hit : 1; /* Enable force hit on Pcache references (RW) */ unsigned pcctl560$v_bank_sel : 1; /* Select left bank if 0, right bank if 1 (RW) */ unsigned pcctl560$v_p_enable : 1; /* Enable parity checking (RW) */ unsigned pcctl560$v_pmm : 3; /* Mbox performance monitor mode (RW) */ unsigned pcctl560$v_elec_disable : 1; /* Pcache electrical disable bit (RW) */ unsigned pcctl560$v_red_enable : 1; /* Redundancy enable bit (RO) */ unsigned pcctl560$$$_fill_1 : 22; } pr560r_pr560pcctl_bits; /* Constants for NVAX+ Pcache tags IPRs */ __struct { unsigned pctag560$v_a : 1; /* Allocation bit corresponding to index of this tag (RW) */ unsigned pctag560$v_v : 4; /* Valid bits corresponding to the 4 data subblocks (RW) */ unsigned pctag560$v_p : 1; /* Tag parity (RW) */ unsigned pctag560$$$_fill_1 : 6; unsigned pctag560$v_tag : 20; /* Tag bits (RW) */ } pr560r_pr560pctag_bits; __struct { unsigned pctaga560$$$_fill_1 : 5; unsigned pctaga560$v_index : 7; /* Index of PCache tag */ unsigned pctaga560$v_b : 1; /* Bank of PCache to access: 0=left, 1=right */ unsigned pctaga560$v_fill_62 : 3; } pr560r_pr560pctaga_bits; /* Constants for Pcache data parity IPRs */ __struct { unsigned pcdap560$v_data_parity : 8; /* Even byte parity for the addressed quadword (RW) */ unsigned pcdap560$$$_fill_1 : 24; } pr560r_pr560pcdap_bits; } ; #if !defined(__VAXC) && !defined(VAXC) #define iccs560$v_run pr560r_pr560iccs_bits.iccs560$v_run #define iccs560$v_xfr pr560r_pr560iccs_bits.iccs560$v_xfr #define iccs560$v_sgl pr560r_pr560iccs_bits.iccs560$v_sgl #define iccs560$v_ie pr560r_pr560iccs_bits.iccs560$v_ie #define iccs560$v_tint pr560r_pr560iccs_bits.iccs560$v_tint #define iccs560$v_err pr560r_pr560iccs_bits.iccs560$v_err #define savpsl560$v_psl_lo pr560r_pr560savpsl_bits.savpsl560$v_psl_lo #define savpsl560$v_haltcode pr560r_pr560savpsl_bits.savpsl560$v_haltcode #define savpsl560$v_invalid pr560r_pr560savpsl_bits.savpsl560$v_invalid #define savpsl560$v_mapen pr560r_pr560savpsl_bits.savpsl560$v_mapen #define savpsl560$v_psl_hi pr560r_pr560savpsl_bits.savpsl560$v_psl_hi #define intsys560$v_sisr pr560r_pr560intsys_bits.intsys560$v_sisr #define intsys560$v_int_id pr560r_pr560intsys_bits.intsys560$v_int_id #define intsys560$v_int_tim_reset pr560r_pr560intsys_bits.intsys560$v_int_tim_reset #define intsys560$v_s_err_reset pr560r_pr560intsys_bits.intsys560$v_s_err_reset #define intsys560$v_pmon_reset pr560r_pr560intsys_bits.intsys560$v_pmon_reset #define intsys560$v_halt_reset pr560r_pr560intsys_bits.intsys560$v_halt_reset #define pmfcnt560$v_pmctr0 pr560r_pr560pmfcnt_bits.pmfcnt560$v_pmctr0 #define pmfcnt560$v_pmctr1 pr560r_pr560pmfcnt_bits.pmfcnt560$v_pmctr1 #define pcscr560$v_par_port_dis pr560r_pr560pcscr_bits.pcscr560$v_par_port_dis #define pcscr560$v_pcs_enb pr560r_pr560pcscr_bits.pcscr560$v_pcs_enb #define pcscr560$v_pcs_write pr560r_pr560pcscr_bits.pcscr560$v_pcs_write #define pcscr560$v_rwl_shift pr560r_pr560pcscr_bits.pcscr560$v_rwl_shift #define pcscr560$v_data pr560r_pr560pcscr_bits.pcscr560$v_data #define pcscr560$v_nonstandard_patch pr560r_pr560pcscr_bits.pcscr560$v_nonstandard_patch #define pcscr560$v_patch_rev pr560r_pr560pcscr_bits.pcscr560$v_patch_rev #define ecr560$v_vector_present pr560r_pr560ecr_bits.ecr560$v_vector_present #define ecr560$v_fbox_enable pr560r_pr560ecr_bits.ecr560$v_fbox_enable #define ecr560$v_timeout_ext pr560r_pr560ecr_bits.ecr560$v_timeout_ext #define ecr560$v_fbox_st4_bypass_enable pr560r_pr560ecr_bits.ecr560$v_fbox_st4_bypass_enable #define ecr560$v_timeout_occurred pr560r_pr560ecr_bits.ecr560$v_timeout_occurred #define ecr560$v_timeout_test pr560r_pr560ecr_bits.ecr560$v_timeout_test #define ecr560$v_timeout_clock pr560r_pr560ecr_bits.ecr560$v_timeout_clock #define ecr560$v_fbox_test_enable pr560r_pr560ecr_bits.ecr560$v_fbox_test_enable #define ecr560$v_pmf_enable pr560r_pr560ecr_bits.ecr560$v_pmf_enable #define ecr560$v_pmf_mux pr560r_pr560ecr_bits.ecr560$v_pmf_mux #define ecr560$v_pmf_emux pr560r_pr560ecr_bits.ecr560$v_pmf_emux #define ecr560$v_pmf_lfsr pr560r_pr560ecr_bits.ecr560$v_pmf_lfsr #define ecr560$v_pmf_clear pr560r_pr560ecr_bits.ecr560$v_pmf_clear #define biu_ctl560$v_bc_en pr560r_pr560biu_ctl_bits.biu_ctl560$v_bc_en #define biu_ctl560$v_ecc pr560r_pr560biu_ctl_bits.biu_ctl560$v_ecc #define biu_ctl560$v_oe pr560r_pr560biu_ctl_bits.biu_ctl560$v_oe #define biu_ctl560$v_bc_fhit pr560r_pr560biu_ctl_bits.biu_ctl560$v_bc_fhit #define biu_ctl560$v_bc_spd pr560r_pr560biu_ctl_bits.biu_ctl560$v_bc_spd #define biu_ctl560$v_pcache_mode pr560r_pr560biu_ctl_bits.biu_ctl560$v_pcache_mode #define biu_ctl560$v_qw_io_rd pr560r_pr560biu_ctl_bits.biu_ctl560$v_qw_io_rd #define biu_ctl560$v_pv pr560r_pr560biu_ctl_bits.biu_ctl560$v_pv #define biu_ctl560$v_io_map pr560r_pr560biu_ctl_bits.biu_ctl560$v_io_map #define biu_ctl560$v_bc_size pr560r_pr560biu_ctl_bits.biu_ctl560$v_bc_size #define biu_ctl560$v_ws_io pr560r_pr560biu_ctl_bits.biu_ctl560$v_ws_io #define diag_ctl560$v_todr_test pr560r_pr560diag_ctl_bits.diag_ctl560$v_todr_test #define diag_ctl560$v_todr_inc pr560r_pr560diag_ctl_bits.diag_ctl560$v_todr_inc #define diag_ctl560$v_pack_disable pr560r_pr560diag_ctl_bits.diag_ctl560$v_pack_disable #define diag_ctl560$v_mab_en pr560r_pr560diag_ctl_bits.diag_ctl560$v_mab_en #define diag_ctl560$v_disable_ecc_err pr560r_pr560diag_ctl_bits.diag_ctl560$v_disable_ecc_err #define diag_ctl560$v_pm_hit_type pr560r_pr560diag_ctl_bits.diag_ctl560$v_pm_hit_type #define diag_ctl560$v_pm_access_type pr560r_pr560diag_ctl_bits.diag_ctl560$v_pm_access_type #define diag_ctl560$v_sw_ecc pr560r_pr560diag_ctl_bits.diag_ctl560$v_sw_ecc #define bc_tag560$v_hit pr560r_pr560bc_tag_bits.bc_tag560$v_hit #define bc_tag560$v_tagctl_v pr560r_pr560bc_tag_bits.bc_tag560$v_tagctl_v #define bc_tag560$v_tagctl_d pr560r_pr560bc_tag_bits.bc_tag560$v_tagctl_d #define bc_tag560$v_tagctl_s pr560r_pr560bc_tag_bits.bc_tag560$v_tagctl_s #define bc_tag560$v_tagctl_p pr560r_pr560bc_tag_bits.bc_tag560$v_tagctl_p #define bc_tag560$v_tag_p pr560r_pr560bc_tag_bits.bc_tag560$v_tag_p #define bc_tag560$v_tag pr560r_pr560bc_tag_bits.bc_tag560$v_tag #define biu_stat560$v_biu_herr pr560r_pr560biu_stat_bits.biu_stat560$v_biu_herr #define biu_stat560$v_biu_serr pr560r_pr560biu_stat_bits.biu_stat560$v_biu_serr #define biu_stat560$v_bc_tperr pr560r_pr560biu_stat_bits.biu_stat560$v_bc_tperr #define biu_stat560$v_bc_tcperr pr560r_pr560biu_stat_bits.biu_stat560$v_bc_tcperr #define biu_stat560$v_biu_dsp_cmd pr560r_pr560biu_stat_bits.biu_stat560$v_biu_dsp_cmd #define biu_stat560$v_biu_seo pr560r_pr560biu_stat_bits.biu_stat560$v_biu_seo #define biu_stat560$v_fill_ecc pr560r_pr560biu_stat_bits.biu_stat560$v_fill_ecc #define biu_stat560$v_fill_crd pr560r_pr560biu_stat_bits.biu_stat560$v_fill_crd #define biu_stat560$v_biu_dperr pr560r_pr560biu_stat_bits.biu_stat560$v_biu_dperr #define biu_stat560$v_fill_ird pr560r_pr560biu_stat_bits.biu_stat560$v_fill_ird #define biu_stat560$v_fill_qw pr560r_pr560biu_stat_bits.biu_stat560$v_fill_qw #define biu_stat560$v_fill_seo pr560r_pr560biu_stat_bits.biu_stat560$v_fill_seo #define biu_stat560$v_raz pr560r_pr560biu_stat_bits.biu_stat560$v_raz #define biu_stat560$v_fill_dsp_cmd pr560r_pr560biu_stat_bits.biu_stat560$v_fill_dsp_cmd #define biu_stat560$v_lst_wrt pr560r_pr560biu_stat_bits.biu_stat560$v_lst_wrt #define biu_stat560$v_rsvd pr560r_pr560biu_stat_bits.biu_stat560$v_rsvd #define biu_stat560$v_biu_addr pr560r_pr560biu_stat_bits.biu_stat560$v_biu_addr #define biu_stat560$v_fill_addr pr560r_pr560biu_stat_bits.biu_stat560$v_fill_addr #define biu_addr560$v_fill_1 pr560r_pr560biu_addr_bits.biu_addr560$v_fill_1 #define biu_addr560$v_address pr560r_pr560biu_addr_bits.biu_addr560$v_address #define fill_syn560$v_lo pr560r_pr560fill_syn_bits.fill_syn560$v_lo #define fill_syn560$v_hi pr560r_pr560fill_syn_bits.fill_syn560$v_hi #define fill_syn560$v_fill_1 pr560r_pr560fill_syn_bits.fill_syn560$v_fill_1 #define fill_addr560$v_fill_1 pr560r_pr560fill_addr_bits.fill_addr560$v_fill_1 #define fill_addr560$v_address pr560r_pr560fill_addr_bits.fill_addr560$v_address #define stc_result560$v_pass pr560r_pr560stc_result_bits.stc_result560$v_pass #define bedecc560$v_lo pr560r_pr560bedecc_bits.bedecc560$v_lo #define bedecc560$v_hi pr560r_pr560bedecc_bits.bedecc560$v_hi #define bedecc560$v_fill_1 pr560r_pr560bedecc_bits.bedecc560$v_fill_1 #define sio560$v_sio_in pr560r_pr560sio_bits.sio560$v_sio_in #define sio560$v_sio_out pr560r_pr560sio_bits.sio560$v_sio_out #define soe560$v_srom_oe pr560r_pr560soe_ie_bits.soe560$v_srom_oe #define soe560$v_srom_fast pr560r_pr560soe_ie_bits.soe560$v_srom_fast #define soe560$v_wafer_row_col_id pr560r_pr560soe_ie_bits.soe560$v_wafer_row_col_id #define vmar560$v_lw pr560r_pr560vmar_bits.vmar560$v_lw #define vmar560$v_sub_block pr560r_pr560vmar_bits.vmar560$v_sub_block #define vmar560$v_row_index pr560r_pr560vmar_bits.vmar560$v_row_index #define vmar560$v_addr pr560r_pr560vmar_bits.vmar560$v_addr #define vtag560$v_v pr560r_pr560vtag_bits.vtag560$v_v #define vtag560$v_dp pr560r_pr560vtag_bits.vtag560$v_dp #define vtag560$v_tp pr560r_pr560vtag_bits.vtag560$v_tp #define vtag560$v_tag pr560r_pr560vtag_bits.vtag560$v_tag #define icsr560$v_enable pr560r_pr560icsr_bits.icsr560$v_enable #define icsr560$v_lock pr560r_pr560icsr_bits.icsr560$v_lock #define icsr560$v_dperr pr560r_pr560icsr_bits.icsr560$v_dperr #define icsr560$v_tperr pr560r_pr560icsr_bits.icsr560$v_tperr #define bpcr560$v_history pr560r_pr560bpcr_bits.bpcr560$v_history #define bpcr560$v_mispredict pr560r_pr560bpcr_bits.bpcr560$v_mispredict #define bpcr560$v_flush_bht pr560r_pr560bpcr_bits.bpcr560$v_flush_bht #define bpcr560$v_flush_ctr pr560r_pr560bpcr_bits.bpcr560$v_flush_ctr #define bpcr560$v_load_history pr560r_pr560bpcr_bits.bpcr560$v_load_history #define bpcr560$v_bpu_algorithm pr560r_pr560bpcr_bits.bpcr560$v_bpu_algorithm #define pamode560$v_mode pr560r_pr560pamode_bits.pamode560$v_mode #define mmests560$v_lv pr560r_pr560mmests_bits.mmests560$v_lv #define mmests560$v_pte_ref pr560r_pr560mmests_bits.mmests560$v_pte_ref #define mmests560$v_m pr560r_pr560mmests_bits.mmests560$v_m #define mmests560$v_fault pr560r_pr560mmests_bits.mmests560$v_fault #define mmests560$v_src pr560r_pr560mmests_bits.mmests560$v_src #define mmests560$v_lock pr560r_pr560mmests_bits.mmests560$v_lock #define tbsts560$v_lock pr560r_pr560tbsts_bits.tbsts560$v_lock #define tbsts560$v_dperr pr560r_pr560tbsts_bits.tbsts560$v_dperr #define tbsts560$v_tperr pr560r_pr560tbsts_bits.tbsts560$v_tperr #define tbsts560$v_em_val pr560r_pr560tbsts_bits.tbsts560$v_em_val #define tbsts560$v_cmd pr560r_pr560tbsts_bits.tbsts560$v_cmd #define tbsts560$v_src pr560r_pr560tbsts_bits.tbsts560$v_src #define pcsts560$v_lock pr560r_pr560pcsts_bits.pcsts560$v_lock #define pcsts560$v_dperr pr560r_pr560pcsts_bits.pcsts560$v_dperr #define pcsts560$v_right_bank pr560r_pr560pcsts_bits.pcsts560$v_right_bank #define pcsts560$v_left_bank pr560r_pr560pcsts_bits.pcsts560$v_left_bank #define pcsts560$v_cmd pr560r_pr560pcsts_bits.pcsts560$v_cmd #define pcsts560$v_pte_er_wr pr560r_pr560pcsts_bits.pcsts560$v_pte_er_wr #define pcsts560$v_pte_er pr560r_pr560pcsts_bits.pcsts560$v_pte_er #define pcctl560$v_d_enable pr560r_pr560pcctl_bits.pcctl560$v_d_enable #define pcctl560$v_i_enable pr560r_pr560pcctl_bits.pcctl560$v_i_enable #define pcctl560$v_force_hit pr560r_pr560pcctl_bits.pcctl560$v_force_hit #define pcctl560$v_bank_sel pr560r_pr560pcctl_bits.pcctl560$v_bank_sel #define pcctl560$v_p_enable pr560r_pr560pcctl_bits.pcctl560$v_p_enable #define pcctl560$v_pmm pr560r_pr560pcctl_bits.pcctl560$v_pmm #define pcctl560$v_elec_disable pr560r_pr560pcctl_bits.pcctl560$v_elec_disable #define pcctl560$v_red_enable pr560r_pr560pcctl_bits.pcctl560$v_red_enable #define pctag560$v_a pr560r_pr560pctag_bits.pctag560$v_a #define pctag560$v_v pr560r_pr560pctag_bits.pctag560$v_v #define pctag560$v_p pr560r_pr560pctag_bits.pctag560$v_p #define pctag560$v_tag pr560r_pr560pctag_bits.pctag560$v_tag #define pctaga560$v_index pr560r_pr560pctaga_bits.pctaga560$v_index #define pctaga560$v_b pr560r_pr560pctaga_bits.pctaga560$v_b #define pcdap560$v_data_parity pr560r_pr560pcdap_bits.pcdap560$v_data_parity #endif /* #if !defined(__VAXC) && !defined(VAXC) */ #endif /* __PR560DEF_LOADED */ #ifdef __cplusplus } #endif #pragma standard #endif /* __PR560DEF_LOADED */