/********************************************************************************************************************************/ /* Created: 15-MAR-2001 23:38:09 by OpenVMS SDL EV1-33 */ /* Source: 15-MAR-2001 23:34:16 _$11$DUA933:[BUILD.SDL]STARDEFMP.SDI;1 */ /********************************************************************************************************************************/ /*** MODULE $PR1701DEF ***/ #ifndef __PR1701DEF_LOADED #define __PR1701DEF_LOADED 1 #pragma nostandard #ifdef __cplusplus extern "C" { #define __unknown_params ... #else #define __unknown_params #endif #if !defined(__VAXC) && !defined(VAXC) #define __struct struct #define __union union #else #define __struct variant_struct #define __union variant_union #endif #define PR1701$K_REVISION 1 /* Revision number of this file */ /* In the definitions below, registers are annotated with one of the following */ /* symbols: */ /* */ /* RW - The register may be read and written */ /* RO - The register may only be read */ /* WO - The register may only be written */ /* */ /* For RO and WO registers, all bits and fields within the register are also */ /* read-only or write-only. For RW registers, each bit or field within */ /* the register is annotated with one of the following: */ /* */ /* RW - The bit/field may be read and written */ /* RO - The bit/field may be read; writes are ignored */ /* WO - The bit/field may be written; reads return an UNPREDICTABLE result. */ /* WZ - The bit/field may be written; reads return a 0 */ /* WC - The bit/field may be read; writes cause state to clear */ /* RC - The bit/field may be read, which also causes state to clear; writes are ignored */ #define PR1701$_IPL 18 /* Interrupt Priority Level */ #define PR1701$_ICCS 24 /* Interval Clock Control/Status */ #define PR1701$_NICR 25 /* Next Interval Count */ #define PR1701$_ICR 26 /* Interval Count */ #define PR1701$_TODR 27 /* Time Of Year Register (RW) */ #define PR1701$_MCESR 38 /* Machine check error register (WO) */ #define PR1701$_SAVPC 42 /* Console saved PC (RO) */ #define PR1701$_SAVPSL 43 /* Console saved PSL (RO) */ #define PR17_SAVPSL$M_PSL_LO 0xFF #define PR17_SAVPSL$M_HALTCODE 0x3F00 #define PR17_SAVPSL$K_HALT_HLTPIN 2 /* HALT_L pin asserted */ #define PR17_SAVPSL$K_HALT_PWRUP 3 /* Initial powerup */ #define PR17_SAVPSL$K_HALT_INTSTK 4 /* Interrupt stack not valid */ #define PR17_SAVPSL$K_HALT_DOUBLE 5 /* Machine check during exception processing */ #define PR17_SAVPSL$K_HALT_HLTINS 6 /* Halt instruction in kernel mode */ #define PR17_SAVPSL$K_HALT_ILLVEC 7 /* Illegal SCB vector (bits<1:0>=11) */ #define PR17_SAVPSL$K_HALT_WCSVEC 8 /* WCS SCB vector (bits<1:0>=10) */ #define PR17_SAVPSL$K_HALT_CHMFI 10 /* CHMx on interrupt stack */ #define PR17_SAVPSL$K_HALT_IE0 16 /* ACV/TNV during machine check processing */ #define PR17_SAVPSL$K_HALT_IE1 17 /* ACV/TNV during KSNV processing */ #define PR17_SAVPSL$K_HALT_IE2 18 /* Machine check during machine check processing */ #define PR17_SAVPSL$K_HALT_IE3 19 /* Machine check during KSNV processing */ #define PR17_SAVPSL$K_HALT_IE_PSL_101 25 /* PSL<26:24>=101 during interrupt or exception */ #define PR17_SAVPSL$K_HALT_IE_PSL_110 26 /* PSL<26:24>=110 during interrupt or exception */ #define PR17_SAVPSL$K_HALT_IE_PSL_111 27 /* PSL<26:24>=111 during interrupt or exception */ #define PR17_SAVPSL$K_HALT_REI_PSL_101 29 /* PSL<26:24>=101 during REI */ #define PR17_SAVPSL$K_HALT_REI_PSL_110 30 /* PSL<26:24>=110 during REI */ #define PR17_SAVPSL$K_HALT_REI_PSL_111 31 /* PSL<26:24>=111 during REI */ #define PR17_SAVPSL$M_INVALID 0x4000 #define PR17_SAVPSL$M_MAPEN 0x8000 #define PR17_SAVPSL$M_PSL_HI 0xFFFF0000 #define PR1701$_IORESET 55 /* I/O system reset register (WO) */ #define PR1701$_PME 61 /* Performance monitoring enable (RW) */ /* System-level required registers. */ #define PR1701$_IAK14 64 /* Level 14 interrupt acknowledge (RO) */ #define PR1701$_IAK15 65 /* Level 15 interrupt acknowledge (RO) */ #define PR1701$_IAK16 66 /* Level 16 interrupt acknowledge (RO) */ #define PR1701$_IAK17 67 /* Level 17 interrupt acknowledge (RO) */ #define IAK$M_IPL17 0x1 #define IAK$M_PR 0x2 #define IAK$M_SCB_OFFSET 0xFFFC #define PR1701$_CWB 68 /* Clear write buffers (RW) */ #define PR1701$_LMBOX 121 /* Laser Mailbox */ /* Ebox registers. */ #define PR1701$_INTSYS 122 /* Interrupt system status register (RW) */ #define INTSYS$M_ICCS6 0x1 #define INTSYS$M_SISR 0xFFFE #define INTSYS$M_INT_ID 0x1F0000 #define INTSYS$K_INT_ID_HALT 31 /* Halt pin */ #define INTSYS$K_INT_ID_PWRFL 30 /* Power fail */ #define INTSYS$K_INT_ID_H_ERR 29 /* Hard error */ #define INTSYS$K_INT_ID_INT_TIM 28 /* Interval timer */ #define INTSYS$K_INT_ID_PMON 27 /* Performance monitor */ #define INTSYS$K_INT_ID_S_ERR 26 /* Soft error */ #define INTSYS$K_INT_ID_IRQ3 23 /* IPL 17 device interrupt */ #define INTSYS$K_INT_ID_IRQ2 22 /* IPL 16 device interrupt */ #define INTSYS$K_INT_ID_IRQ1 21 /* IPL 15 device interrupt */ #define INTSYS$K_INT_ID_IRQ0 20 /* IPL 14 device interrupt */ #define INTSYS$K_INT_ID_SISR15 15 /* SISR<15> */ #define INTSYS$K_INT_ID_SISR14 14 /* SISR<14> */ #define INTSYS$K_INT_ID_SISR13 13 /* SISR<13> */ #define INTSYS$K_INT_ID_SISR12 12 /* SISR<12> */ #define INTSYS$K_INT_ID_SISR11 11 /* SISR<11> */ #define INTSYS$K_INT_ID_SISR10 10 /* SISR<10> */ #define INTSYS$K_INT_ID_SISR9 9 /* SISR<9> */ #define INTSYS$K_INT_ID_SISR8 8 /* SISR<8> */ #define INTSYS$K_INT_ID_SISR7 7 /* SISR<7> */ #define INTSYS$K_INT_ID_SISR6 6 /* SISR<6> */ #define INTSYS$K_INT_ID_SISR5 5 /* SISR<5> */ #define INTSYS$K_INT_ID_SISR4 4 /* SISR<4> */ #define INTSYS$K_INT_ID_SISR3 3 /* SISR<3> */ #define INTSYS$K_INT_ID_SISR2 2 /* SISR<2> */ #define INTSYS$K_INT_ID_SISR1 1 /* SISR<1> */ #define INTSYS$K_INT_ID_NO_INT 0 /* No interrupt */ #define INTSYS$M_INT_TIM_RESET 0x1000000 #define INTSYS$M_S_ERR_RESET 0x8000000 #define INTSYS$M_PMON_RESET 0x10000000 #define INTSYS$M_H_ERR_RESET 0x20000000 #define INTSYS$M_PWRFL_RESET 0x40000000 #define INTSYS$M_HALT_RESET 0x80000000 #define PR1701$_PMFCNT 123 /* Performance monitoring facility count register (RW) */ #define PMFCNT$M_PMCTR0 0xFFFF #define PMFCNT$M_PMCTR1 0xFFFF0000 #define PR1701$_PCSCR 124 /* Patchable control store control register (WO) */ #define PCSCR$M_PAR_PORT_DIS 0x100 #define PCSCR$M_PCS_ENB 0x200 #define PCSCR$M_PCS_WRITE 0x400 #define PCSCR$M_RWL_SHIFT 0x800 #define PCSCR$M_DATA 0x1000 #define PCSCR$M_NONSTANDARD_PATCH 0x800000 #define PCSCR$M_PATCH_REV 0x1F000000 #define PR1701$_ECR 125 /* Ebox control register (RW) */ #define ECR$M_VECTOR_PRESENT 0x1 #define ECR$M_FBOX_ENABLE 0x2 #define ECR$M_TIMEOUT_EXT 0x4 #define ECR$M_FBOX_ST4_BYPASS_ENABLE 0x8 #define ECR$M_TIMEOUT_OCCURRED 0x10 #define ECR$M_TIMEOUT_TEST 0x20 #define ECR$M_TIMEOUT_CLOCK 0x40 #define ECR$M_FBOX_TEST_ENABLE 0x2000 #define ECR$M_PMF_ENABLE 0x10000 #define ECR$M_PMF_PMUX 0x60000 #define ECR$K_PMUX_IBOX 0 /* Select Ibox */ #define ECR$K_PMUX_EBOX 1 /* Select Ebox */ #define ECR$K_PMUX_MBOX 2 /* Select Mbox */ #define ECR$K_PMUX_CBOX 3 /* Select Cbox */ #define ECR$M_PMF_EMUX 0x380000 #define ECR$K_EMUX_S3_STALL 0 /* Measure S3 stall against total cycles */ #define ECR$K_EMUX_EM_PA_STALL 1 /* Measure EM+PA queue stall against total cycles */ #define ECR$K_EMUX_CPI 2 /* Measure instructions retired against total cycles */ #define ECR$K_EMUX_STALL 3 /* Measure total stalls against total cycles */ #define ECR$K_EMUX_S3_STALL_PCT 4 /* Measure S3 stall against total stalls */ #define ECR$K_EMUX_EM_PA_STALL_PCT 5 /* Measure EM+PA queue stall against total stalls */ #define ECR$K_EMUX_UWORD 7 /* Count microword increments */ #define ECR$M_PMF_LFSR 0x400000 #define ECR$M_PMF_CLEAR 0x80000000 #define PR1701$_MTBTAG 126 /* Mbox TB tag fill (WO) */ #define MTBTAG$M_TP 0x1 #define MTBTAG$M_VPN 0xFFFFFE00 #define PR1701$_MTBPTE 127 /* Mbox TB PTE fill (WO) */ #define MTBPTE$M_PFN 0x7FFFFF #define MTBPTE$M_P 0x1000000 #define MTBPTE$M_M 0x4000000 #define MTBPTE$M_PROT 0x18000000 #define MTBPTE$M_V 0x20000000 #define PR1701$_VPSR 144 /* Vector processor status register (RW) */ #define PR17_VPSR$M_VEN 0x1 #define PR17_VPSR$M_RST 0x2 #define PR17_VPSR$M_AEX 0x80 #define PR17_VPSR$M_IMP 0x1000000 #define PR17_VPSR$M_BSY 0x80000000 #define PR1701$_VAER 145 /* Vector arithmetic exception register (RO) */ #define PR17_VAER$M_F_UNDF 0x1 #define PR17_VAER$M_F_DIVZ 0x2 #define PR17_VAER$M_F_ROPR 0x4 #define PR17_VAER$M_F_OVFL 0x8 #define PR17_VAER$M_I_OVFL 0x20 #define PR17_VAER$M_REGISTER_MASK 0xFFFF0000 #define PR1701$_VMAC 146 /* Vector memory activity register (RO) */ #define PR1701$_VTBIA 147 /* Vector translation buffer invalidate all (WO) */ /* Cbox registers. */ #define PR1701$_BIU_CTL 160 /* Cbox control register (RW) */ #define BIU_CTL$M_BC_EN 0x1 #define BIU_CTL$M_ECC 0x2 #define BIU_CTL$K_ECC_ECC 1 /* select ECC mode */ #define BIU_CTL$K_ECC_PARITY 0 /* select Parity mode */ #define BIU_CTL$M_OE 0x4 #define BIU_CTL$M_BC_FHIT 0x8 #define BIU_CTL$M_BC_SPD 0xF0 #define BIU_CTL$K_BC_SPD_2X 0 /* 2x cpu cycle */ #define BIU_CTL$K_BC_SPD_3X 1 /* 3x cpu cycle */ #define BIU_CTL$K_BC_SPD_4X 2 /* 4x cpu cycle */ #define BIU_CTL$M_BC_SIZE 0x70000000 #define BIU_CTL$K_BC_SIZE_128KB 0 /* Select 128KB Bcache */ #define BIU_CTL$K_BC_SIZE_256KB 1 /* Select 256KB Bcache */ #define BIU_CTL$K_BC_SIZE_512KB 2 /* Select 512KB Bcache */ #define BIU_CTL$K_BC_SIZE_1MB 3 /* Select 1MB Bcache */ #define BIU_CTL$K_BC_SIZE_2MB 4 /* Select 2MB Bcache */ #define BIU_CTL$K_BC_SIZE_4MB 5 /* Select 4MB Bcache */ #define BIU_CTL$K_BC_SIZE_8MB 6 /* Select 8MB Bcache */ #define BIU_CTL$M_WS_IO 0x80000000 #define PR1701$_BC_TAG 162 /* Bcache error tag (RO) */ #define BC_TAG$M_HIT 0x1 #define BC_TAG$M_CTL_P 0x2 #define BC_TAG$M_CTL_S 0x4 #define BC_TAG$M_CTL_D 0x8 #define BC_TAG$M_CTL_V 0x10 #define BC_TAG$M_TAG_P 0x400000 #define PR1701$_BIU_STAT 164 /* Bcache error data status (W1C) */ #define BIU_STAT$M_BIU_HERR 0x1 #define BIU_STAT$M_BIU_SERR 0x2 #define BIU_STAT$M_BC_TPERR 0x4 #define BIU_STAT$M_BC_TCPERR 0x8 #define BIU_STAT$M_BIU_DSP_CMD 0x70 #define BIU_STAT$K_WRITE_UNLOCK_IO 0 /* WRITE_UNLOCK_IO cmd */ #define BIU_STAT$K_IREAD 1 /* IREAD cmd */ #define BIU_STAT$K_WRITE_UNLOCK 2 /* WRITE_UNLOCK cmd */ #define BIU_STAT$K_WRITE 3 /* WRITE cmd */ #define BIU_STAT$K_DREAD 4 /* DREAD cmd */ #define BIU_STAT$K_DREAD_IO 5 /* DREAD_IO cmd */ #define BIU_STAT$K_DREAD_LOCK 6 /* DREAD_LOCK cmd */ #define BIU_STAT$M_BIU_SEO 0x80 #define BIU_STAT$M_FILL_ECC 0x100 #define BIU_STAT$M_FILL_CRD 0x200 #define BIU_STAT$M_BIU_DPERR 0x400 #define BIU_STAT$M_FILL_IRD 0x800 #define BIU_STAT$M_FILL_SEO 0x4000 #define BIU_STAT$M_RAZ 0x8000 #define BIU_STAT$M_FILL_DSP_CMD 0xF0000 #define BIU_STAT$K_F_IREAD 2 /* IREAD cmd */ #define BIU_STAT$K_IREAD_IO 3 /* IREAD_IO cmd */ #define BIU_STAT$K_F_WRITE_UNLOCK_IO 4 /* WRITE_UNLOCK_IO cmd */ #define BIU_STAT$K_WRITE_IO 5 /* WRITE_IO cmd */ #define BIU_STAT$K_F_WRITE 6 /* WRITE cmd */ #define BIU_STAT$K_F_WRITE_UNLOCK 7 /* WRITE_UNLOCK cmd */ #define BIU_STAT$K_F_DREAD 8 /* DREAD cmd 100X */ #define BIU_STAT$K_F_DREAD2 9 /* DREAD cmd 100X */ #define BIU_STAT$K_F_DREAD_IO 10 /* DREAD_IO cmd */ #define BIU_STAT$K_F_DREAD_LOCK 12 /* DREAD_LOCK cmd */ #define BIU_STAT$K_DREAD_LOCK_IO 13 /* DREAD_LOCK_IO cmd */ #define BIU_STAT$M_LST_WRT 0x100000 #define BIU_STAT$M_RSVD 0xFE00000 #define BIU_STAT$M_BIU_ADDR 0x30000000 #define BIU_STAT$M_FILL_ADDR 0xC0000000 #define PR1701$_BIU_ADDR 166 /* error address associated with BIU errors (RO) */ #define PR1701$_FILL_SYN 168 /* Syndrome bits associated with bad quadword during fill (RO) */ #define PR1701$_FILL_ADDR 170 /* error address associated with FILL errors (RO) */ #define PR1701$_STC_RESULT 172 /* Result of last store conditional (RO) */ #define STC_RESULT$M_PASS 0x4 #define PR1701$_BEDECC 174 /* Alternate source of ECC check bits (W) */ #define PR1701$_CHALT 176 /* Console HALT register (RW) */ #define PR1701$_SIO 178 /* Seral line I/O register (RW) */ #define SIO$M_SIO_IN 0x1 #define SIO$M_SIO_OUT 0x2 #define PR1701$_SIO_IE 180 /* Seral line I/O register (RW) */ #define SIO$M_SROM_OE 0x1 #define SIO$M_SROM_FAST 0x2 #define PR1701$_QW_PACK 184 /* Pack next two longword writes (WO) */ #define PR1701$_CLR_IO_PACK 185 /* Clear QW IO Pack (W) */ /* Ibox registers. */ #define PR1701$_VMAR 208 /* VIC memory address register */ #define VMAR$M_LW 0x4 #define VMAR$M_SUB_BLOCK 0x18 #define VMAR$M_ROW_INDEX 0x7E0 #define VMAR$M_ADDR 0xFFFFF800 #define PR1701$_VTAG 209 /* VIC tag register */ #define VTAG$M_V 0xF #define VTAG$M_DP 0xF0 #define VTAG$M_TP 0x100 #define VTAG$M_TAG 0xFFFFF800 #define PR1701$_VDATA 210 /* VIC data register */ #define PR1701$_ICSR 211 /* Ibox control and status register (RW) */ #define ICSR$M_ENABLE 0x1 #define ICSR$M_LOCK 0x4 #define ICSR$M_DPERR 0x8 #define ICSR$M_TPERR 0x10 #define PR1701$_BPCR 212 /* Ibox branch prediction control register */ #define BPCR$M_HISTORY 0xF #define BPCR$M_MISPREDICT 0x20 #define BPCR$M_FLUSH_BHT 0x40 #define BPCR$M_FLUSH_CTR 0x80 #define BPCR$M_LOAD_HISTORY 0x100 #define BPCR$M_BPU_ALGORITHM 0xFFFF0000 #define BPCR$K_BPU_ALGORITHM 65226 /* default value for BPU_ALGORITHM field */ #define PR1701$_BPC 214 /* Ibox Backup PC (RO) */ #define PR1701$_BPCUNW 215 /* Ibox Backup PC with RLOG unwind (RO) */ /* Mbox internal memory management registers. */ #define PR1701$_MP0BR 224 /* Mbox P0 base register (RW) */ #define PR1701$_MP0LR 225 /* Mbox P0 length register (RW) */ #define PR1701$_MP1BR 226 /* Mbox P1 base register (RW) */ #define PR1701$_MP1LR 227 /* Mbox P1 length register (RW) */ #define PR1701$_MSBR 228 /* Mbox system base register (RW) */ #define PR1701$_MSLR 229 /* Mbox system length register (RW) */ #define PR1701$_MMAPEN 230 /* Mbox memory management enable (RW) */ /* Mbox registers. */ #define PR1701$_PAMODE 231 /* Mbox physical address mode (RW) */ #define PR1701_PAMODE$M_MODE 0x1 #define PR1701_PAMODE$K_PA_30 0 /* 30-bit PA mode */ #define PR1701_PAMODE$K_PA_32 1 /* 32-bit PA mode */ #define PR1701$_MMEADR 232 /* Mbox memory management fault address (RO) */ #define PR1701$_MMEPTE 233 /* Mbox memory management fault PTE address (RO) */ #define PR1701$_MMESTS 234 /* Mbox memory management fault status (RO) */ #define MMESTS$M_LV 0x1 #define MMESTS$M_PTE_REF 0x2 #define MMESTS$M_M 0x4 #define MMESTS$M_FAULT 0xC000 #define MMESTS$K_FAULT_ACV 1 /* ACV fault */ #define MMESTS$K_FAULT_TNV 2 /* TNV fault */ #define MMESTS$K_FAULT_M0 3 /* M=0 fault */ #define MMESTS$M_SRC 0x1C000000 #define MMESTS$M_LOCK 0xE0000000 #define PR1701$_TBADR 236 /* Mbox TB parity error address (RO) */ #define PR1701$_TBSTS 237 /* Mbox TB parity error status (RW) */ #define TBSTS$M_LOCK 0x1 #define TBSTS$M_DPERR 0x2 #define TBSTS$M_TPERR 0x4 #define TBSTS$M_EM_VAL 0x8 #define TBSTS$M_CMD 0x1F0 #define TBSTS$M_SRC 0xE0000000 #define MSRC$K_IREF_LATCH 6 /* Source of fault was IREF latch */ #define MSRC$K_SPEC_QUEUE 4 /* Source of fault was spec queue */ #define MSRC$K_EM_LATCH 0 /* Source of fault was EM latch */ /* Mbox Pcache registers */ #define PR1701$_PCADR 242 /* Mbox Pcache parity error address (RO) */ #define PR1701$_PCSTS 244 /* Mbox Pcache parity error status (RW) */ #define PCSTS$M_LOCK 0x1 #define PCSTS$M_DPERR 0x2 #define PCSTS$M_RIGHT_BANK 0x4 #define PCSTS$M_LEFT_BANK 0x8 #define PCSTS$M_CMD 0x1F0 #define PCSTS$M_PTE_ER_WR 0x200 #define PCSTS$M_PTE_ER 0x400 #define PR1701$_PCCTL 248 /* Mbox Pcache control (RW) */ #define PCCTL$M_D_ENABLE 0x1 #define PCCTL$M_I_ENABLE 0x2 #define PCCTL$M_FORCE_HIT 0x4 #define PCCTL$M_BANK_SEL 0x8 #define PCCTL$M_P_ENABLE 0x10 #define PCCTL$M_PMM 0xE0 #define PCCTL$M_ELEC_DISABLE 0x100 #define PCCTL$M_RED_ENABLE 0x200 #define PR1701$_PCTAG 25165824 /* First of 256 Pcache tag IPRs (RW) */ #define PR1701$_PCTAG_MAX 25173984 /* Last of 256 Pcache tag IPRs */ #define PCTAG$K_IPR_INCR 32 /* Increment between Pcache tag IPR numbers */ #define PR17_PCTAG$M_A 0x1 #define PR17_PCTAG$M_V 0x1E #define PR17_PCTAG$M_P 0x20 #define PR17_PCTAG$M_TAG 0x1FFF000 #define PCTAGA$M_INDEX 0xFE0 #define PCTAGA$M_B 0x1000 #define PR1701$_PCDAP 29360128 /* First of 1024 Pcache data parity IPRs (RW) */ #define PR1701$_PCDAP_MAX 29368312 /* Last of 1024 Pcache data parity IPRs */ #define PCDAP$K_IPR_INCR 8 /* Increment between Pcache data parity IPR numbers */ #define PCDAP$M_DATA_PARITY 0xFF union pr1701def { /* Architecturally-defined registers which have different characteristics */ /* on this CPU. */ __struct { unsigned pr17_savpsl$v_psl_lo : 8; /* Saved PSL bits <7:0> */ unsigned pr17_savpsl$v_haltcode : 6; /* Halt code containing one of the following values */ unsigned pr17_savpsl$v_invalid : 1; /* Invalid SAVPSL if = 1 */ unsigned pr17_savpsl$v_mapen : 1; /* MAPEN<0> */ unsigned pr17_savpsl$v_psl_hi : 16; /* Saved PSL bits <31:16> */ } pr1701r_pr1701savpsl_bits; /* These registers are for testability and diagnostics use only. */ /* They should not be referenced in normal operation. */ __struct { /* Vector returned in response to IAK1x read */ unsigned iak$v_ipl17 : 1; /* Force IPL 17, independent of actual level */ unsigned iak$v_pr : 1; /* Passive release */ unsigned iak$v_scb_offset : 14; /* LW offset in SCB of interrupt vector */ unsigned iak$$$_fill_1 : 16; } pr1701r_pr1701iak_vector; /* Ebox register definition */ __struct { unsigned intsys$v_iccs6 : 1; /* ICCS<6> (RO) */ unsigned intsys$v_sisr : 15; /* SISR<15:1> (RO) */ unsigned intsys$v_int_id : 5; /* ID of highest pending interrupt (RO) */ unsigned intsys$$$_fill_1 : 3; unsigned intsys$v_int_tim_reset : 1; /* Interval timer interrupt reset (WC) */ unsigned intsys$$$_fill_2 : 2; unsigned intsys$v_s_err_reset : 1; /* Soft error interrupt reset (WC) */ unsigned intsys$v_pmon_reset : 1; /* Performance monitoring interrupt reset (WC) */ unsigned intsys$v_h_err_reset : 1; /* Hard error interrupt reset (WC) */ unsigned intsys$v_pwrfl_reset : 1; /* Power fail interrupt reset (WC) */ unsigned intsys$v_halt_reset : 1; /* Halt pin interrupt reset (WC) */ } pr1701r_pr1701intsys_bits; __struct { unsigned pmfcnt$v_pmctr0 : 16; /* PMCTR0 word */ unsigned pmfcnt$v_pmctr1 : 16; /* PMCTR1 word */ } pr1701r_pr1701pmfcnt_bits; __struct { unsigned pcscr$$$_fill_1 : 8; unsigned pcscr$v_par_port_dis : 1; /* Disable parallel port control of scan chain */ unsigned pcscr$v_pcs_enb : 1; /* Enable use of patchable control store */ unsigned pcscr$v_pcs_write : 1; /* Write scan chain to patchable control store */ unsigned pcscr$v_rwl_shift : 1; /* Shift read-write latch scan chain by one bit */ unsigned pcscr$v_data : 1; /* Data to be shifted into the PCS scan chain */ unsigned pcscr$$$_fill_2 : 10; unsigned pcscr$v_nonstandard_patch : 1; /* Non-standard patch bit */ unsigned pcscr$v_patch_rev : 5; /* Patch revision number */ unsigned pcscr$$$_fill_3 : 3; } pr1701r_pr1701pcscr_bits; __struct { unsigned ecr$v_vector_present : 1; /* Vector unit present (RW) */ unsigned ecr$v_fbox_enable : 1; /* Fbox enabled (RW) */ unsigned ecr$v_timeout_ext : 1; /* Select external timebase for S3 stall timeout timer (RW) */ unsigned ecr$v_fbox_st4_bypass_enable : 1; /* Fbox stage 4 conditional bypass enable (RW) */ unsigned ecr$v_timeout_occurred : 1; /* S3 stall timeout occurred (WC) */ unsigned ecr$v_timeout_test : 1; /* Select test mode for S3 stall timeout (RW) */ unsigned ecr$v_timeout_clock : 1; /* Clock S3 timeout (RW) */ unsigned ecr$$$_fill_4 : 1; /* eliminate -ICCS in external logic- bit */ unsigned ecr$$$_fill_1 : 5; unsigned ecr$v_fbox_test_enable : 1; /* Enable test of Fbox (RW) */ unsigned ecr$$$_fill_2 : 2; unsigned ecr$v_pmf_enable : 1; /* Performance monitoring facility enable (RW) */ unsigned ecr$v_pmf_pmux : 2; /* Performance monitoring facility master select (RW) */ unsigned ecr$v_pmf_emux : 3; /* Performance monitoring facility Ebox mux select (RW) */ unsigned ecr$v_pmf_lfsr : 1; /* Performance monitoring facility Wbus LFSR enable (RW) */ unsigned ecr$$$_fill_3 : 8; unsigned ecr$v_pmf_clear : 1; /* Clear performance monitoring hardware counters (WO) */ } pr1701r_pr1701ecr_bits; /* Mbox TB registers. */ /* These registers are for testability and diagnostics use only. */ /* They should not be referenced in normal operation. */ __struct { unsigned mtbtag$v_tp : 1; /* Tag parity bit */ unsigned mtbtag$$$_fill_1 : 8; unsigned mtbtag$v_vpn : 23; /* Virtual page number of address (VA<31:9>) */ } pr1701r_pr1701mtbtag_bits; __struct { /* Format is normal PTE format, except for PTE parity bit */ unsigned mtbpte$v_pfn : 23; /* Page frame number (PA<31:9>) */ unsigned mtbpte$$$_fill_1 : 1; unsigned mtbpte$v_p : 1; /* PTE parity */ unsigned mtbpte$$$_fill_2 : 1; unsigned mtbpte$v_m : 1; /* Modify bit */ unsigned mtbpte$v_prot : 2; /* Protection field */ unsigned mtbpte$v_v : 1; /* PTE valid bit */ unsigned mtbpte$v_fill_104 : 2; } pr1701r_pr1701mtbpte_bits; /* Vector architecture registers */ __struct { unsigned pr17_vpsr$v_ven : 1; /* Vector processor enabled (RW) */ unsigned pr17_vpsr$v_rst : 1; /* Vector processor state reset (WO) */ unsigned pr17_vpsr$$$_fill_1 : 5; unsigned pr17_vpsr$v_aex : 1; /* Vector arithmetic exception (WC) */ unsigned pr17_vpsr$$$_fill_2 : 16; unsigned pr17_vpsr$v_imp : 1; /* Implementation-specific hardware error (WC) */ unsigned pr17_vpsr$$$_fill_3 : 6; unsigned pr17_vpsr$v_bsy : 1; /* Vector processor busy (RO) */ } pr1701r_pr1701vpsr_bits; __struct { unsigned pr17_vaer$v_f_undf : 1; /* Floating underflow */ unsigned pr17_vaer$v_f_divz : 1; /* Floating divide-by-zero */ unsigned pr17_vaer$v_f_ropr : 1; /* Floating reserved operand */ unsigned pr17_vaer$v_f_ovfl : 1; /* Floating overflow */ unsigned pr17_vaer$$$_fill_1 : 1; unsigned pr17_vaer$v_i_ovfl : 1; /* Integer overflow */ unsigned pr17_vaer$$$_fill_2 : 10; unsigned pr17_vaer$v_register_mask : 16; /* Vector destination register mask */ } pr1701r_pr1701vaer_bits; __struct { unsigned biu_ctl$v_bc_en : 1; /* Enable Bcache (WO) */ unsigned biu_ctl$v_ecc : 1; /* ECC/Parity select (WO) */ unsigned biu_ctl$v_oe : 1; /* CE pins not asserted during RAM write cycles (WO) */ unsigned biu_ctl$v_bc_fhit : 1; /* Force Bcache hit (WO) */ unsigned biu_ctl$v_bc_spd : 4; /* Bcache speed (WO) */ unsigned biu_ctl$$$_fill_1 : 20; unsigned biu_ctl$v_bc_size : 3; /* Bcache size (WO) */ unsigned biu_ctl$v_ws_io : 1; /* Workstation IO mapping */ } pr1701r_pr1701biu_ctl_bits; /* Cbox registers, continued */ __struct { unsigned bc_tag$v_hit : 1; /* */ unsigned bc_tag$v_ctl_p : 1; /* tag status parity bit */ unsigned bc_tag$v_ctl_s : 1; /* tag shared bit */ unsigned bc_tag$v_ctl_d : 1; /* tag dirty bit */ unsigned bc_tag$v_ctl_v : 1; /* tag valid bit */ unsigned bc_tag$v_tag : 17; /* tag */ unsigned bc_tag$v_tag_p : 1; /* tag parity */ unsigned bc_tag$v_fill_105 : 1; } pr1701r_pr1701bc_tag_bits; /* Cbox registers, continued */ __struct { unsigned biu_stat$v_biu_herr : 1; /* Hard_Error on cACK */ unsigned biu_stat$v_biu_serr : 1; /* Soft_Error on cACK */ unsigned biu_stat$v_bc_tperr : 1; /* Tag Parity error in tag address RAM */ unsigned biu_stat$v_bc_tcperr : 1; /* Tag Parity error in tag control RAM */ unsigned biu_stat$v_biu_dsp_cmd : 3; /* Cbox cycle type */ unsigned biu_stat$v_biu_seo : 1; /* second BIU or BC error */ unsigned biu_stat$v_fill_ecc : 1; /* ECC error on Pcache fill data */ unsigned biu_stat$v_fill_crd : 1; /* ECC error was correctable */ unsigned biu_stat$v_biu_dperr : 1; /* BIU parity error */ unsigned biu_stat$v_fill_ird : 1; /* error during I stream fill */ unsigned biu_stat$v_fill_qw : 2; /* Quadword within Pcache FILL hexaword which had a FILL error */ unsigned biu_stat$v_fill_seo : 1; /* second FILL error */ unsigned biu_stat$v_raz : 1; /* Read as ZERO */ unsigned biu_stat$v_fill_dsp_cmd : 4; /* Cbox cmd which resulted in FILL error */ unsigned biu_stat$v_lst_wrt : 1; /* Lost write error */ unsigned biu_stat$v_rsvd : 7; /* reserved bits */ unsigned biu_stat$v_biu_addr : 2; /* BIU ADDR bits 33:32 */ unsigned biu_stat$v_fill_addr : 2; /* FILL ADDR bits 33:32 */ } pr1701r_pr1701biu_stat_bits; __struct { unsigned fill_syn$v_lo : 7; /* ECC syndrome bits for low longword */ unsigned fill_syn$v_hi : 7; /* ECC syndrome bits for high longword */ unsigned fill_syn$v_fill_1 : 18; } pr1701r_pr1701fill_syn_bits; /* Cbox registers, continued */ __struct { unsigned stc_result$$$_fill_1 : 2; unsigned stc_result$v_pass : 1; /* Store Conditional passed */ unsigned stc_result$$$_fill_2 : 29; } pr1701r_pr1701stc_result_bits; __struct { unsigned bedecc$v_lo : 7; /* BEDECC bits for low longword */ unsigned bedecc$v_hi : 7; /* BEDECC bits for high longword */ unsigned bedecc$v_fill_1 : 18; } pr1701r_pr1701bedecc_bits; /* Console dispatch structure */ __struct { /* Console dispatch structure */ unsigned int chalt$l_brw_code; /* BRW code */ unsigned int chalt$l_sys_type; /* System Type */ unsigned int chalt$l_cnsl_load_adr; /* Consoles Load address used by SROM */ unsigned int chalt$l_hwrpb_size; /* HWRPB size in pages */ unsigned int chalt$l_hwrpb_phys_adr; /* HWRPB base physical addrress */ unsigned int chalt$l_mem_bitmap_siz; /* Memory bitmap size (bits) */ unsigned int chalt$l_mem_bitmap_phys_adr; /* Memory bitmap physical address */ unsigned int chalt$l_mem_bitmap_chksm; /* Memory bitmap checksum */ } pr1701r_console_dispatch; /* Serial line I/O registers */ __struct { unsigned sio$v_sio_in : 1; /* Serial line/SROM input */ unsigned sio$v_sio_out : 1; /* Serial line/SROM clock output */ unsigned sio$$$_fill_1 : 30; } pr1701r_pr1701sio_bits; __struct { unsigned sio$v_srom_oe : 1; /* SROM output enable */ unsigned sio$v_srom_fast : 1; /* Use fast version of SROM */ unsigned sio$$$_fill_2 : 30; } pr1701r_pr1701sio_ie_bits; __struct { unsigned vmar$$$_fill_1 : 2; unsigned vmar$v_lw : 1; /* longword within quadword */ unsigned vmar$v_sub_block : 2; /* sub-block indicator */ unsigned vmar$v_row_index : 6; /* cache row index */ unsigned vmar$v_addr : 21; /* error address */ } pr1701r_pr1701vmar_bits; __struct { unsigned vtag$v_v : 4; /* data valid bits */ unsigned vtag$v_dp : 4; /* data parity bits */ unsigned vtag$v_tp : 1; /* tag parity bit */ unsigned vtag$$$_fill_1 : 2; /* unused bits (zero) */ unsigned vtag$v_tag : 21; /* tag */ } pr1701r_pr1701vtag_bits; __struct { unsigned icsr$v_enable : 1; /* VIC enable bit (RW) */ unsigned icsr$$$_fill_1 : 1; unsigned icsr$v_lock : 1; /* Register is locked due to an error (WC) */ unsigned icsr$v_dperr : 1; /* Data parity error (RO) */ unsigned icsr$v_tperr : 1; /* Tag parity error (RO) */ unsigned icsr$$$_fill_2 : 27; } pr1701r_pr1701icsr_bits; __struct { unsigned bpcr$v_history : 4; /* branch history bits */ unsigned bpcr$$$_fill_1 : 1; unsigned bpcr$v_mispredict : 1; /* history of last branch */ unsigned bpcr$v_flush_bht : 1; /* flush branch history table */ unsigned bpcr$v_flush_ctr : 1; /* flush branch hist addr counter */ unsigned bpcr$v_load_history : 1; /* write new history to array */ unsigned bpcr$$$_fill_2 : 7; /* unused bits (must be zero) */ unsigned bpcr$v_bpu_algorithm : 16; /* branch prediction algorithm */ } pr1701r_pr1701bpcr_bits; /* The following two registers are for testability and diagnostics use only. */ /* They should not be referenced in normal operation. */ /* These registers are for testability and diagnostics use only. */ /* In normal operation, the equivalent architecturally-defined registers */ /* should be used instead. */ __struct { unsigned pr1701_pamode$v_mode : 1; /* Addressing mode(1 = 32bit addressing) (RW) */ unsigned pr1701_pamode$$$_fill_1 : 31; } pr1701r_pr1701pamode_bits; __struct { unsigned mmests$v_lv : 1; /* ACV fault due to length violation */ unsigned mmests$v_pte_ref : 1; /* ACV/TNV fault occurred on PPTE reference */ unsigned mmests$v_m : 1; /* Reference had write or modify intent */ unsigned mmests$$$_fill_1 : 11; unsigned mmests$v_fault : 2; /* Fault type, one of the following: */ unsigned mmests$$$_fill_2 : 10; unsigned mmests$v_src : 3; /* Shadow copy of LOCK bits (see MSRC$ constants below) */ unsigned mmests$v_lock : 3; /* Lock status (see MSRC$ constant below) */ } pr1701r_pr1701mmests_bits; __struct { unsigned tbsts$v_lock : 1; /* Register is locked due to an error (WC) */ unsigned tbsts$v_dperr : 1; /* Data parity error (RO) */ unsigned tbsts$v_tperr : 1; /* Tag parity error (RO) */ unsigned tbsts$v_em_val : 1; /* EM latch was valid when error occurred (RO) */ unsigned tbsts$v_cmd : 5; /* S5 command when TB parity error occured (RO) */ unsigned tbsts$$$_fill_1 : 20; unsigned tbsts$v_src : 3; /* Source of original refernce (see MSRC$ constants below) (RO) */ } pr1701r_pr1701tbsts_bits; __struct { unsigned pcsts$v_lock : 1; /* Register is locked due to an error (WC) */ unsigned pcsts$v_dperr : 1; /* Data parity error occurred (RO) */ unsigned pcsts$v_right_bank : 1; /* Right bank tag parity error occurred (RO) */ unsigned pcsts$v_left_bank : 1; /* Left bank tag parity error occurred (RO) */ unsigned pcsts$v_cmd : 5; /* S6 command when Pcache parity error occured (RO) */ unsigned pcsts$v_pte_er_wr : 1; /* Hard error on PTE DREAD occurred (orig ref was WRITE) (WC) */ unsigned pcsts$v_pte_er : 1; /* Hard error on PTE DREAD occurred (WC) */ unsigned pcsts$$$_fill_1 : 21; } pr1701r_pr1701pcsts_bits; __struct { unsigned pcctl$v_d_enable : 1; /* Enable for invalidate, D-stream read/write/fill (RW) */ unsigned pcctl$v_i_enable : 1; /* Enable for invalidate, I-stream read/fill (RW) */ unsigned pcctl$v_force_hit : 1; /* Enable force hit on Pcache references (RW) */ unsigned pcctl$v_bank_sel : 1; /* Select left bank if 0, right bank if 1 (RW) */ unsigned pcctl$v_p_enable : 1; /* Enable parity checking (RW) */ unsigned pcctl$v_pmm : 3; /* Mbox performance monitor mode (RW) */ unsigned pcctl$v_elec_disable : 1; /* Pcache electrical disable bit (RW) */ unsigned pcctl$v_red_enable : 1; /* Redundancy enable bit (RO) */ unsigned pcctl$$$_fill_1 : 22; } pr1701r_pr1701pcctl_bits; __struct { unsigned pr17_pctag$v_a : 1; /* Allocation bit corresponding to index of this tag (RW) */ unsigned pr17_pctag$v_v : 4; /* Valid bits corresponding to the 4 data subblocks (RW) */ unsigned pr17_pctag$v_p : 1; /* Tag parity (RW) */ unsigned pr17_pctag$$$_fill_1 : 6; unsigned pr17_pctag$v_tag : 13; /* Tag bits (RW) */ unsigned pr17_pctag$v_fill_106 : 7; } pr1701r_pr1701pctag_bits; __struct { /* Address of Pcache tag IPRs - Base = PCTAG */ unsigned pctaga$$$_fill_1 : 5; unsigned pctaga$v_index : 7; /* Index of PCache tag */ unsigned pctaga$v_b : 1; /* Bank of PCache to access: 0=left, 1=right */ unsigned pctaga$v_fill_107 : 3; } pr1701r_pr1701pctaga_bits; __struct { unsigned pcdap$v_data_parity : 8; /* Even byte parity for the addressed quadword (RW) */ unsigned pcdap$$$_fill_1 : 24; } pr1701r_pr1701pcdap_bits; } ; #if !defined(__VAXC) && !defined(VAXC) #define pr17_savpsl$v_psl_lo pr1701r_pr1701savpsl_bits.pr17_savpsl$v_psl_lo #define pr17_savpsl$v_haltcode pr1701r_pr1701savpsl_bits.pr17_savpsl$v_haltcode #define pr17_savpsl$v_invalid pr1701r_pr1701savpsl_bits.pr17_savpsl$v_invalid #define pr17_savpsl$v_mapen pr1701r_pr1701savpsl_bits.pr17_savpsl$v_mapen #define pr17_savpsl$v_psl_hi pr1701r_pr1701savpsl_bits.pr17_savpsl$v_psl_hi #define iak$v_ipl17 pr1701r_pr1701iak_vector.iak$v_ipl17 #define iak$v_pr pr1701r_pr1701iak_vector.iak$v_pr #define iak$v_scb_offset pr1701r_pr1701iak_vector.iak$v_scb_offset #define intsys$v_iccs6 pr1701r_pr1701intsys_bits.intsys$v_iccs6 #define intsys$v_sisr pr1701r_pr1701intsys_bits.intsys$v_sisr #define intsys$v_int_id pr1701r_pr1701intsys_bits.intsys$v_int_id #define intsys$v_int_tim_reset pr1701r_pr1701intsys_bits.intsys$v_int_tim_reset #define intsys$v_s_err_reset pr1701r_pr1701intsys_bits.intsys$v_s_err_reset #define intsys$v_pmon_reset pr1701r_pr1701intsys_bits.intsys$v_pmon_reset #define intsys$v_h_err_reset pr1701r_pr1701intsys_bits.intsys$v_h_err_reset #define intsys$v_pwrfl_reset pr1701r_pr1701intsys_bits.intsys$v_pwrfl_reset #define intsys$v_halt_reset pr1701r_pr1701intsys_bits.intsys$v_halt_reset #define pmfcnt$v_pmctr0 pr1701r_pr1701pmfcnt_bits.pmfcnt$v_pmctr0 #define pmfcnt$v_pmctr1 pr1701r_pr1701pmfcnt_bits.pmfcnt$v_pmctr1 #define pcscr$v_par_port_dis pr1701r_pr1701pcscr_bits.pcscr$v_par_port_dis #define pcscr$v_pcs_enb pr1701r_pr1701pcscr_bits.pcscr$v_pcs_enb #define pcscr$v_pcs_write pr1701r_pr1701pcscr_bits.pcscr$v_pcs_write #define pcscr$v_rwl_shift pr1701r_pr1701pcscr_bits.pcscr$v_rwl_shift #define pcscr$v_data pr1701r_pr1701pcscr_bits.pcscr$v_data #define pcscr$v_nonstandard_patch pr1701r_pr1701pcscr_bits.pcscr$v_nonstandard_patch #define pcscr$v_patch_rev pr1701r_pr1701pcscr_bits.pcscr$v_patch_rev #define ecr$v_vector_present pr1701r_pr1701ecr_bits.ecr$v_vector_present #define ecr$v_fbox_enable pr1701r_pr1701ecr_bits.ecr$v_fbox_enable #define ecr$v_timeout_ext pr1701r_pr1701ecr_bits.ecr$v_timeout_ext #define ecr$v_fbox_st4_bypass_enable pr1701r_pr1701ecr_bits.ecr$v_fbox_st4_bypass_enable #define ecr$v_timeout_occurred pr1701r_pr1701ecr_bits.ecr$v_timeout_occurred #define ecr$v_timeout_test pr1701r_pr1701ecr_bits.ecr$v_timeout_test #define ecr$v_timeout_clock pr1701r_pr1701ecr_bits.ecr$v_timeout_clock #define ecr$v_fbox_test_enable pr1701r_pr1701ecr_bits.ecr$v_fbox_test_enable #define ecr$v_pmf_enable pr1701r_pr1701ecr_bits.ecr$v_pmf_enable #define ecr$v_pmf_pmux pr1701r_pr1701ecr_bits.ecr$v_pmf_pmux #define ecr$v_pmf_emux pr1701r_pr1701ecr_bits.ecr$v_pmf_emux #define ecr$v_pmf_lfsr pr1701r_pr1701ecr_bits.ecr$v_pmf_lfsr #define ecr$v_pmf_clear pr1701r_pr1701ecr_bits.ecr$v_pmf_clear #define mtbtag$v_tp pr1701r_pr1701mtbtag_bits.mtbtag$v_tp #define mtbtag$v_vpn pr1701r_pr1701mtbtag_bits.mtbtag$v_vpn #define mtbpte$v_pfn pr1701r_pr1701mtbpte_bits.mtbpte$v_pfn #define mtbpte$v_p pr1701r_pr1701mtbpte_bits.mtbpte$v_p #define mtbpte$v_m pr1701r_pr1701mtbpte_bits.mtbpte$v_m #define mtbpte$v_prot pr1701r_pr1701mtbpte_bits.mtbpte$v_prot #define mtbpte$v_v pr1701r_pr1701mtbpte_bits.mtbpte$v_v #define pr17_vpsr$v_ven pr1701r_pr1701vpsr_bits.pr17_vpsr$v_ven #define pr17_vpsr$v_rst pr1701r_pr1701vpsr_bits.pr17_vpsr$v_rst #define pr17_vpsr$v_aex pr1701r_pr1701vpsr_bits.pr17_vpsr$v_aex #define pr17_vpsr$v_imp pr1701r_pr1701vpsr_bits.pr17_vpsr$v_imp #define pr17_vpsr$v_bsy pr1701r_pr1701vpsr_bits.pr17_vpsr$v_bsy #define pr17_vaer$v_f_undf pr1701r_pr1701vaer_bits.pr17_vaer$v_f_undf #define pr17_vaer$v_f_divz pr1701r_pr1701vaer_bits.pr17_vaer$v_f_divz #define pr17_vaer$v_f_ropr pr1701r_pr1701vaer_bits.pr17_vaer$v_f_ropr #define pr17_vaer$v_f_ovfl pr1701r_pr1701vaer_bits.pr17_vaer$v_f_ovfl #define pr17_vaer$v_i_ovfl pr1701r_pr1701vaer_bits.pr17_vaer$v_i_ovfl #define pr17_vaer$v_register_mask pr1701r_pr1701vaer_bits.pr17_vaer$v_register_mask #define biu_ctl$v_bc_en pr1701r_pr1701biu_ctl_bits.biu_ctl$v_bc_en #define biu_ctl$v_ecc pr1701r_pr1701biu_ctl_bits.biu_ctl$v_ecc #define biu_ctl$v_oe pr1701r_pr1701biu_ctl_bits.biu_ctl$v_oe #define biu_ctl$v_bc_fhit pr1701r_pr1701biu_ctl_bits.biu_ctl$v_bc_fhit #define biu_ctl$v_bc_spd pr1701r_pr1701biu_ctl_bits.biu_ctl$v_bc_spd #define biu_ctl$v_bc_size pr1701r_pr1701biu_ctl_bits.biu_ctl$v_bc_size #define biu_ctl$v_ws_io pr1701r_pr1701biu_ctl_bits.biu_ctl$v_ws_io #define bc_tag$v_hit pr1701r_pr1701bc_tag_bits.bc_tag$v_hit #define bc_tag$v_ctl_p pr1701r_pr1701bc_tag_bits.bc_tag$v_ctl_p #define bc_tag$v_ctl_s pr1701r_pr1701bc_tag_bits.bc_tag$v_ctl_s #define bc_tag$v_ctl_d pr1701r_pr1701bc_tag_bits.bc_tag$v_ctl_d #define bc_tag$v_ctl_v pr1701r_pr1701bc_tag_bits.bc_tag$v_ctl_v #define bc_tag$v_tag pr1701r_pr1701bc_tag_bits.bc_tag$v_tag #define bc_tag$v_tag_p pr1701r_pr1701bc_tag_bits.bc_tag$v_tag_p #define biu_stat$v_biu_herr pr1701r_pr1701biu_stat_bits.biu_stat$v_biu_herr #define biu_stat$v_biu_serr pr1701r_pr1701biu_stat_bits.biu_stat$v_biu_serr #define biu_stat$v_bc_tperr pr1701r_pr1701biu_stat_bits.biu_stat$v_bc_tperr #define biu_stat$v_bc_tcperr pr1701r_pr1701biu_stat_bits.biu_stat$v_bc_tcperr #define biu_stat$v_biu_dsp_cmd pr1701r_pr1701biu_stat_bits.biu_stat$v_biu_dsp_cmd #define biu_stat$v_biu_seo pr1701r_pr1701biu_stat_bits.biu_stat$v_biu_seo #define biu_stat$v_fill_ecc pr1701r_pr1701biu_stat_bits.biu_stat$v_fill_ecc #define biu_stat$v_fill_crd pr1701r_pr1701biu_stat_bits.biu_stat$v_fill_crd #define biu_stat$v_biu_dperr pr1701r_pr1701biu_stat_bits.biu_stat$v_biu_dperr #define biu_stat$v_fill_ird pr1701r_pr1701biu_stat_bits.biu_stat$v_fill_ird #define biu_stat$v_fill_qw pr1701r_pr1701biu_stat_bits.biu_stat$v_fill_qw #define biu_stat$v_fill_seo pr1701r_pr1701biu_stat_bits.biu_stat$v_fill_seo #define biu_stat$v_raz pr1701r_pr1701biu_stat_bits.biu_stat$v_raz #define biu_stat$v_fill_dsp_cmd pr1701r_pr1701biu_stat_bits.biu_stat$v_fill_dsp_cmd #define biu_stat$v_lst_wrt pr1701r_pr1701biu_stat_bits.biu_stat$v_lst_wrt #define biu_stat$v_rsvd pr1701r_pr1701biu_stat_bits.biu_stat$v_rsvd #define biu_stat$v_biu_addr pr1701r_pr1701biu_stat_bits.biu_stat$v_biu_addr #define biu_stat$v_fill_addr pr1701r_pr1701biu_stat_bits.biu_stat$v_fill_addr #define fill_syn$v_lo pr1701r_pr1701fill_syn_bits.fill_syn$v_lo #define fill_syn$v_hi pr1701r_pr1701fill_syn_bits.fill_syn$v_hi #define fill_syn$v_fill_1 pr1701r_pr1701fill_syn_bits.fill_syn$v_fill_1 #define stc_result$v_pass pr1701r_pr1701stc_result_bits.stc_result$v_pass #define bedecc$v_lo pr1701r_pr1701bedecc_bits.bedecc$v_lo #define bedecc$v_hi pr1701r_pr1701bedecc_bits.bedecc$v_hi #define bedecc$v_fill_1 pr1701r_pr1701bedecc_bits.bedecc$v_fill_1 #define chalt$l_brw_code pr1701r_console_dispatch.chalt$l_brw_code #define chalt$l_sys_type pr1701r_console_dispatch.chalt$l_sys_type #define chalt$l_cnsl_load_adr pr1701r_console_dispatch.chalt$l_cnsl_load_adr #define chalt$l_hwrpb_size pr1701r_console_dispatch.chalt$l_hwrpb_size #define chalt$l_hwrpb_phys_adr pr1701r_console_dispatch.chalt$l_hwrpb_phys_adr #define chalt$l_mem_bitmap_siz pr1701r_console_dispatch.chalt$l_mem_bitmap_siz #define chalt$l_mem_bitmap_phys_adr pr1701r_console_dispatch.chalt$l_mem_bitmap_phys_adr #define chalt$l_mem_bitmap_chksm pr1701r_console_dispatch.chalt$l_mem_bitmap_chksm #define sio$v_sio_in pr1701r_pr1701sio_bits.sio$v_sio_in #define sio$v_sio_out pr1701r_pr1701sio_bits.sio$v_sio_out #define sio$v_srom_oe pr1701r_pr1701sio_ie_bits.sio$v_srom_oe #define sio$v_srom_fast pr1701r_pr1701sio_ie_bits.sio$v_srom_fast #define vmar$v_lw pr1701r_pr1701vmar_bits.vmar$v_lw #define vmar$v_sub_block pr1701r_pr1701vmar_bits.vmar$v_sub_block #define vmar$v_row_index pr1701r_pr1701vmar_bits.vmar$v_row_index #define vmar$v_addr pr1701r_pr1701vmar_bits.vmar$v_addr #define vtag$v_v pr1701r_pr1701vtag_bits.vtag$v_v #define vtag$v_dp pr1701r_pr1701vtag_bits.vtag$v_dp #define vtag$v_tp pr1701r_pr1701vtag_bits.vtag$v_tp #define vtag$v_tag pr1701r_pr1701vtag_bits.vtag$v_tag #define icsr$v_enable pr1701r_pr1701icsr_bits.icsr$v_enable #define icsr$v_lock pr1701r_pr1701icsr_bits.icsr$v_lock #define icsr$v_dperr pr1701r_pr1701icsr_bits.icsr$v_dperr #define icsr$v_tperr pr1701r_pr1701icsr_bits.icsr$v_tperr #define bpcr$v_history pr1701r_pr1701bpcr_bits.bpcr$v_history #define bpcr$v_mispredict pr1701r_pr1701bpcr_bits.bpcr$v_mispredict #define bpcr$v_flush_bht pr1701r_pr1701bpcr_bits.bpcr$v_flush_bht #define bpcr$v_flush_ctr pr1701r_pr1701bpcr_bits.bpcr$v_flush_ctr #define bpcr$v_load_history pr1701r_pr1701bpcr_bits.bpcr$v_load_history #define bpcr$v_bpu_algorithm pr1701r_pr1701bpcr_bits.bpcr$v_bpu_algorithm #define pr1701_pamode$v_mode pr1701r_pr1701pamode_bits.pr1701_pamode$v_mode #define mmests$v_lv pr1701r_pr1701mmests_bits.mmests$v_lv #define mmests$v_pte_ref pr1701r_pr1701mmests_bits.mmests$v_pte_ref #define mmests$v_m pr1701r_pr1701mmests_bits.mmests$v_m #define mmests$v_fault pr1701r_pr1701mmests_bits.mmests$v_fault #define mmests$v_src pr1701r_pr1701mmests_bits.mmests$v_src #define mmests$v_lock pr1701r_pr1701mmests_bits.mmests$v_lock #define tbsts$v_lock pr1701r_pr1701tbsts_bits.tbsts$v_lock #define tbsts$v_dperr pr1701r_pr1701tbsts_bits.tbsts$v_dperr #define tbsts$v_tperr pr1701r_pr1701tbsts_bits.tbsts$v_tperr #define tbsts$v_em_val pr1701r_pr1701tbsts_bits.tbsts$v_em_val #define tbsts$v_cmd pr1701r_pr1701tbsts_bits.tbsts$v_cmd #define tbsts$v_src pr1701r_pr1701tbsts_bits.tbsts$v_src #define pcsts$v_lock pr1701r_pr1701pcsts_bits.pcsts$v_lock #define pcsts$v_dperr pr1701r_pr1701pcsts_bits.pcsts$v_dperr #define pcsts$v_right_bank pr1701r_pr1701pcsts_bits.pcsts$v_right_bank #define pcsts$v_left_bank pr1701r_pr1701pcsts_bits.pcsts$v_left_bank #define pcsts$v_cmd pr1701r_pr1701pcsts_bits.pcsts$v_cmd #define pcsts$v_pte_er_wr pr1701r_pr1701pcsts_bits.pcsts$v_pte_er_wr #define pcsts$v_pte_er pr1701r_pr1701pcsts_bits.pcsts$v_pte_er #define pcctl$v_d_enable pr1701r_pr1701pcctl_bits.pcctl$v_d_enable #define pcctl$v_i_enable pr1701r_pr1701pcctl_bits.pcctl$v_i_enable #define pcctl$v_force_hit pr1701r_pr1701pcctl_bits.pcctl$v_force_hit #define pcctl$v_bank_sel pr1701r_pr1701pcctl_bits.pcctl$v_bank_sel #define pcctl$v_p_enable pr1701r_pr1701pcctl_bits.pcctl$v_p_enable #define pcctl$v_pmm pr1701r_pr1701pcctl_bits.pcctl$v_pmm #define pcctl$v_elec_disable pr1701r_pr1701pcctl_bits.pcctl$v_elec_disable #define pcctl$v_red_enable pr1701r_pr1701pcctl_bits.pcctl$v_red_enable #define pr17_pctag$v_a pr1701r_pr1701pctag_bits.pr17_pctag$v_a #define pr17_pctag$v_v pr1701r_pr1701pctag_bits.pr17_pctag$v_v #define pr17_pctag$v_p pr1701r_pr1701pctag_bits.pr17_pctag$v_p #define pr17_pctag$v_tag pr1701r_pr1701pctag_bits.pr17_pctag$v_tag #define pctaga$v_index pr1701r_pr1701pctaga_bits.pctaga$v_index #define pctaga$v_b pr1701r_pr1701pctaga_bits.pctaga$v_b #define pcdap$v_data_parity pr1701r_pr1701pcdap_bits.pcdap$v_data_parity #endif /* #if !defined(__VAXC) && !defined(VAXC) */ #ifdef __cplusplus } #endif #pragma standard #endif /* __PR1701DEF_LOADED */