/********************************************************************************************************************************/ /* Created: 15-MAR-2001 23:38:09 by OpenVMS SDL EV1-33 */ /* Source: 15-MAR-2001 23:34:16 _$11$DUA933:[BUILD.SDL]STARDEFMP.SDI;1 */ /********************************************************************************************************************************/ /*** MODULE $PR13DEF ***/ #ifndef __PR13DEF_LOADED #define __PR13DEF_LOADED 1 #pragma nostandard #ifdef __cplusplus extern "C" { #define __unknown_params ... #else #define __unknown_params #endif #if !defined(__VAXC) && !defined(VAXC) #define __struct struct #define __union union #else #define __struct variant_struct #define __union variant_union #endif #define PR13$K_REVISION 30 /* Revision number of this file */ /* In the definitions below, registers are annotated with one of the following */ /* symbols: */ /* */ /* RW - The register may be read and written */ /* RO - The register may only be read */ /* WO - The register may only be written */ /* */ /* For RO and WO registers, all bits and fields within the register are also */ /* read-only or write-only. For RW registers, each bit or field within */ /* the register is annotated with one of the following: */ /* */ /* RW - The bit/field may be read and written */ /* RO - The bit/field may be read; writes are ignored */ /* WO - The bit/field may be written; reads return an UNPREDICTABLE result. */ /* WZ - The bit/field may be written; reads return a 0 */ /* WC - The bit/field may be read; writes cause state to clear */ /* RC - The bit/field may be read, which also causes state to clear; writes are ignored */ #define PR13$_TODR 27 /* Time Of Year Register (RW) */ #define PR13$_MCESR 38 /* Machine check error register (WO) */ #define PR13$_SAVPC 42 /* Console saved PC (RO) */ #define PR13$_SAVPSL 43 /* Console saved PSL (RO) */ #define PR13_SAVPSL$M_PSL_LO 0xFF #define PR13_SAVPSL$M_HALTCODE 0x3F00 #define PR13_SAVPSL$K_HALT_HLTPIN 2 /* HALT_L pin asserted */ #define PR13_SAVPSL$K_HALT_PWRUP 3 /* Initial powerup */ #define PR13_SAVPSL$K_HALT_INTSTK 4 /* Interrupt stack not valid */ #define PR13_SAVPSL$K_HALT_DOUBLE 5 /* Machine check during exception processing */ #define PR13_SAVPSL$K_HALT_HLTINS 6 /* Halt instruction in kernel mode */ #define PR13_SAVPSL$K_HALT_ILLVEC 7 /* Illegal SCB vector (bits<1:0>=11) */ #define PR13_SAVPSL$K_HALT_WCSVEC 8 /* WCS SCB vector (bits<1:0>=10) */ #define PR13_SAVPSL$K_HALT_CHMFI 10 /* CHMx on interrupt stack */ #define PR13_SAVPSL$K_HALT_IE0 16 /* ACV/TNV during machine check processing */ #define PR13_SAVPSL$K_HALT_IE1 17 /* ACV/TNV during KSNV processing */ #define PR13_SAVPSL$K_HALT_IE2 18 /* Machine check during machine check processing */ #define PR13_SAVPSL$K_HALT_IE3 19 /* Machine check during KSNV processing */ #define PR13_SAVPSL$K_HALT_IE_PSL_101 25 /* PSL<26:24>=101 during interrupt or exception */ #define PR13_SAVPSL$K_HALT_IE_PSL_110 26 /* PSL<26:24>=110 during interrupt or exception */ #define PR13_SAVPSL$K_HALT_IE_PSL_111 27 /* PSL<26:24>=111 during interrupt or exception */ #define PR13_SAVPSL$K_HALT_REI_PSL_101 29 /* PSL<26:24>=101 during REI */ #define PR13_SAVPSL$K_HALT_REI_PSL_110 30 /* PSL<26:24>=110 during REI */ #define PR13_SAVPSL$K_HALT_REI_PSL_111 31 /* PSL<26:24>=111 during REI */ #define PR13_SAVPSL$M_INVALID 0x4000 #define PR13_SAVPSL$M_MAPEN 0x8000 #define PR13_SAVPSL$M_PSL_HI 0xFFFF0000 #define PR13$_IORESET 55 /* I/O system reset register (WO) */ #define PR13$_PME 61 /* Performance monitoring enable (RW) */ #define PR13$_SID 62 /* System identification register (RO) */ #define PR13_SID$M_UCODE_REV 0xFF #define PR13_SID$M_NONSTANDARD_PATCH 0x100 #define PR13_SID$M_PATCH_REV 0x3E00 #define PR13_SID$M_TYPE 0xFF000000 #define PR13$_IAK14 64 /* Level 14 interrupt acknowledge (RO) */ #define PR13$_IAK15 65 /* Level 15 interrupt acknowledge (RO) */ #define PR13$_IAK16 66 /* Level 16 interrupt acknowledge (RO) */ #define PR13$_IAK17 67 /* Level 17 interrupt acknowledge (RO) */ #define PR13_IAK$M_IPL17 0x1 #define PR13_IAK$M_PR 0x2 #define PR13_IAK$M_SCB_OFFSET 0xFFFC #define PR13$_CWB 68 /* Clear write buffers (RW) */ /* Ebox registers. */ #define PR13$_INTSYS 122 /* Interrupt system status register (RW) */ #define PR13_INTSYS$M_ICCS6 0x1 #define PR13_INTSYS$M_SISR 0xFFFE #define PR13_INTSYS$M_INT_ID 0x1F0000 #define PR13_INTSYS$K_INT_ID_HALT 31 /* Halt pin */ #define PR13_INTSYS$K_INT_ID_PWRFL 30 /* Power fail */ #define PR13_INTSYS$K_INT_ID_H_ERR 29 /* Hard error */ #define PR13_INTSYS$K_INT_ID_INT_TIM 28 /* Interval timer */ #define PR13_INTSYS$K_INT_ID_PMON 27 /* Performance monitor */ #define PR13_INTSYS$K_INT_ID_S_ERR 26 /* Soft error */ #define PR13_INTSYS$K_INT_ID_IRQ3 23 /* IPL 17 device interrupt */ #define PR13_INTSYS$K_INT_ID_IRQ2 22 /* IPL 16 device interrupt */ #define PR13_INTSYS$K_INT_ID_IRQ1 21 /* IPL 15 device interrupt */ #define PR13_INTSYS$K_INT_ID_IRQ0 20 /* IPL 14 device interrupt */ #define PR13_INTSYS$K_INT_ID_SISR15 15 /* SISR<15> */ #define PR13_INTSYS$K_INT_ID_SISR14 14 /* SISR<14> */ #define PR13_INTSYS$K_INT_ID_SISR13 13 /* SISR<13> */ #define PR13_INTSYS$K_INT_ID_SISR12 12 /* SISR<12> */ #define PR13_INTSYS$K_INT_ID_SISR11 11 /* SISR<11> */ #define PR13_INTSYS$K_INT_ID_SISR10 10 /* SISR<10> */ #define PR13_INTSYS$K_INT_ID_SISR9 9 /* SISR<9> */ #define PR13_INTSYS$K_INT_ID_SISR8 8 /* SISR<8> */ #define PR13_INTSYS$K_INT_ID_SISR7 7 /* SISR<7> */ #define PR13_INTSYS$K_INT_ID_SISR6 6 /* SISR<6> */ #define PR13_INTSYS$K_INT_ID_SISR5 5 /* SISR<5> */ #define PR13_INTSYS$K_INT_ID_SISR4 4 /* SISR<4> */ #define PR13_INTSYS$K_INT_ID_SISR3 3 /* SISR<3> */ #define PR13_INTSYS$K_INT_ID_SISR2 2 /* SISR<2> */ #define PR13_INTSYS$K_INT_ID_SISR1 1 /* SISR<1> */ #define PR13_INTSYS$K_INT_ID_NO_INT 0 /* No interrupt */ #define PR13_INTSYS$M_INT_TIM_RESET 0x1000000 #define PR13_INTSYS$M_S_ERR_RESET 0x8000000 #define PR13_INTSYS$M_PMON_RESET 0x10000000 #define PR13_INTSYS$M_H_ERR_RESET 0x20000000 #define PR13_INTSYS$M_PWRFL_RESET 0x40000000 #define PR13_INTSYS$M_HALT_RESET 0x80000000 #define PR13$_PMFCNT 123 /* Performance monitoring facility count register (RW) */ #define PR13_PMFCNT$M_PMCTR0 0xFFFF #define PR13_PMFCNT$M_PMCTR1 0xFFFF0000 #define PR13$_PCSCR 124 /* Patchable control store control register (RW) */ #define PR13_PCSCR$M_PAR_PORT_DIS 0x100 #define PR13_PCSCR$M_PCS_ENB 0x200 #define PR13_PCSCR$M_PCS_WRITE 0x400 #define PR13_PCSCR$M_RWL_SHIFT 0x800 #define PR13_PCSCR$M_DATA 0x1000 #define PR13_PCSCR$M_NONSTANDARD_PATCH 0x800000 #define PR13_PCSCR$M_PATCH_REV 0x1F000000 #define PR13$_ECR 125 /* Ebox control register (RW) */ #define PR13_ECR$M_VECTOR_PRESENT 0x1 #define PR13_ECR$M_FBOX_ENABLE 0x2 #define PR13_ECR$M_TIMEOUT_EXT 0x4 #define PR13_ECR$M_FBOX_ST4_BYPASS_ENA 0x8 #define PR13_ECR$M_TIMEOUT_OCCURRED 0x10 #define PR13_ECR$M_TIMEOUT_TEST 0x20 #define PR13_ECR$M_TIMEOUT_CLOCK 0x40 #define PR13_ECR$M_ICCS_EXT 0x80 #define PR13_ECR$M_FBOX_TEST_ENABLE 0x2000 #define PR13_ECR$M_PMF_ENABLE 0x10000 #define PR13_ECR$M_PMF_PMUX 0x60000 #define PR13_ECR$K_PMUX_IBOX 0 /* Select Ibox */ #define PR13_ECR$K_PMUX_EBOX 1 /* Select Ebox */ #define PR13_ECR$K_PMUX_MBOX 2 /* Select Mbox */ #define PR13_ECR$K_PMUX_CBOX 3 /* Select Cbox */ #define PR13_ECR$M_PMF_EMUX 0x380000 #define PR13_ECR$K_EMUX_S3_STALL 0 /* Measure S3 stall against total cycles */ #define PR13_ECR$K_EMUX_EM_PA_STALL 1 /* Measure EM+PA queue stall against total cycles */ #define PR13_ECR$K_EMUX_CPI 2 /* Measure instructions retired against total cycles */ #define PR13_ECR$K_EMUX_STALL 3 /* Measure total stalls against total cycles */ #define PR13_ECR$K_EMUX_S3_STALL_PCT 4 /* Measure S3 stall against total stalls */ #define PR13_ECR$K_EMUX_EM_PA_STALL_PCT 5 /* Measure EM+PA queue stall against total stalls */ #define PR13_ECR$K_EMUX_UWORD 7 /* Count microword increments */ #define PR13_ECR$M_PMF_LFSR 0x400000 #define PR13_ECR$M_PMF_CLEAR 0x80000000 #define PR13$_MTBTAG 126 /* Mbox TB tag fill (WO) */ #define PR13_MTBTAG$M_TP 0x1 #define PR13_MTBTAG$M_VPN 0xFFFFFE00 #define PR13$_MTBPTE 127 /* Mbox TB PTE fill (WO) */ #define PR13_MTBPTE$M_PFN 0x7FFFFF #define PR13_MTBPTE$M_P 0x1000000 #define PR13_MTBPTE$M_M 0x4000000 #define PR13_MTBPTE$M_PROT 0x18000000 #define PR13_MTBPTE$M_V 0x20000000 #define PR13$_VPSR 144 /* Vector processor status register (RW) */ #define PR13_VPSR$M_VEN 0x1 #define PR13_VPSR$M_RST 0x2 #define PR13_VPSR$M_AEX 0x80 #define PR13_VPSR$M_IMP 0x1000000 #define PR13_VPSR$M_BSY 0x80000000 #define PR13$_VAER 145 /* Vector arithmetic exception register (RO) */ #define PR13_VAER$M_F_UNDF 0x1 #define PR13_VAER$M_F_DIVZ 0x2 #define PR13_VAER$M_F_ROPR 0x4 #define PR13_VAER$M_F_OVFL 0x8 #define PR13_VAER$M_I_OVFL 0x20 #define PR13_VAER$M_REGISTER_MASK 0xFFFF0000 #define PR13$_VMAC 146 /* Vector memory activity register (RO) */ #define PR13$_VTBIA 147 /* Vector translation buffer invalidate all (WO) */ /* Cbox registers. */ #define PR13$_CCTL 160 /* Cbox control register (RW) */ #define PR13_CCTL$M_ENABLE 0x1 #define PR13_CCTL$M_TAG_SPEED 0x2 #define PR13_CCTL$K_TAG_3_CYCLES 0 /* Select tag RAM speed: 3-cycle read rep/3-cycle write rep */ #define PR13_CCTL$K_TAG_4_CYCLES 1 /* Select tag RAM speed: 4-cycle read rep/4-cycle write rep */ #define PR13_CCTL$M_DATA_SPEED 0xC #define PR13_CCTL$K_DATA_2_CYCLES 0 /* Select data RAM speed: 2-cycle read rep/3-cycle write rep */ #define PR13_CCTL$K_DATA_3_CYCLES 1 /* Select data RAM speed: 3-cycle read rep/4-cycle write rep */ #define PR13_CCTL$K_DATA_4_CYCLES 2 /* Select data RAM speed: 4-cycle read rep/5-cycle write rep */ #define PR13_CCTL$M_SIZE 0x30 #define PR13_CCTL$K_SIZE_128KB 0 /* Select 128KB Bcache */ #define PR13_CCTL$K_SIZE_256KB 1 /* Select 256KB Bcache */ #define PR13_CCTL$K_SIZE_512KB 2 /* Select 512KB Bcache */ #define PR13_CCTL$K_SIZE_2MB 3 /* Select 2MB Bcache */ #define PR13_CCTL$M_FORCE_HIT 0x40 #define PR13_CCTL$M_DISABLE_ERRORS 0x80 #define PR13_CCTL$M_SW_ECC 0x100 #define PR13_CCTL$M_TIMEOUT_TEST 0x200 #define PR13_CCTL$M_DISABLE_PACK 0x400 #define PR13_CCTL$M_PM_ACCESS_TYPE 0x3800 #define PR13_CCTL$K_PMAT_COH 0 /* Coherency access of either type */ #define PR13_CCTL$K_PMAT_COH_READ 1 /* Coherency access for READ */ #define PR13_CCTL$K_PMAT_COH_OREAD 2 /* Coherency access for OREAD */ #define PR13_CCTL$K_PMAT_CPU 4 /* CPU access of any type */ #define PR13_CCTL$K_PMAT_CPU_IREAD 5 /* CPU access for IREAD */ #define PR13_CCTL$K_PMAT_CPU_DREAD 6 /* CPU access for DREAD */ #define PR13_CCTL$K_PMAT_CPU_OREAD 7 /* CPU access for OREAD */ #define PR13_CCTL$M_PM_HIT_TYPE 0xC000 #define PR13_CCTL$K_PMHT_HIT 0 /* Hit */ #define PR13_CCTL$K_PMHT_HIT_OWNED 1 /* Hit on owned block */ #define PR13_CCTL$K_PMHT_HIT_VALID 2 /* Hit on valid block */ #define PR13_CCTL$K_PMHT_MISS_OWNED 3 /* Miss on owned block (causes writeback) */ #define PR13_CCTL$M_FORCE_NDAL_PERR 0x10000 #define PR13_CCTL$M_SW_ETM 0x40000000 #define PR13_CCTL$M_HW_ETM 0x80000000 #define PR13$_BCDECC 162 /* Bcache data ram ECC (WO) */ #define PR13_BCDECC$M_ECCLO 0x3C0 #define PR13_BCDECC$M_ECCHI 0x3C00000 #define PR13$_BCETSTS 163 /* Bcache error tag status (RW) */ #define PR13_BCETSTS$M_LOCK 0x1 #define PR13_BCETSTS$M_CORR 0x2 #define PR13_BCETSTS$M_UNCORR 0x4 #define PR13_BCETSTS$M_BAD_ADDR 0x8 #define PR13_BCETSTS$M_LOST_ERR 0x10 #define PR13_BCETSTS$M_TS_CMD 0x3E0 #define PR13_BCETSTS$K_CMD_DREAD 7 /* Command was D-stream tag lookup */ #define PR13_BCETSTS$K_CMD_IREAD 3 /* Command was I-stream tag lookup */ #define PR13_BCETSTS$K_CMD_OREAD 2 /* Command was OREAD tag lookup for write or read lock */ #define PR13_BCETSTS$K_CMD_WUNLOCK 8 /* Command was write unlock tag lookup (done only under ETM) */ #define PR13_BCETSTS$K_CMD_R_INVAL 13 /* Command was inval tag lookup for NDAL DREAD or IREAD */ #define PR13_BCETSTS$K_CMD_O_INVAL 9 /* Command was inval tag lookup for NDAL OREAD or WRITE */ #define PR13_BCETSTS$K_CMD_IPR_DEALLOC 10 /* Command was tag lookup for IPR deallocate */ #define PR13$_BCETIDX 164 /* Bcache error tag index (RO) */ #define PR13$_BCETAG 165 /* Bcache error tag (RO) */ #define PR13_BCETAG$M_VALID 0x200 #define PR13_BCETAG$M_OWNED 0x400 #define PR13_BCETAG$M_ECC 0x1F800 #define PR13_BCETAG$M_TAG 0xFFFE0000 #define PR13$_BCEDSTS 166 /* Bcache error data status (RW) */ #define PR13_BCEDSTS$M_LOCK 0x1 #define PR13_BCEDSTS$M_CORR 0x2 #define PR13_BCEDSTS$M_UNCORR 0x4 #define PR13_BCEDSTS$M_BAD_ADDR 0x8 #define PR13_BCEDSTS$M_LOST_ERR 0x10 #define PR13_BCEDSTS$M_DR_CMD 0xF00 #define PR13_BCEDSTS$K_CMD_DREAD 7 /* Command was D-stream data lookup */ #define PR13_BCEDSTS$K_CMD_IREAD 3 /* Command was I-stream data lookup */ #define PR13_BCEDSTS$K_CMD_WBACK 4 /* Command was writeback data lookup */ #define PR13_BCEDSTS$K_CMD_RMW 2 /* Command was read-modify-write data lookup */ #define PR13$_BCEDIDX 167 /* Bcache error data index (RO) */ #define PR13$_BCEDECC 168 /* Bcache error ECC (RO) */ #define PR13_BCEDECC$M_ECCLO 0x3C0 #define PR13_BCEDECC$M_ECCHI 0x3C00000 #define PR13$_CEFADR 171 /* Fill error address (RO) */ #define PR13$_CEFSTS 172 /* Fill error status (RW) */ #define PR13_CEFSTS$M_RDLK 0x1 #define PR13_CEFSTS$M_LOCK 0x2 #define PR13_CEFSTS$M_TIMEOUT 0x4 #define PR13_CEFSTS$M_RDE 0x8 #define PR13_CEFSTS$M_LOST_ERR 0x10 #define PR13_CEFSTS$M_ID0 0x20 #define PR13_CEFSTS$M_IREAD 0x40 #define PR13_CEFSTS$M_OREAD 0x80 #define PR13_CEFSTS$M_WRITE 0x100 #define PR13_CEFSTS$M_TO_MBOX 0x200 #define PR13_CEFSTS$M_RIP 0x400 #define PR13_CEFSTS$M_OIP 0x800 #define PR13_CEFSTS$M_DNF 0x1000 #define PR13_CEFSTS$M_RDLK_FL_DONE 0x2000 #define PR13_CEFSTS$M_REQ_FILL_DONE 0x4000 #define PR13_CEFSTS$M_COUNT 0x18000 #define PR13_CEFSTS$M_UNEXPECTED_FILL 0x200000 #define PR13$_NESTS 174 /* NDAL error status (RW) */ #define PR13_NESTS$M_NOACK 0x1 #define PR13_NESTS$M_BADWDATA 0x2 #define PR13_NESTS$M_LOST_OERR 0x4 #define PR13_NESTS$M_PERR 0x8 #define PR13_NESTS$M_INCON_PERR 0x10 #define PR13_NESTS$M_LOST_PERR 0x20 #define PR13$_NEOADR 176 /* NDAL error output address (RO) */ #define PR13$_NEOCMD 178 /* NDAL error output command (RO) */ #define PR13_NEOCMD$M_CMD 0xF #define PR13_NEOCMD$M_ID 0x70 #define PR13_NEOCMD$M_BYTE_EN 0xFF00 #define PR13_NEOCMD$M_LEN 0xC0000000 #define PR13$_NEDATHI 180 /* NDAL error data high (RO) */ #define PR13$_NEDATLO 182 /* NDAL error data low (RO) */ #define PR13$_NEICMD 184 /* NDAL error input command (RO) */ #define PR13_NEICMD$M_CMD 0xF #define PR13_NEICMD$M_ID 0x70 #define PR13_NEICMD$M_PARITY 0x380 #define PR13_NDAL$K_LEN_HW 0 /* Length = hexaword */ #define PR13_NDAL$K_LEN_QW 2 /* Length = quadword */ #define PR13_NDAL$K_LEN_OW 3 /* Length = octaword */ /* encoded NDAL command values */ #define PR13_NDAL$K_CMD_NOP 0 /* Command = NOP */ #define PR13_NDAL$K_CMD_WRITE 2 /* Command = Write */ #define PR13_NDAL$K_CMD_WDISOWN 3 /* Command = Write disown */ #define PR13_NDAL$K_CMD_IREAD 4 /* Command = I-read */ #define PR13_NDAL$K_CMD_DREAD 5 /* Command = D-read */ #define PR13_NDAL$K_CMD_OREAD 6 /* Command = O-read */ #define PR13_NDAL$K_CMD_RDE 9 /* Command = Read data error */ #define PR13_NDAL$K_CMD_WDATA 10 /* Command = Write data */ #define PR13_NDAL$K_CMD_BADWDATA 11 /* Command = Bad write data */ #define PR13_NDAL$K_CMD_RDR0 12 /* Command = Read data return 0 */ #define PR13_NDAL$K_CMD_RDR1 13 /* Command = Read data return 1 */ #define PR13_NDAL$K_CMD_RDR2 14 /* Command = Read data return 2 */ #define PR13_NDAL$K_CMD_RDR3 15 /* Command = Read data return 3 */ /* Cbox registers, continued */ #define PR13$_BCTAG 16777216 /* First of 64K Bcache tag IPRs (RW) */ #define PR13$_BCTAG_128KB_MAX 16908256 /* Last tag IPR for 128KB Bcache */ #define PR13$_BCTAG_256KB_MAX 17039328 /* Last tag IPR for 256KB Bcache */ #define PR13$_BCTAG_512KB_MAX 17301472 /* Last tag IPR for 512KB Bcache */ #define PR13$_BCTAG_2MB_MAX 18874336 /* Last tag IPR for 2MB Bcache */ #define PR13_BCTAG$K_IPR_INCR 32 /* Increment between Bcache tag IPR numbers */ #define PR13_BCTAG$M_VALID 0x200 #define PR13_BCTAG$M_OWNED 0x400 #define PR13_BCTAG$M_ECC 0x1F800 #define PR13_BCTAG$M_TAG 0xFFFE0000 #define PR13$_BCFLUSH 20971520 /* First of 64K Bcache tag deallocate IPRs (WO) */ #define PR13$_BCFLUSH_128KB_MAX 21102560 /* Last deallocate IPR for 128KB Bcache */ #define PR13$_BCFLUSH_256KB_MAX 21233632 /* Last deallocate IPR for 256KB Bcache */ #define PR13$_BCFLUSH_512KB_MAX 21495776 /* Last deallocate IPR for 512KB Bcache */ #define PR13$_BCFLUSH_2MB_MAX 23068640 /* Last deallocate IPR for 2MB Bcache */ #define PR13_BCFLUSH$K_IPR_INCR 32 /* Increment between Bcache deallocate IPR numbers */ /* Ibox registers. */ #define PR13$_VMAR 208 /* VIC memory address register */ #define PR13_VMAR$M_LW 0x4 #define PR13_VMAR$M_SUB_BLOCK 0x18 #define PR13_VMAR$M_ROW_INDEX 0x7E0 #define PR13_VMAR$M_ADDR 0xFFFFF800 #define PR13$_VTAG 209 /* VIC tag register */ #define PR13_VTAG$M_V 0xF #define PR13_VTAG$M_DP 0xF0 #define PR13_VTAG$M_TP 0x100 #define PR13_VTAG$M_TAG 0xFFFFF800 #define PR13$_VDATA 210 /* VIC data register */ #define PR13$_ICSR 211 /* Ibox control and status register (RW) */ #define PR13_ICSR$M_ENABLE 0x1 #define PR13_ICSR$M_LOCK 0x4 #define PR13_ICSR$M_DPERR 0x8 #define PR13_ICSR$M_TPERR 0x10 #define PR13$_BPCR 212 /* Ibox branch prediction control register */ #define PR13_BPCR$M_HISTORY 0xF #define PR13_BPCR$M_MISPREDICT 0x20 #define PR13_BPCR$M_FLUSH_BHT 0x40 #define PR13_BPCR$M_FLUSH_CTR 0x80 #define PR13_BPCR$M_LOAD_HISTORY 0x100 #define PR13_BPCR$M_BPU_ALGORITHM 0xFFFF0000 #define PR13_BPCR$K_BPU_ALGORITHM 65226 /* default value for BPU_ALGORITHM field */ #define PR13$_BPC 214 /* Ibox Backup PC (RO) */ #define PR13$_BPCUNW 215 /* Ibox Backup PC with RLOG unwind (RO) */ /* Mbox internal memory management registers. */ #define PR13$_MP0BR 224 /* Mbox P0 base register (RW) */ #define PR13$_MP0LR 225 /* Mbox P0 length register (RW) */ #define PR13$_MP1BR 226 /* Mbox P1 base register (RW) */ #define PR13$_MP1LR 227 /* Mbox P1 length register (RW) */ #define PR13$_MSBR 228 /* Mbox system base register (RW) */ #define PR13$_MSLR 229 /* Mbox system length register (RW) */ #define PR13$_MMAPEN 230 /* Mbox memory management enable (RW) */ /* Mbox registers. */ #define PR13$_PAMODE 231 /* Mbox physical address mode (RW) */ #define PR13_PAMODE$M_MODE 0x1 #define PR13_PAMODE$K_PA_30 0 /* 30-bit PA mode */ #define PR13_PAMODE$K_PA_32 1 /* 32-bit PA mode */ #define PR13$_MMEADR 232 /* Mbox memory management fault address (RO) */ #define PR13$_MMEPTE 233 /* Mbox memory management fault PTE address (RO) */ #define PR13$_MMESTS 234 /* Mbox memory management fault status (RO) */ #define PR13_MMESTS$M_LV 0x1 #define PR13_MMESTS$M_PTE_REF 0x2 #define PR13_MMESTS$M_M 0x4 #define PR13_MMESTS$M_FAULT 0xC000 #define PR13_MMESTS$K_FAULT_ACV 1 /* ACV fault */ #define PR13_MMESTS$K_FAULT_TNV 2 /* TNV fault */ #define PR13_MMESTS$K_FAULT_M0 3 /* M=0 fault */ #define PR13_MMESTS$M_SRC 0x1C000000 #define PR13_MMESTS$M_LOCK 0xE0000000 #define PR13$_TBADR 236 /* Mbox TB parity error address (RO) */ #define PR13$_TBSTS 237 /* Mbox TB parity error status (RW) */ #define PR13_TBSTS$M_LOCK 0x1 #define PR13_TBSTS$M_DPERR 0x2 #define PR13_TBSTS$M_TPERR 0x4 #define PR13_TBSTS$M_EM_VAL 0x8 #define PR13_TBSTS$M_CMD 0x1F0 #define PR13_TBSTS$M_SRC 0xE0000000 #define PR13_MSRC$K_IREF_LATCH 6 /* Source of fault was IREF latch */ #define PR13_MSRC$K_SPEC_QUEUE 4 /* Source of fault was spec queue */ #define PR13_MSRC$K_EM_LATCH 0 /* Source of fault was EM latch */ /* Mbox Pcache registers */ #define PR13$_PCADR 242 /* Mbox Pcache parity error address (RO) */ #define PR13$_PCSTS 244 /* Mbox Pcache parity error status (RW) */ #define PR13_PCSTS$M_LOCK 0x1 #define PR13_PCSTS$M_DPERR 0x2 #define PR13_PCSTS$M_RIGHT_BANK 0x4 #define PR13_PCSTS$M_LEFT_BANK 0x8 #define PR13_PCSTS$M_CMD 0x1F0 #define PR13_PCSTS$M_PTE_ER_WR 0x200 #define PR13_PCSTS$M_PTE_ER 0x400 #define PR13$_PCCTL 248 /* Mbox Pcache control (RW) */ #define PR13_PCCTL$M_D_ENABLE 0x1 #define PR13_PCCTL$M_I_ENABLE 0x2 #define PR13_PCCTL$M_FORCE_HIT 0x4 #define PR13_PCCTL$M_BANK_SEL 0x8 #define PR13_PCCTL$M_P_ENABLE 0x10 #define PR13_PCCTL$M_PMM 0xE0 #define PR13_PCCTL$M_ELEC_DISABLE 0x100 #define PR13_PCCTL$M_RED_ENABLE 0x200 #define PR13$_PCTAG 25165824 /* First of 256 Pcache tag IPRs (RW) */ #define PR13$_PCTAG_MAX 25173984 /* Last of 256 Pcache tag IPRs */ #define PR13_PCTAG$K_IPR_INCR 32 /* Increment between Pcache tag IPR numbers */ #define PR13_PCTAG$M_A 0x1 #define PR13_PCTAG$M_V 0x1E #define PR13_PCTAG$M_P 0x20 #define PR13_PCTAG$M_TAG 0xFFFFF000 #define PR13$_PCDAP 29360128 /* First of 1024 Pcache data parity IPRs (RW) */ #define PR13$_PCDAP_MAX 29368312 /* Last of 1024 Pcache data parity IPRs */ #define PR13_PCDAP$K_IPR_INCR 8 /* Increment between Pcache data parity IPR numbers */ #define PR13_PCDAP$M_DATA_PARITY 0xFF union pr13def { /* Architecturally-defined registers which have different characteristics */ /* on this CPU. */ __struct { unsigned pr13_savpsl$v_psl_lo : 8; /* Saved PSL bits <7:0> */ unsigned pr13_savpsl$v_haltcode : 6; /* Halt code containing one of the following values */ unsigned pr13_savpsl$v_invalid : 1; /* Invalid SAVPSL if = 1 */ unsigned pr13_savpsl$v_mapen : 1; /* MAPEN<0> */ unsigned pr13_savpsl$v_psl_hi : 16; /* Saved PSL bits <31:16> */ } pr13r_pr13savpsl_bits; __struct { unsigned pr13_sid$v_ucode_rev : 8; /* Microcode (chip) revision number */ unsigned pr13_sid$v_nonstandard_patch : 1; /* PCS loaded with a non-standard patch */ unsigned pr13_sid$v_patch_rev : 5; /* Patch revision number */ unsigned pr13_sid$$$_fill_1 : 10; unsigned pr13_sid$v_type : 8; /* CPU type code (19 decimal for NVAX) */ } pr13r_pr13sid_bits; /* System-level required registers. */ /* These registers are for testability and diagnostics use only. */ /* They should not be referenced in normal operation. */ __struct { /* Vector returned in response to IAK1x read */ unsigned pr13_iak$v_ipl17 : 1; /* Force IPL 17, independent of actual level */ unsigned pr13_iak$v_pr : 1; /* Passive release */ unsigned pr13_iak$v_scb_offset : 14; /* LW offset in SCB of interrupt vector */ unsigned pr13_iak$$$_fill_1 : 16; } pr13r_pr13iak_vector; /* Ebox register definition */ __struct { unsigned pr13_intsys$v_iccs6 : 1; /* ICCS<6> (RO) */ unsigned pr13_intsys$v_sisr : 15; /* SISR<15:1> (RO) */ unsigned pr13_intsys$v_int_id : 5; /* ID of highest pending interrupt (RO) */ unsigned pr13_intsys$$$_fill_1 : 3; unsigned pr13_intsys$v_int_tim_reset : 1; /* Interval timer interrupt reset (WC) */ unsigned pr13_intsys$$$_fill_2 : 2; unsigned pr13_intsys$v_s_err_reset : 1; /* Soft error interrupt reset (WC) */ unsigned pr13_intsys$v_pmon_reset : 1; /* Performance monitoring interrupt reset (WC) */ unsigned pr13_intsys$v_h_err_reset : 1; /* Hard error interrupt reset (WC) */ unsigned pr13_intsys$v_pwrfl_reset : 1; /* Power fail interrupt reset (WC) */ unsigned pr13_intsys$v_halt_reset : 1; /* Halt pin interrupt reset (WC) */ } pr13r_pr13intsys_bits; __struct { unsigned pr13_pmfcnt$v_pmctr0 : 16; /* PMCTR0 word */ unsigned pr13_pmfcnt$v_pmctr1 : 16; /* PMCTR1 word */ } pr13r_pr13pmfcnt_bits; __struct { unsigned pr13_pcscr$$$_fill_1 : 8; unsigned pr13_pcscr$v_par_port_dis : 1; /* Disable parallel port control of scan chain (RW) */ unsigned pr13_pcscr$v_pcs_enb : 1; /* Enable use of patchable control store (RW) */ unsigned pr13_pcscr$v_pcs_write : 1; /* Write scan chain to patchable control store (WO) */ unsigned pr13_pcscr$v_rwl_shift : 1; /* Shift read-write latch scan chain by one bit (WO) */ unsigned pr13_pcscr$v_data : 1; /* Data to be shifted into the PCS scan chain (RW) */ unsigned pr13_pcscr$$$_fill_2 : 10; unsigned pr13_pcscr$v_nonstandard_patch : 1; /* PCS loaded with a non-standard patch (RW) */ unsigned pr13_pcscr$v_patch_rev : 5; /* Patch revision number (RW) */ unsigned pr13_pcscr$$$_fill_3 : 3; } pr13r_pr13pcscr_bits; __struct { unsigned pr13_ecr$v_vector_present : 1; /* Vector unit present (RW) */ unsigned pr13_ecr$v_fbox_enable : 1; /* Fbox enabled (RW) */ unsigned pr13_ecr$v_timeout_ext : 1; /* Select external timebase for S3 stall timeout timer (RW) */ unsigned pr13_ecr$v_fbox_st4_bypass_ena : 1; /* Fbox stage 4 conditional bypass enable (RW) */ unsigned pr13_ecr$v_timeout_occurred : 1; /* S3 stall timeout occurred (WC) */ unsigned pr13_ecr$v_timeout_test : 1; /* Select test mode for S3 stall timeout (RW) */ unsigned pr13_ecr$v_timeout_clock : 1; /* Clock S3 timeout (RW) */ unsigned pr13_ecr$v_iccs_ext : 1; /* Full ICCS implemented in external logic (RW) */ unsigned pr13_ecr$$$_fill_1 : 5; unsigned pr13_ecr$v_fbox_test_enable : 1; /* Enable test of Fbox (RW) */ unsigned pr13_ecr$$$_fill_2 : 2; unsigned pr13_ecr$v_pmf_enable : 1; /* Performance monitoring facility enable (RW) */ unsigned pr13_ecr$v_pmf_pmux : 2; /* Performance monitoring facility master select (RW) */ unsigned pr13_ecr$v_pmf_emux : 3; /* Performance monitoring facility Ebox mux select (RW) */ unsigned pr13_ecr$v_pmf_lfsr : 1; /* Performance monitoring facility Wbus LFSR enable (RW) */ unsigned pr13_ecr$$$_fill_3 : 8; unsigned pr13_ecr$v_pmf_clear : 1; /* Clear performance monitoring hardware counters (WO) */ } pr13r_pr13ecr_bits; /* Mbox TB registers. */ /* These registers are for testability and diagnostics use only. */ /* They should not be referenced in normal operation. */ __struct { unsigned pr13_mtbtag$v_tp : 1; /* Tag parity bit */ unsigned pr13_mtbtag$$$_fill_1 : 8; unsigned pr13_mtbtag$v_vpn : 23; /* Virtual page number of address (VA<31:9>) */ } pr13r_pr13mtbtag_bits; __struct { /* Format is normal PTE format, except for PTE parity bit */ unsigned pr13_mtbpte$v_pfn : 23; /* Page frame number (PA<31:9>) */ unsigned pr13_mtbpte$$$_fill_1 : 1; unsigned pr13_mtbpte$v_p : 1; /* PTE parity */ unsigned pr13_mtbpte$$$_fill_2 : 1; unsigned pr13_mtbpte$v_m : 1; /* Modify bit */ unsigned pr13_mtbpte$v_prot : 2; /* Protection field */ unsigned pr13_mtbpte$v_v : 1; /* PTE valid bit */ unsigned pr13_mtbpte$v_fill_103 : 2; } pr13r_pr13mtbpte_bits; /* Vector architecture registers */ __struct { unsigned pr13_vpsr$v_ven : 1; /* Vector processor enabled (RW) */ unsigned pr13_vpsr$v_rst : 1; /* Vector processor state reset (WO) */ unsigned pr13_vpsr$$$_fill_1 : 5; unsigned pr13_vpsr$v_aex : 1; /* Vector arithmetic exception (WC) */ unsigned pr13_vpsr$$$_fill_2 : 16; unsigned pr13_vpsr$v_imp : 1; /* Implementation-specific hardware error (WC) */ unsigned pr13_vpsr$$$_fill_3 : 6; unsigned pr13_vpsr$v_bsy : 1; /* Vector processor busy (RO) */ } pr13r_pr13vpsr_bits; __struct { unsigned pr13_vaer$v_f_undf : 1; /* Floating underflow */ unsigned pr13_vaer$v_f_divz : 1; /* Floating divide-by-zero */ unsigned pr13_vaer$v_f_ropr : 1; /* Floating reserved operand */ unsigned pr13_vaer$v_f_ovfl : 1; /* Floating overflow */ unsigned pr13_vaer$$$_fill_1 : 1; unsigned pr13_vaer$v_i_ovfl : 1; /* Integer overflow */ unsigned pr13_vaer$$$_fill_2 : 10; unsigned pr13_vaer$v_register_mask : 16; /* Vector destination register mask */ } pr13r_pr13vaer_bits; __struct { unsigned pr13_cctl$v_enable : 1; /* Enable Bcache (RW) */ unsigned pr13_cctl$v_tag_speed : 1; /* Tag RAM speed (RW) */ unsigned pr13_cctl$v_data_speed : 2; /* Data RAM speed (RW) */ unsigned pr13_cctl$v_size : 2; /* Bcache size (RW) */ unsigned pr13_cctl$v_force_hit : 1; /* Force Bcache hit (RW) */ unsigned pr13_cctl$v_disable_errors : 1; /* Disable Bcache ECC errors (RW) */ unsigned pr13_cctl$v_sw_ecc : 1; /* Enable use of software ECC (RW) */ unsigned pr13_cctl$v_timeout_test : 1; /* Enable test of Cbox read timeout counters (RW) */ unsigned pr13_cctl$v_disable_pack : 1; /* Disable write packing (RW) */ unsigned pr13_cctl$v_pm_access_type : 3; /* Performance monitoring access type (RW) */ unsigned pr13_cctl$v_pm_hit_type : 2; /* Performance monitoring hit type (RW) */ unsigned pr13_cctl$v_force_ndal_perr : 1; /* Forces 1 parity error on the NDAL, on next outgoing transaction */ unsigned pr13_cctl$$$_fill_1 : 13; unsigned pr13_cctl$v_sw_etm : 1; /* Enter software error transition mode (RW) */ unsigned pr13_cctl$v_hw_etm : 1; /* Error transition mode entered due to error (WC) */ } pr13r_pr13cctl_bits; __struct { unsigned pr13_bcdecc$$$_fill_1 : 6; unsigned pr13_bcdecc$v_ecclo : 4; /* ECC check bits <3:0> */ unsigned pr13_bcdecc$$$_fill_2 : 12; unsigned pr13_bcdecc$v_ecchi : 4; /* ECC check bits <7:4> */ unsigned pr13_bcdecc$$$_fill_3 : 6; } pr13r_pr13bcdecc_bits; /* Cbox registers, continued */ __struct { unsigned pr13_bcetsts$v_lock : 1; /* Tag store registers are locked due to an error (WC) */ unsigned pr13_bcetsts$v_corr : 1; /* Correctable error occurred (WC) */ unsigned pr13_bcetsts$v_uncorr : 1; /* Uncorrectable error occurred (WC) */ unsigned pr13_bcetsts$v_bad_addr : 1; /* Addressing error occurred (WC) */ unsigned pr13_bcetsts$v_lost_err : 1; /* Error occured while register was locked (WC) */ unsigned pr13_bcetsts$v_ts_cmd : 5; /* Tag store command which caused error (RO) */ unsigned pr13_bcetsts$$$_fill_1 : 22; } pr13r_pr13bcetsts_bits; __struct { unsigned pr13_bcetag$$$_fill_1 : 9; unsigned pr13_bcetag$v_valid : 1; /* Valid bit */ unsigned pr13_bcetag$v_owned : 1; /* Ownership bit */ unsigned pr13_bcetag$v_ecc : 6; /* ECC bits */ unsigned pr13_bcetag$v_tag : 15; /* tag data */ } pr13r_pr13bcetag_bits; /* Cbox registers, continued */ __struct { unsigned pr13_bcedsts$v_lock : 1; /* Data RAM registers are locked due to an error (WC) */ unsigned pr13_bcedsts$v_corr : 1; /* Correctable ECC error occurred (WC) */ unsigned pr13_bcedsts$v_uncorr : 1; /* Uncorrectable ECC error occurred (WC) */ unsigned pr13_bcedsts$v_bad_addr : 1; /* Addressing error occurred (WC) */ unsigned pr13_bcedsts$v_lost_err : 1; /* Error occurred while register was locked (WC) */ unsigned pr13_bcedsts$$$_fill_1 : 3; unsigned pr13_bcedsts$v_dr_cmd : 4; /* Data RAM command which caused error (RO) */ unsigned pr13_bcedsts$$$_fill_2 : 20; } pr13r_pr13bcedsts_bits; __struct { unsigned pr13_bcedecc$$$_fill_1 : 6; unsigned pr13_bcedecc$v_ecclo : 4; /* Bcache data ECC syndrome bits <3:0> */ unsigned pr13_bcedecc$$$_fill_2 : 12; unsigned pr13_bcedecc$v_ecchi : 4; /* Bcache data ECC syndrome bits <7:4> */ unsigned pr13_bcedecc$$$_fill_3 : 6; } pr13r_pr13bcedecc_bits; /* Cbox registers, continued */ __struct { unsigned pr13_cefsts$v_rdlk : 1; /* Error occurred during a read lock (WC) */ unsigned pr13_cefsts$v_lock : 1; /* CEFSTS & CEFADR registers are locked due to an error (WC) */ unsigned pr13_cefsts$v_timeout : 1; /* Fill failed due to transaction timeout (WC) */ unsigned pr13_cefsts$v_rde : 1; /* Fill failed due to Read Data Error (WC) */ unsigned pr13_cefsts$v_lost_err : 1; /* Error occurred while register was locked (WC) */ unsigned pr13_cefsts$v_id0 : 1; /* NDAL id<0> for failed read (RO) */ unsigned pr13_cefsts$v_iread : 1; /* Error occured during an IREAD (RO) */ unsigned pr13_cefsts$v_oread : 1; /* Error occurred during an OREAD (RO) */ unsigned pr13_cefsts$v_write : 1; /* Error occurred during a write (RO) */ unsigned pr13_cefsts$v_to_mbox : 1; /* Data was destined for the Mbox (RO) */ unsigned pr13_cefsts$v_rip : 1; /* READ invalidate was pending (RO) */ unsigned pr13_cefsts$v_oip : 1; /* OREAD invalidate was pending (RO) */ unsigned pr13_cefsts$v_dnf : 1; /* Data was not to be validated when fill completed (RO) */ unsigned pr13_cefsts$v_rdlk_fl_done : 1; /* Last fill for read lock received (RO) */ unsigned pr13_cefsts$v_req_fill_done : 1; /* Requested fill quadword was received for this read. */ unsigned pr13_cefsts$v_count : 2; /* Number of requested QW of fill received (RO) */ unsigned pr13_cefsts$$$_fill_1 : 4; unsigned pr13_cefsts$v_unexpected_fill : 1; /* RDE or RDR was received from the NDAL when fill_cam not valid (WC) */ unsigned pr13_cefsts$$$_fill_2 : 10; } pr13r_pr13cefsts_bits; /* Cbox registers, continued */ __struct { unsigned pr13_nests$v_noack : 1; /* Outgoing command was NACKed (WC) */ unsigned pr13_nests$v_badwdata : 1; /* BADWDATA cycle transmitted (WC) */ unsigned pr13_nests$v_lost_oerr : 1; /* Outgoing error was lost while register was locked (WC) */ unsigned pr13_nests$v_perr : 1; /* NDAL parity error detected (WC) */ unsigned pr13_nests$v_incon_perr : 1; /* Inconsistent parity error (parity error detected on */ unsigned pr13_nests$v_lost_perr : 1; /* NDAL parity error detected while register was locked (WC) */ /* ACKed transaction) (WC) */ unsigned pr13_nests$$$_fill_1 : 26; } pr13r_pr13nests_bits; __struct { unsigned pr13_neocmd$v_cmd : 4; /* NDAL command on outgoing error transaction (see below) */ unsigned pr13_neocmd$v_id : 3; /* NDAL ID on outgoing error transaction */ unsigned pr13_neocmd$$$_fill_1 : 1; unsigned pr13_neocmd$v_byte_en : 8; /* Byte enables on outgoing error transaction */ unsigned pr13_neocmd$$$_fill_2 : 14; unsigned pr13_neocmd$v_len : 2; /* Length on outgoing error transaction (see below) */ } pr13r_pr13neocmd_bits; __struct { unsigned pr13_neicmd$v_cmd : 4; /* NDAL command received on error transaction (see below) */ unsigned pr13_neicmd$v_id : 3; /* NDAL ID received error on transaction */ unsigned pr13_neicmd$v_parity : 3; /* NDAL parity bits received error on transaction */ unsigned pr13_neicmd$$$_fill_1 : 22; } pr13r_pr13neicmd_bits; /* Encoded NDAL length values */ __struct { unsigned pr13_bctag$$$_fill_1 : 9; unsigned pr13_bctag$v_valid : 1; /* Valid bit (RW) */ unsigned pr13_bctag$v_owned : 1; /* Ownership bit (RW) */ unsigned pr13_bctag$v_ecc : 6; /* ECC bits (RW) */ unsigned pr13_bctag$v_tag : 15; /* tag data (RW) */ } pr13r_pr13bctag_bits; __struct { unsigned pr13_vmar$$$_fill_1 : 2; unsigned pr13_vmar$v_lw : 1; /* longword within quadword */ unsigned pr13_vmar$v_sub_block : 2; /* sub-block indicator */ unsigned pr13_vmar$v_row_index : 6; /* cache row index */ unsigned pr13_vmar$v_addr : 21; /* error address */ } pr13r_pr13vmar_bits; __struct { unsigned pr13_vtag$v_v : 4; /* data valid bits */ unsigned pr13_vtag$v_dp : 4; /* data parity bits */ unsigned pr13_vtag$v_tp : 1; /* tag parity bit */ unsigned pr13_vtag$$$_fill_1 : 2; /* unused bits (zero) */ unsigned pr13_vtag$v_tag : 21; /* tag */ } pr13r_pr13vtag_bits; __struct { unsigned pr13_icsr$v_enable : 1; /* VIC enable bit (RW) */ unsigned pr13_icsr$$$_fill_1 : 1; unsigned pr13_icsr$v_lock : 1; /* Register is locked due to an error (WC) */ unsigned pr13_icsr$v_dperr : 1; /* Data parity error (RO) */ unsigned pr13_icsr$v_tperr : 1; /* Tag parity error (RO) */ unsigned pr13_icsr$$$_fill_2 : 27; } pr13r_pr13icsr_bits; __struct { unsigned pr13_bpcr$v_history : 4; /* branch history bits */ unsigned pr13_bpcr$$$_fill_1 : 1; unsigned pr13_bpcr$v_mispredict : 1; /* history of last branch */ unsigned pr13_bpcr$v_flush_bht : 1; /* flush branch history table */ unsigned pr13_bpcr$v_flush_ctr : 1; /* flush branch hist addr counter */ unsigned pr13_bpcr$v_load_history : 1; /* write new history to array */ unsigned pr13_bpcr$$$_fill_2 : 7; /* unused bits (must be zero) */ unsigned pr13_bpcr$v_bpu_algorithm : 16; /* branch prediction algorithm */ } pr13r_pr13bpcr_bits; /* The following two registers are for testability and diagnostics use only. */ /* They should not be referenced in normal operation. */ /* These registers are for testability and diagnostics use only. */ /* In normal operation, the equivalent architecturally-defined registers */ /* should be used instead. */ __struct { unsigned pr13_pamode$v_mode : 1; /* Addressing mode(1 = 32bit addressing) (RW) */ unsigned pr13_pamode$$$_fill_1 : 31; } pr13r_pr13pamode_bits; __struct { unsigned pr13_mmests$v_lv : 1; /* ACV fault due to length violation */ unsigned pr13_mmests$v_pte_ref : 1; /* ACV/TNV fault occurred on PPTE reference */ unsigned pr13_mmests$v_m : 1; /* Reference had write or modify intent */ unsigned pr13_mmests$$$_fill_1 : 11; unsigned pr13_mmests$v_fault : 2; /* Fault type, one of the following: */ unsigned pr13_mmests$$$_fill_2 : 10; unsigned pr13_mmests$v_src : 3; /* Shadow copy of LOCK bits (see MSRC$ constants below) */ unsigned pr13_mmests$v_lock : 3; /* Lock status (see MSRC$ constant below) */ } pr13r_pr13mmests_bits; __struct { unsigned pr13_tbsts$v_lock : 1; /* Register is locked due to an error (WC) */ unsigned pr13_tbsts$v_dperr : 1; /* Data parity error (RO) */ unsigned pr13_tbsts$v_tperr : 1; /* Tag parity error (RO) */ unsigned pr13_tbsts$v_em_val : 1; /* EM latch was valid when error occurred (RO) */ unsigned pr13_tbsts$v_cmd : 5; /* S5 command when TB parity error occured (RO) */ unsigned pr13_tbsts$$$_fill_1 : 20; unsigned pr13_tbsts$v_src : 3; /* Source of original refernce (see MSRC$ constants below) (RO) */ } pr13r_pr13tbsts_bits; __struct { unsigned pr13_pcsts$v_lock : 1; /* Register is locked due to an error (WC) */ unsigned pr13_pcsts$v_dperr : 1; /* Data parity error occurred (RO) */ unsigned pr13_pcsts$v_right_bank : 1; /* Right bank tag parity error occurred (RO) */ unsigned pr13_pcsts$v_left_bank : 1; /* Left bank tag parity error occurred (RO) */ unsigned pr13_pcsts$v_cmd : 5; /* S6 command when Pcache parity error occured (RO) */ unsigned pr13_pcsts$v_pte_er_wr : 1; /* Hard error on PTE DREAD occurred (orig ref was WRITE) (WC) */ unsigned pr13_pcsts$v_pte_er : 1; /* Hard error on PTE DREAD occurred (WC) */ unsigned pr13_pcsts$$$_fill_1 : 21; } pr13r_pr13pcsts_bits; __struct { unsigned pr13_pcctl$v_d_enable : 1; /* Enable for invalidate, D-stream read/write/fill (RW) */ unsigned pr13_pcctl$v_i_enable : 1; /* Enable for invalidate, I-stream read/fill (RW) */ unsigned pr13_pcctl$v_force_hit : 1; /* Enable force hit on Pcache references (RW) */ unsigned pr13_pcctl$v_bank_sel : 1; /* Select left bank if 0, right bank if 1 (RW) */ unsigned pr13_pcctl$v_p_enable : 1; /* Enable parity checking (RW) */ unsigned pr13_pcctl$v_pmm : 3; /* Mbox performance monitor mode (RW) */ unsigned pr13_pcctl$v_elec_disable : 1; /* Pcache electrical disable bit (RW) */ unsigned pr13_pcctl$v_red_enable : 1; /* Redundancy enable bit (RO) */ unsigned pr13_pcctl$$$_fill_1 : 22; } pr13r_pr13pcctl_bits; __struct { unsigned pr13_pctag$v_a : 1; /* Allocation bit corresponding to index of this tag (RW) */ unsigned pr13_pctag$v_v : 4; /* Valid bits corresponding to the 4 data subblocks (RW) */ unsigned pr13_pctag$v_p : 1; /* Tag parity (RW) */ unsigned pr13_pctag$$$_fill_1 : 6; unsigned pr13_pctag$v_tag : 20; /* Tag bits (RW) */ } pr13r_pr13pctag_bits; __struct { unsigned pr13_pcdap$v_data_parity : 8; /* Even byte parity for the addressed quadword (RW) */ unsigned pr13_pcdap$$$_fill_1 : 24; } pr13r_pr13pcdap_bits; } ; #if !defined(__VAXC) && !defined(VAXC) #define pr13_savpsl$v_psl_lo pr13r_pr13savpsl_bits.pr13_savpsl$v_psl_lo #define pr13_savpsl$v_haltcode pr13r_pr13savpsl_bits.pr13_savpsl$v_haltcode #define pr13_savpsl$v_invalid pr13r_pr13savpsl_bits.pr13_savpsl$v_invalid #define pr13_savpsl$v_mapen pr13r_pr13savpsl_bits.pr13_savpsl$v_mapen #define pr13_savpsl$v_psl_hi pr13r_pr13savpsl_bits.pr13_savpsl$v_psl_hi #define pr13_sid$v_ucode_rev pr13r_pr13sid_bits.pr13_sid$v_ucode_rev #define pr13_sid$v_nonstandard_patch pr13r_pr13sid_bits.pr13_sid$v_nonstandard_patch #define pr13_sid$v_patch_rev pr13r_pr13sid_bits.pr13_sid$v_patch_rev #define pr13_sid$v_type pr13r_pr13sid_bits.pr13_sid$v_type #define pr13_iak$v_ipl17 pr13r_pr13iak_vector.pr13_iak$v_ipl17 #define pr13_iak$v_pr pr13r_pr13iak_vector.pr13_iak$v_pr #define pr13_iak$v_scb_offset pr13r_pr13iak_vector.pr13_iak$v_scb_offset #define pr13_intsys$v_iccs6 pr13r_pr13intsys_bits.pr13_intsys$v_iccs6 #define pr13_intsys$v_sisr pr13r_pr13intsys_bits.pr13_intsys$v_sisr #define pr13_intsys$v_int_id pr13r_pr13intsys_bits.pr13_intsys$v_int_id #define pr13_intsys$v_int_tim_reset pr13r_pr13intsys_bits.pr13_intsys$v_int_tim_reset #define pr13_intsys$v_s_err_reset pr13r_pr13intsys_bits.pr13_intsys$v_s_err_reset #define pr13_intsys$v_pmon_reset pr13r_pr13intsys_bits.pr13_intsys$v_pmon_reset #define pr13_intsys$v_h_err_reset pr13r_pr13intsys_bits.pr13_intsys$v_h_err_reset #define pr13_intsys$v_pwrfl_reset pr13r_pr13intsys_bits.pr13_intsys$v_pwrfl_reset #define pr13_intsys$v_halt_reset pr13r_pr13intsys_bits.pr13_intsys$v_halt_reset #define pr13_pmfcnt$v_pmctr0 pr13r_pr13pmfcnt_bits.pr13_pmfcnt$v_pmctr0 #define pr13_pmfcnt$v_pmctr1 pr13r_pr13pmfcnt_bits.pr13_pmfcnt$v_pmctr1 #define pr13_pcscr$v_par_port_dis pr13r_pr13pcscr_bits.pr13_pcscr$v_par_port_dis #define pr13_pcscr$v_pcs_enb pr13r_pr13pcscr_bits.pr13_pcscr$v_pcs_enb #define pr13_pcscr$v_pcs_write pr13r_pr13pcscr_bits.pr13_pcscr$v_pcs_write #define pr13_pcscr$v_rwl_shift pr13r_pr13pcscr_bits.pr13_pcscr$v_rwl_shift #define pr13_pcscr$v_data pr13r_pr13pcscr_bits.pr13_pcscr$v_data #define pr13_pcscr$v_nonstandard_patch pr13r_pr13pcscr_bits.pr13_pcscr$v_nonstandard_patch #define pr13_pcscr$v_patch_rev pr13r_pr13pcscr_bits.pr13_pcscr$v_patch_rev #define pr13_ecr$v_vector_present pr13r_pr13ecr_bits.pr13_ecr$v_vector_present #define pr13_ecr$v_fbox_enable pr13r_pr13ecr_bits.pr13_ecr$v_fbox_enable #define pr13_ecr$v_timeout_ext pr13r_pr13ecr_bits.pr13_ecr$v_timeout_ext #define pr13_ecr$v_fbox_st4_bypass_ena pr13r_pr13ecr_bits.pr13_ecr$v_fbox_st4_bypass_ena #define pr13_ecr$v_timeout_occurred pr13r_pr13ecr_bits.pr13_ecr$v_timeout_occurred #define pr13_ecr$v_timeout_test pr13r_pr13ecr_bits.pr13_ecr$v_timeout_test #define pr13_ecr$v_timeout_clock pr13r_pr13ecr_bits.pr13_ecr$v_timeout_clock #define pr13_ecr$v_iccs_ext pr13r_pr13ecr_bits.pr13_ecr$v_iccs_ext #define pr13_ecr$v_fbox_test_enable pr13r_pr13ecr_bits.pr13_ecr$v_fbox_test_enable #define pr13_ecr$v_pmf_enable pr13r_pr13ecr_bits.pr13_ecr$v_pmf_enable #define pr13_ecr$v_pmf_pmux pr13r_pr13ecr_bits.pr13_ecr$v_pmf_pmux #define pr13_ecr$v_pmf_emux pr13r_pr13ecr_bits.pr13_ecr$v_pmf_emux #define pr13_ecr$v_pmf_lfsr pr13r_pr13ecr_bits.pr13_ecr$v_pmf_lfsr #define pr13_ecr$v_pmf_clear pr13r_pr13ecr_bits.pr13_ecr$v_pmf_clear #define pr13_mtbtag$v_tp pr13r_pr13mtbtag_bits.pr13_mtbtag$v_tp #define pr13_mtbtag$v_vpn pr13r_pr13mtbtag_bits.pr13_mtbtag$v_vpn #define pr13_mtbpte$v_pfn pr13r_pr13mtbpte_bits.pr13_mtbpte$v_pfn #define pr13_mtbpte$v_p pr13r_pr13mtbpte_bits.pr13_mtbpte$v_p #define pr13_mtbpte$v_m pr13r_pr13mtbpte_bits.pr13_mtbpte$v_m #define pr13_mtbpte$v_prot pr13r_pr13mtbpte_bits.pr13_mtbpte$v_prot #define pr13_mtbpte$v_v pr13r_pr13mtbpte_bits.pr13_mtbpte$v_v #define pr13_vpsr$v_ven pr13r_pr13vpsr_bits.pr13_vpsr$v_ven #define pr13_vpsr$v_rst pr13r_pr13vpsr_bits.pr13_vpsr$v_rst #define pr13_vpsr$v_aex pr13r_pr13vpsr_bits.pr13_vpsr$v_aex #define pr13_vpsr$v_imp pr13r_pr13vpsr_bits.pr13_vpsr$v_imp #define pr13_vpsr$v_bsy pr13r_pr13vpsr_bits.pr13_vpsr$v_bsy #define pr13_vaer$v_f_undf pr13r_pr13vaer_bits.pr13_vaer$v_f_undf #define pr13_vaer$v_f_divz pr13r_pr13vaer_bits.pr13_vaer$v_f_divz #define pr13_vaer$v_f_ropr pr13r_pr13vaer_bits.pr13_vaer$v_f_ropr #define pr13_vaer$v_f_ovfl pr13r_pr13vaer_bits.pr13_vaer$v_f_ovfl #define pr13_vaer$v_i_ovfl pr13r_pr13vaer_bits.pr13_vaer$v_i_ovfl #define pr13_vaer$v_register_mask pr13r_pr13vaer_bits.pr13_vaer$v_register_mask #define pr13_cctl$v_enable pr13r_pr13cctl_bits.pr13_cctl$v_enable #define pr13_cctl$v_tag_speed pr13r_pr13cctl_bits.pr13_cctl$v_tag_speed #define pr13_cctl$v_data_speed pr13r_pr13cctl_bits.pr13_cctl$v_data_speed #define pr13_cctl$v_size pr13r_pr13cctl_bits.pr13_cctl$v_size #define pr13_cctl$v_force_hit pr13r_pr13cctl_bits.pr13_cctl$v_force_hit #define pr13_cctl$v_disable_errors pr13r_pr13cctl_bits.pr13_cctl$v_disable_errors #define pr13_cctl$v_sw_ecc pr13r_pr13cctl_bits.pr13_cctl$v_sw_ecc #define pr13_cctl$v_timeout_test pr13r_pr13cctl_bits.pr13_cctl$v_timeout_test #define pr13_cctl$v_disable_pack pr13r_pr13cctl_bits.pr13_cctl$v_disable_pack #define pr13_cctl$v_pm_access_type pr13r_pr13cctl_bits.pr13_cctl$v_pm_access_type #define pr13_cctl$v_pm_hit_type pr13r_pr13cctl_bits.pr13_cctl$v_pm_hit_type #define pr13_cctl$v_force_ndal_perr pr13r_pr13cctl_bits.pr13_cctl$v_force_ndal_perr #define pr13_cctl$v_sw_etm pr13r_pr13cctl_bits.pr13_cctl$v_sw_etm #define pr13_cctl$v_hw_etm pr13r_pr13cctl_bits.pr13_cctl$v_hw_etm #define pr13_bcdecc$v_ecclo pr13r_pr13bcdecc_bits.pr13_bcdecc$v_ecclo #define pr13_bcdecc$v_ecchi pr13r_pr13bcdecc_bits.pr13_bcdecc$v_ecchi #define pr13_bcetsts$v_lock pr13r_pr13bcetsts_bits.pr13_bcetsts$v_lock #define pr13_bcetsts$v_corr pr13r_pr13bcetsts_bits.pr13_bcetsts$v_corr #define pr13_bcetsts$v_uncorr pr13r_pr13bcetsts_bits.pr13_bcetsts$v_uncorr #define pr13_bcetsts$v_bad_addr pr13r_pr13bcetsts_bits.pr13_bcetsts$v_bad_addr #define pr13_bcetsts$v_lost_err pr13r_pr13bcetsts_bits.pr13_bcetsts$v_lost_err #define pr13_bcetsts$v_ts_cmd pr13r_pr13bcetsts_bits.pr13_bcetsts$v_ts_cmd #define pr13_bcetag$v_valid pr13r_pr13bcetag_bits.pr13_bcetag$v_valid #define pr13_bcetag$v_owned pr13r_pr13bcetag_bits.pr13_bcetag$v_owned #define pr13_bcetag$v_ecc pr13r_pr13bcetag_bits.pr13_bcetag$v_ecc #define pr13_bcetag$v_tag pr13r_pr13bcetag_bits.pr13_bcetag$v_tag #define pr13_bcedsts$v_lock pr13r_pr13bcedsts_bits.pr13_bcedsts$v_lock #define pr13_bcedsts$v_corr pr13r_pr13bcedsts_bits.pr13_bcedsts$v_corr #define pr13_bcedsts$v_uncorr pr13r_pr13bcedsts_bits.pr13_bcedsts$v_uncorr #define pr13_bcedsts$v_bad_addr pr13r_pr13bcedsts_bits.pr13_bcedsts$v_bad_addr #define pr13_bcedsts$v_lost_err pr13r_pr13bcedsts_bits.pr13_bcedsts$v_lost_err #define pr13_bcedsts$v_dr_cmd pr13r_pr13bcedsts_bits.pr13_bcedsts$v_dr_cmd #define pr13_bcedecc$v_ecclo pr13r_pr13bcedecc_bits.pr13_bcedecc$v_ecclo #define pr13_bcedecc$v_ecchi pr13r_pr13bcedecc_bits.pr13_bcedecc$v_ecchi #define pr13_cefsts$v_rdlk pr13r_pr13cefsts_bits.pr13_cefsts$v_rdlk #define pr13_cefsts$v_lock pr13r_pr13cefsts_bits.pr13_cefsts$v_lock #define pr13_cefsts$v_timeout pr13r_pr13cefsts_bits.pr13_cefsts$v_timeout #define pr13_cefsts$v_rde pr13r_pr13cefsts_bits.pr13_cefsts$v_rde #define pr13_cefsts$v_lost_err pr13r_pr13cefsts_bits.pr13_cefsts$v_lost_err #define pr13_cefsts$v_id0 pr13r_pr13cefsts_bits.pr13_cefsts$v_id0 #define pr13_cefsts$v_iread pr13r_pr13cefsts_bits.pr13_cefsts$v_iread #define pr13_cefsts$v_oread pr13r_pr13cefsts_bits.pr13_cefsts$v_oread #define pr13_cefsts$v_write pr13r_pr13cefsts_bits.pr13_cefsts$v_write #define pr13_cefsts$v_to_mbox pr13r_pr13cefsts_bits.pr13_cefsts$v_to_mbox #define pr13_cefsts$v_rip pr13r_pr13cefsts_bits.pr13_cefsts$v_rip #define pr13_cefsts$v_oip pr13r_pr13cefsts_bits.pr13_cefsts$v_oip #define pr13_cefsts$v_dnf pr13r_pr13cefsts_bits.pr13_cefsts$v_dnf #define pr13_cefsts$v_rdlk_fl_done pr13r_pr13cefsts_bits.pr13_cefsts$v_rdlk_fl_done #define pr13_cefsts$v_req_fill_done pr13r_pr13cefsts_bits.pr13_cefsts$v_req_fill_done #define pr13_cefsts$v_count pr13r_pr13cefsts_bits.pr13_cefsts$v_count #define pr13_cefsts$v_unexpected_fill pr13r_pr13cefsts_bits.pr13_cefsts$v_unexpected_fill #define pr13_nests$v_noack pr13r_pr13nests_bits.pr13_nests$v_noack #define pr13_nests$v_badwdata pr13r_pr13nests_bits.pr13_nests$v_badwdata #define pr13_nests$v_lost_oerr pr13r_pr13nests_bits.pr13_nests$v_lost_oerr #define pr13_nests$v_perr pr13r_pr13nests_bits.pr13_nests$v_perr #define pr13_nests$v_incon_perr pr13r_pr13nests_bits.pr13_nests$v_incon_perr #define pr13_nests$v_lost_perr pr13r_pr13nests_bits.pr13_nests$v_lost_perr #define pr13_neocmd$v_cmd pr13r_pr13neocmd_bits.pr13_neocmd$v_cmd #define pr13_neocmd$v_id pr13r_pr13neocmd_bits.pr13_neocmd$v_id #define pr13_neocmd$v_byte_en pr13r_pr13neocmd_bits.pr13_neocmd$v_byte_en #define pr13_neocmd$v_len pr13r_pr13neocmd_bits.pr13_neocmd$v_len #define pr13_neicmd$v_cmd pr13r_pr13neicmd_bits.pr13_neicmd$v_cmd #define pr13_neicmd$v_id pr13r_pr13neicmd_bits.pr13_neicmd$v_id #define pr13_neicmd$v_parity pr13r_pr13neicmd_bits.pr13_neicmd$v_parity #define pr13_bctag$v_valid pr13r_pr13bctag_bits.pr13_bctag$v_valid #define pr13_bctag$v_owned pr13r_pr13bctag_bits.pr13_bctag$v_owned #define pr13_bctag$v_ecc pr13r_pr13bctag_bits.pr13_bctag$v_ecc #define pr13_bctag$v_tag pr13r_pr13bctag_bits.pr13_bctag$v_tag #define pr13_vmar$v_lw pr13r_pr13vmar_bits.pr13_vmar$v_lw #define pr13_vmar$v_sub_block pr13r_pr13vmar_bits.pr13_vmar$v_sub_block #define pr13_vmar$v_row_index pr13r_pr13vmar_bits.pr13_vmar$v_row_index #define pr13_vmar$v_addr pr13r_pr13vmar_bits.pr13_vmar$v_addr #define pr13_vtag$v_v pr13r_pr13vtag_bits.pr13_vtag$v_v #define pr13_vtag$v_dp pr13r_pr13vtag_bits.pr13_vtag$v_dp #define pr13_vtag$v_tp pr13r_pr13vtag_bits.pr13_vtag$v_tp #define pr13_vtag$v_tag pr13r_pr13vtag_bits.pr13_vtag$v_tag #define pr13_icsr$v_enable pr13r_pr13icsr_bits.pr13_icsr$v_enable #define pr13_icsr$v_lock pr13r_pr13icsr_bits.pr13_icsr$v_lock #define pr13_icsr$v_dperr pr13r_pr13icsr_bits.pr13_icsr$v_dperr #define pr13_icsr$v_tperr pr13r_pr13icsr_bits.pr13_icsr$v_tperr #define pr13_bpcr$v_history pr13r_pr13bpcr_bits.pr13_bpcr$v_history #define pr13_bpcr$v_mispredict pr13r_pr13bpcr_bits.pr13_bpcr$v_mispredict #define pr13_bpcr$v_flush_bht pr13r_pr13bpcr_bits.pr13_bpcr$v_flush_bht #define pr13_bpcr$v_flush_ctr pr13r_pr13bpcr_bits.pr13_bpcr$v_flush_ctr #define pr13_bpcr$v_load_history pr13r_pr13bpcr_bits.pr13_bpcr$v_load_history #define pr13_bpcr$v_bpu_algorithm pr13r_pr13bpcr_bits.pr13_bpcr$v_bpu_algorithm #define pr13_pamode$v_mode pr13r_pr13pamode_bits.pr13_pamode$v_mode #define pr13_mmests$v_lv pr13r_pr13mmests_bits.pr13_mmests$v_lv #define pr13_mmests$v_pte_ref pr13r_pr13mmests_bits.pr13_mmests$v_pte_ref #define pr13_mmests$v_m pr13r_pr13mmests_bits.pr13_mmests$v_m #define pr13_mmests$v_fault pr13r_pr13mmests_bits.pr13_mmests$v_fault #define pr13_mmests$v_src pr13r_pr13mmests_bits.pr13_mmests$v_src #define pr13_mmests$v_lock pr13r_pr13mmests_bits.pr13_mmests$v_lock #define pr13_tbsts$v_lock pr13r_pr13tbsts_bits.pr13_tbsts$v_lock #define pr13_tbsts$v_dperr pr13r_pr13tbsts_bits.pr13_tbsts$v_dperr #define pr13_tbsts$v_tperr pr13r_pr13tbsts_bits.pr13_tbsts$v_tperr #define pr13_tbsts$v_em_val pr13r_pr13tbsts_bits.pr13_tbsts$v_em_val #define pr13_tbsts$v_cmd pr13r_pr13tbsts_bits.pr13_tbsts$v_cmd #define pr13_tbsts$v_src pr13r_pr13tbsts_bits.pr13_tbsts$v_src #define pr13_pcsts$v_lock pr13r_pr13pcsts_bits.pr13_pcsts$v_lock #define pr13_pcsts$v_dperr pr13r_pr13pcsts_bits.pr13_pcsts$v_dperr #define pr13_pcsts$v_right_bank pr13r_pr13pcsts_bits.pr13_pcsts$v_right_bank #define pr13_pcsts$v_left_bank pr13r_pr13pcsts_bits.pr13_pcsts$v_left_bank #define pr13_pcsts$v_cmd pr13r_pr13pcsts_bits.pr13_pcsts$v_cmd #define pr13_pcsts$v_pte_er_wr pr13r_pr13pcsts_bits.pr13_pcsts$v_pte_er_wr #define pr13_pcsts$v_pte_er pr13r_pr13pcsts_bits.pr13_pcsts$v_pte_er #define pr13_pcctl$v_d_enable pr13r_pr13pcctl_bits.pr13_pcctl$v_d_enable #define pr13_pcctl$v_i_enable pr13r_pr13pcctl_bits.pr13_pcctl$v_i_enable #define pr13_pcctl$v_force_hit pr13r_pr13pcctl_bits.pr13_pcctl$v_force_hit #define pr13_pcctl$v_bank_sel pr13r_pr13pcctl_bits.pr13_pcctl$v_bank_sel #define pr13_pcctl$v_p_enable pr13r_pr13pcctl_bits.pr13_pcctl$v_p_enable #define pr13_pcctl$v_pmm pr13r_pr13pcctl_bits.pr13_pcctl$v_pmm #define pr13_pcctl$v_elec_disable pr13r_pr13pcctl_bits.pr13_pcctl$v_elec_disable #define pr13_pcctl$v_red_enable pr13r_pr13pcctl_bits.pr13_pcctl$v_red_enable #define pr13_pctag$v_a pr13r_pr13pctag_bits.pr13_pctag$v_a #define pr13_pctag$v_v pr13r_pr13pctag_bits.pr13_pctag$v_v #define pr13_pctag$v_p pr13r_pr13pctag_bits.pr13_pctag$v_p #define pr13_pctag$v_tag pr13r_pr13pctag_bits.pr13_pctag$v_tag #define pr13_pcdap$v_data_parity pr13r_pr13pcdap_bits.pr13_pcdap$v_data_parity #endif /* #if !defined(__VAXC) && !defined(VAXC) */ #ifdef __cplusplus } #endif #pragma standard #endif /* __PR13DEF_LOADED */