/********************************************************************************************************************************/ /* Created: 15-MAR-2001 23:38:09 by OpenVMS SDL EV1-33 */ /* Source: 15-MAR-2001 23:34:16 _$11$DUA933:[BUILD.SDL]STARDEFMP.SDI;1 */ /********************************************************************************************************************************/ /*** MODULE $PR1202DEF ***/ #ifndef __PR1202DEF_LOADED #define __PR1202DEF_LOADED 1 #pragma nostandard #ifdef __cplusplus extern "C" { #define __unknown_params ... #else #define __unknown_params #endif #if !defined(__VAXC) && !defined(VAXC) #define __struct struct #define __union union #else #define __struct variant_struct #define __union variant_union #endif #define PR1202$_ICCS 24 /* Interval Clock Control/Status */ #define PR1202_ICCS$M_IE 0x40 #define PR1202$_TODR 27 /* Time of Year Clock */ #define PR1202$_RXCS 32 /* Console Receiver Control/Status */ #define PR1202_RXCS$M_RX_IE 0x40 #define PR1202_RXCS$M_RX_DONE 0x80 #define PR1202$_RXDB 33 /* Console Receiver Data Buffer */ #define PR1202_RXDB$M_DATA 0xFF #define PR1202_RXDB$M_RCV_BRK 0x800 #define PR1202_RXDB$M_FRM_ERR 0x2000 #define PR1202_RXDB$M_OVR_ERR 0x4000 #define PR1202_RXDB$M_ERR 0x8000 #define PR1202$_TXCS 34 /* Console Transmit Control/Status */ #define PR1202_TXCS$M_XMIT_BRK 0x1 #define PR1202_TXCS$M_LOOPBACK 0x4 #define PR1202_TXCS$M_TX_IE 0x40 #define PR1202_TXCS$M_TX_RDY 0x80 #define PR1202$_TXDB 35 /* Console Transmit Data Buffer */ #define PR1202_TXDB$M_DATA 0xFF #define PR1202$_MCESR 38 /* Machine Check Error Register */ #define PR1202$_ACCS 40 /* Floating Point Accelerator Register */ #define PR1202_ACCS$M_VECTOR_PRESENT 0x1 #define PR1202_ACCS$M_FCHIP_PRESENT 0x2 #define PR1202_ACCS$M_EADDR_MODE 0x4 #define PR1202_ACCS$M_WRITE_EVEN_PARITY 0x80000000 #define PR1202$_SAVPC 42 /* Console SAVED PC */ #define PR1202$_SAVPSL 43 /* Console SAVED PSL */ #define PR1202_SAVPSL$M_HALT_CODE 0x3F00 #define PR1202_SAVPSL$M_INVALID 0x4000 #define PR1202_SAVPSL$M_MAPEN 0x8000 #define PR1202$_TBTAG 47 /* Translation Buffer Tag */ #define PR1202$_IORESET 55 /* IO BUS RESET */ #define PR1202$_TBDATA 59 /* Translation Buffer Data */ #define PR1202$_SID 62 /* System Identification Register */ #define PR1202_SID$M_UCODE_REV 0xFF #define PR1202_SID$M_UCODE_OPT 0xFF00 #define PR1202_SID$M_CPU_TYPE 0xFF000000 #define PR1202_XSID$M_ARCH_ID 0xFF #define PR1202_XSID$M_SYS_VAR 0xFF00 #define PR1202_XSID$M_CONSOLE_REV 0xFF0000 #define PR1202_XSID$M_SYS_TYPE 0xFF000000 #define PR1202$_BCIDX 112 /* Backup Cache Index Register */ #define PR1202_BCIDX$M_BCIDX 0x7FF80 #define PR1202_BCIDX$M_COLUMN 0x780 #define PR1202_BCIDX$M_ROW 0x7F800 #define PR1202$_BCSTS 113 /* Backup Cache Status Register */ #define PR1202_BCSTS$M_ERR_SUMMARY 0x1 #define PR1202_BCSTS$M_BTS_TPERR 0x2 #define PR1202_BCSTS$M_BTS_VDPERR 0x4 #define PR1202_BCSTS$M_I_PERR 0x30 #define PR1202_BCSTS$M_FILL_ABORT 0x40 #define PR1202_BCSTS$M_AC_PERR 0x80 #define PR1202_BCSTS$M_SECOND_ERR 0x100 #define PR1202_BCSTS$M_BTS_HIT 0x8000 #define PR1202_BCSTS$M_BTS_COMPARE 0x10000 #define PR1202_BCSTS$M_PPG 0x20000 #define PR1202_BCSTS$M_PTS_PARITY 0xC0000 #define PR1202_BCSTS$M_IBUS_CYCLE 0x100000 #define PR1202_BCSTS$M_IBUS_CMD 0x200000 #define PR1202_BCSTS$M_DAL_CMD 0x3C00000 #define PR1202_BCSTS$M_DMG_L 0x4000000 #define PR1202_BCSTS$M_SYNC_L 0x8000000 #define PR1202_BCSTS$M_AC_PARITY 0x10000000 #define PR1202_BCSTS$M_OREAD_PENDING 0x20000000 #define PR1202$_BCCTL 114 /* Backup Cache Control Register */ #define PR1202_BCCTL$M_FORCE_BHIT 0x1 #define PR1202_BCCTL$M_ENABLE_BTS 0x2 #define PR1202_BCCTL$M_BTS_ERROR_TRAN 0x4 #define PR1202_BCCTL$M_GEN_BAD_ACP 0x8 #define PR1202$_BCERA 115 /* Error address register */ #define PR1202$_BCBTS 116 /* Backup Cache Tag Store */ #define PR1202_BCBTS$M_VALID 0xF #define PR1202_BCBTS$M_DIRTY 0xF0 #define PR1202_BCBTS$M_VD_PARITY 0x100 #define PR1202_BCBTS$M_TAG_PARITY 0x200 #define PR1202_BCBTS$M_TAG 0x7FF80000 #define PR1202$_BCDET 117 /* Deallocate tag register */ #define PR1202$_BCERT 118 /* Current parity bits */ #define PR1202_BCERT$M_VALID 0xF #define PR1202_BCERT$M_DIRTY 0xF0 #define PR1202_BCERT$M_VD_DIRTY 0x100 #define PR1202_BCERT$M_TAG_PARITY 0x200 #define PR1202_BCERT$M_CACHE_ENTRY 0x7FF80000 #define PR1202$_BC119 119 /* Backup Cache Reserved Reister */ #define PR1202$_BC120 120 /* Backup Cache Reserved Reister */ #define PR1202$_BC121 121 /* Backup Cache Reserved Reister */ #define PR1202$_BC122 122 /* Backup Cache Reserved Reister */ #define PR1202$_VINTSR 123 /* Vector Interface Error Status Reg. */ #define PR1202_VINTSR$M_VP_ABSENT 0x1 #define PR1202_VINTSR$M_VP_SERR 0x2 #define PR1202_VINTSR$M_VP_HERR 0x4 #define PR1202_VINTSR$M_VECTL_VIB_SERR 0x8 #define PR1202_VINTSR$M_VECTL_VIB_HERR 0x10 #define PR1202_VINTSR$M_CCHIP_VIB_SERR 0x20 #define PR1202_VINTSR$M_CCHIP_VIB_HERR 0x40 #define PR1202_VINTSR$M_BUS_TIMEOUT 0x80 #define PR1202_VINTSR$M_VP_RESET 0x100 #define PR1202_VINTSR$M_DIS_VP_INTF 0x200 #define PR1202_VINTSR$M_BAD_DPARITY 0x400 #define PR1202_VINTSR$M_BAD_CPARITY 0x800 #define PR1202$_PCTAG 124 /* Primary Cache Tag Store */ #define PR1202_PCTAG$M_VALID 0x1 #define PR1202_PCTAG$M_TAG 0x7FFFF800 #define PR1202_PCTAG$M_PARITY 0x80000000 #define PR1202$_PCIDX 125 /* Primary Cache Index Register */ #define PR1202_PCIDX$M_IDX 0x7F8 #define PR1202$_PCERR 126 /* Primary Cache Error Address Register */ #define PR1202$_PCSTS 127 /* Primary Cache Status Register */ #define PR1202_PCSTS$M_FORCE_HIT 0x1 #define PR1202_PCSTS$M_ENABLE_PTS 0x2 #define PR1202_PCSTS$M_FLUSH 0x4 #define PR1202_PCSTS$M_P_CACHE_HIT 0x10 #define PR1202_PCSTS$M_INTERRUPT 0x20 #define PR1202_PCSTS$M_TRAP2 0x40 #define PR1202_PCSTS$M_TRAP1 0x80 #define PR1202_PCSTS$M_TAG_PARITY_ERR 0x100 #define PR1202_PCSTS$M_DAL_PARITY_ERR 0x200 #define PR1202_PCSTS$M_DATA_PARITY_ERR 0x400 #define PR1202_PCSTS$M_BUS_ERR 0x800 #define PR1202_PCSTS$M_B_CACHE_HIT 0x1000 union pr1202def { __struct { unsigned pr1202_iccs$v_fill_1 : 6; unsigned pr1202_iccs$v_ie : 1; /* Interrupt enable */ unsigned pr1202_iccs$v_fill_94 : 1; } pr1202r_pr1202iccs_bits; __struct { unsigned pr1202_rxcs$v_fill_1 : 6; unsigned pr1202_rxcs$v_rx_ie : 1; /* Interrupt enable */ unsigned pr1202_rxcs$v_rx_done : 1; /* Receiver done */ } pr1202r_pr1202rxcs_bits; __struct { unsigned pr1202_rxdb$v_data : 8; /* Received data */ unsigned pr1202_rxdb$v_fill_1 : 3; unsigned pr1202_rxdb$v_rcv_brk : 1; /* Break or CTRL/P received */ unsigned pr1202_rxdb$v_fill_2 : 1; unsigned pr1202_rxdb$v_frm_err : 1; /* Framing error */ unsigned pr1202_rxdb$v_ovr_err : 1; /* Overrun error */ unsigned pr1202_rxdb$v_err : 1; /* Error */ } pr1202r_pr1202rxdb_bits; __struct { unsigned pr1202_txcs$v_xmit_brk : 1; /* Transmit break */ unsigned pr1202_txcs$v_fill_1 : 1; unsigned pr1202_txcs$v_loopback : 1; /* Loopback */ unsigned pr1202_txcs$v_fill_2 : 3; unsigned pr1202_txcs$v_tx_ie : 1; /* Interrupt enable */ unsigned pr1202_txcs$v_tx_rdy : 1; /* Transmitter ready */ } pr1202r_pr1202txcs_bits; __struct { unsigned pr1202_txdb$v_data : 8; /* Data to transmit */ } pr1202r_pr1202txdb_bits; __struct { unsigned pr1202_accs$v_vector_present : 1; /* Vector unit present */ unsigned pr1202_accs$v_fchip_present : 1; /* F-Chip present */ unsigned pr1202_accs$v_eaddr_mode : 1; /* Selects 30-bit/32-bit mode */ unsigned pr1202_accs$v_fill_1 : 28; unsigned pr1202_accs$v_write_even_parity : 1; /* Write even parity */ } pr1202r_pr1202accs_bits; __struct { unsigned pr1202_savpsl$v_fill_1 : 8; unsigned pr1202_savpsl$v_halt_code : 6; /* Halt code */ unsigned pr1202_savpsl$v_invalid : 1; /* Saved PSL invalid */ unsigned pr1202_savpsl$v_mapen : 1; /* Saved MAPEN */ } pr1202r_pr1202savpsl_bits; __struct { unsigned pr1202_sid$v_ucode_rev : 8; /* Microcode revision level */ unsigned pr1202_sid$v_ucode_opt : 8; /* Microcode option */ unsigned pr1202_sid$v_fill_1 : 8; unsigned pr1202_sid$v_cpu_type : 8; /* CPU_TYPE (12 hex/18 decimal) */ } pr1202r_pr1202sid_bits; /* XSID (SYS_TYPE) Register bits */ __struct { unsigned pr1202_xsid$v_arch_id : 8; /* Timeshare/Server */ unsigned pr1202_xsid$v_sys_var : 8; /* System Variant */ unsigned pr1202_xsid$v_console_rev : 8; /* XMP console revision level */ unsigned pr1202_xsid$v_sys_type : 8; /* System type (02) */ } pr1202r_pr1202xsid_bits; __struct { __union { __struct { unsigned pr1202_bcidx$v_fill_1 : 7; unsigned pr1202_bcidx$v_bcidx : 12; /* Backup cache tag index */ unsigned pr1202_bcidx$v_fill_95 : 5; } pr1202_bcidx$r_bcidx_bits0; __struct { unsigned pr1202_bcidx$v_fill_2 : 7; unsigned pr1202_bcidx$v_column : 4; /* Backup tag column index */ unsigned pr1202_bcidx$v_row : 8; /* Backup tag row index */ unsigned pr1202_bcidx$v_fill_96 : 5; } pr1202_bcidx$r_bcidx1_bits; } pr1202_bcidx$r_bcidx_overlay; } pr1202r_pr1202bcidx; __struct { unsigned pr1202_bcsts$v_err_summary : 1; /* Error summary */ unsigned pr1202_bcsts$v_bts_tperr : 1; /* Parity error in tag field */ unsigned pr1202_bcsts$v_bts_vdperr : 1; /* Parity error in V/D bit */ unsigned pr1202_bcsts$v_fill_1 : 1; unsigned pr1202_bcsts$v_i_perr : 2; /* IBUS parity error */ unsigned pr1202_bcsts$v_fill_abort : 1; /* Cache fill aborted */ unsigned pr1202_bcsts$v_ac_perr : 1; /* Address/Command parity error */ unsigned pr1202_bcsts$v_second_err : 1; /* Second error occured */ unsigned pr1202_bcsts$v_fill_2 : 6; unsigned pr1202_bcsts$v_bts_hit : 1; /* Valid sublock hit */ unsigned pr1202_bcsts$v_bts_compare : 1; /* Results of tap comparison */ unsigned pr1202_bcsts$v_ppg : 1; /* Predicted parity generator */ unsigned pr1202_bcsts$v_pts_parity : 2; /* Parity generated on tag */ unsigned pr1202_bcsts$v_ibus_cycle : 1; /* Status register is loaded */ unsigned pr1202_bcsts$v_ibus_cmd : 1; /* Invalidate command siganl */ unsigned pr1202_bcsts$v_dal_cmd : 4; /* Last DAL command */ unsigned pr1202_bcsts$v_dmg_l : 1; /* DMG from last DAL command */ unsigned pr1202_bcsts$v_sync_l : 1; /* SYNC from last DAL command */ unsigned pr1202_bcsts$v_ac_parity : 1; /* Parity from last ABUS DAL */ unsigned pr1202_bcsts$v_oread_pending : 1; /* Pending OREAD during last DAL */ unsigned pr1202_bcsts$v_fill_97 : 2; } pr1202r_pr1202bcsts_bits; __struct { unsigned pr1202_bcctl$v_force_bhit : 1; /* Force hit */ unsigned pr1202_bcctl$v_enable_bts : 1; /* Enable backup cache */ unsigned pr1202_bcctl$v_bts_error_tran : 1; /* Error transition */ unsigned pr1202_bcctl$v_gen_bad_acp : 1; /* Generate incorrect parity */ unsigned pr1202_bcctl$v_fill_98 : 4; } pr1202r_pr1202bcctl_bits; __struct { unsigned pr1202_bcbts$v_valid : 4; /* Four valid bits */ unsigned pr1202_bcbts$v_dirty : 4; /* Four dirty bits */ unsigned pr1202_bcbts$v_vd_parity : 1; /* Valid/dirty parity bit */ unsigned pr1202_bcbts$v_tag_parity : 1; /* Tag parity bit */ unsigned pr1202_bcbts$v_fill_1 : 9; unsigned pr1202_bcbts$v_tag : 12; /* Cache tag */ unsigned pr1202_bcbts$v_fill_2 : 1; } pr1202r_pr1202bcbts_bits; __struct { unsigned pr1202_bcert$v_valid : 4; /* Valid bit */ unsigned pr1202_bcert$v_dirty : 4; /* Dirty bit */ unsigned pr1202_bcert$v_vd_dirty : 1; /* Valid/dirty parity bit */ unsigned pr1202_bcert$v_tag_parity : 1; /* Tag parity bit */ unsigned pr1202_bcert$v_fill_1 : 9; unsigned pr1202_bcert$v_cache_entry : 12; /* Cache entry tag */ unsigned pr1202_bcert$v_fill_99 : 1; } pr1202r_pr1202bcert_bits; __struct { unsigned pr1202_vintsr$v_vp_absent : 1; /* 1=Vector Unit is present */ unsigned pr1202_vintsr$v_vp_serr : 1; /* Recoverable internal error */ unsigned pr1202_vintsr$v_vp_herr : 1; /* Unrecoverable internal error */ unsigned pr1202_vintsr$v_vectl_vib_serr : 1; /* Recoverable VIB error */ unsigned pr1202_vintsr$v_vectl_vib_herr : 1; /* Unrecoverable VIB error */ unsigned pr1202_vintsr$v_cchip_vib_serr : 1; /* MC-chip detected recoverable VIB error */ unsigned pr1202_vintsr$v_cchip_vib_herr : 1; /* MC-chip detected unrecoverable VIB error */ unsigned pr1202_vintsr$v_bus_timeout : 1; /* MC-chip detected bus timeout to vec IPR read/write */ unsigned pr1202_vintsr$v_vp_reset : 1; /* Vector module reset */ unsigned pr1202_vintsr$v_dis_vp_intf : 1; /* Disable vector interface to MC-chip */ unsigned pr1202_vintsr$v_bad_dparity : 1; /* Causes MC-chip to generate bad parity on data */ unsigned pr1202_vintsr$v_bad_cparity : 1; /* Causes MC-chip to generate bad parity on command */ unsigned pr1202_vintsr$v_fill_100 : 4; } pr1202r_pr1202vintsr_bits; __struct { unsigned pr1202_pctag$v_valid : 1; /* Valid bit */ unsigned pr1202_pctag$v_fill_1 : 10; unsigned pr1202_pctag$v_tag : 20; /* Cache tag */ unsigned pr1202_pctag$v_parity : 1; /* Parity bit */ } pr1202r_pr1202pctag_bits; __struct { unsigned pr1202_pcidx$v_fill_1 : 3; unsigned pr1202_pcidx$v_idx : 8; /* Tag index */ unsigned pr1202_pcidx$v_fill_101 : 5; } pr1202r_pr1202pcidx_bits; __struct { unsigned pr1202_pcsts$v_force_hit : 1; /* Force hit */ unsigned pr1202_pcsts$v_enable_pts : 1; /* Enable tag store (cache on) */ unsigned pr1202_pcsts$v_flush : 1; /* Flush cache */ unsigned pr1202_pcsts$v_fill_1 : 1; unsigned pr1202_pcsts$v_p_cache_hit : 1; /* Reference hit */ unsigned pr1202_pcsts$v_interrupt : 1; /* Error interrupt pending */ unsigned pr1202_pcsts$v_trap2 : 1; /* Double error lock */ unsigned pr1202_pcsts$v_trap1 : 1; /* Error lock */ unsigned pr1202_pcsts$v_tag_parity_err : 1; /* Tag parity error */ unsigned pr1202_pcsts$v_dal_parity_err : 1; /* DAL data parity error */ unsigned pr1202_pcsts$v_data_parity_err : 1; /* Data parity error */ unsigned pr1202_pcsts$v_bus_err : 1; /* Bus error */ unsigned pr1202_pcsts$v_b_cache_hit : 1; /* Reference hit in Bcache */ unsigned pr1202_pcsts$v_fill_102 : 3; } pr1202r_pr1202pcsts_bits; } ; #if !defined(__VAXC) && !defined(VAXC) #define pr1202_iccs$v_ie pr1202r_pr1202iccs_bits.pr1202_iccs$v_ie #define pr1202_rxcs$v_rx_ie pr1202r_pr1202rxcs_bits.pr1202_rxcs$v_rx_ie #define pr1202_rxcs$v_rx_done pr1202r_pr1202rxcs_bits.pr1202_rxcs$v_rx_done #define pr1202_rxdb$v_data pr1202r_pr1202rxdb_bits.pr1202_rxdb$v_data #define pr1202_rxdb$v_rcv_brk pr1202r_pr1202rxdb_bits.pr1202_rxdb$v_rcv_brk #define pr1202_rxdb$v_frm_err pr1202r_pr1202rxdb_bits.pr1202_rxdb$v_frm_err #define pr1202_rxdb$v_ovr_err pr1202r_pr1202rxdb_bits.pr1202_rxdb$v_ovr_err #define pr1202_rxdb$v_err pr1202r_pr1202rxdb_bits.pr1202_rxdb$v_err #define pr1202_txcs$v_xmit_brk pr1202r_pr1202txcs_bits.pr1202_txcs$v_xmit_brk #define pr1202_txcs$v_loopback pr1202r_pr1202txcs_bits.pr1202_txcs$v_loopback #define pr1202_txcs$v_tx_ie pr1202r_pr1202txcs_bits.pr1202_txcs$v_tx_ie #define pr1202_txcs$v_tx_rdy pr1202r_pr1202txcs_bits.pr1202_txcs$v_tx_rdy #define pr1202_txdb$v_data pr1202r_pr1202txdb_bits.pr1202_txdb$v_data #define pr1202_accs$v_vector_present pr1202r_pr1202accs_bits.pr1202_accs$v_vector_present #define pr1202_accs$v_fchip_present pr1202r_pr1202accs_bits.pr1202_accs$v_fchip_present #define pr1202_accs$v_eaddr_mode pr1202r_pr1202accs_bits.pr1202_accs$v_eaddr_mode #define pr1202_accs$v_write_even_parity pr1202r_pr1202accs_bits.pr1202_accs$v_write_even_parity #define pr1202_savpsl$v_halt_code pr1202r_pr1202savpsl_bits.pr1202_savpsl$v_halt_code #define pr1202_savpsl$v_invalid pr1202r_pr1202savpsl_bits.pr1202_savpsl$v_invalid #define pr1202_savpsl$v_mapen pr1202r_pr1202savpsl_bits.pr1202_savpsl$v_mapen #define pr1202_sid$v_ucode_rev pr1202r_pr1202sid_bits.pr1202_sid$v_ucode_rev #define pr1202_sid$v_ucode_opt pr1202r_pr1202sid_bits.pr1202_sid$v_ucode_opt #define pr1202_sid$v_cpu_type pr1202r_pr1202sid_bits.pr1202_sid$v_cpu_type #define pr1202_xsid$v_arch_id pr1202r_pr1202xsid_bits.pr1202_xsid$v_arch_id #define pr1202_xsid$v_sys_var pr1202r_pr1202xsid_bits.pr1202_xsid$v_sys_var #define pr1202_xsid$v_console_rev pr1202r_pr1202xsid_bits.pr1202_xsid$v_console_rev #define pr1202_xsid$v_sys_type pr1202r_pr1202xsid_bits.pr1202_xsid$v_sys_type #define pr1202_bcidx$v_bcidx pr1202r_pr1202bcidx.pr1202_bcidx$r_bcidx_overlay.pr1202_bcidx$r_bcidx_bits0.pr1202_bcidx$v_bcidx #define pr1202_bcidx$v_column pr1202r_pr1202bcidx.pr1202_bcidx$r_bcidx_overlay.pr1202_bcidx$r_bcidx1_bits.pr1202_bcidx$v_column #define pr1202_bcidx$v_row pr1202r_pr1202bcidx.pr1202_bcidx$r_bcidx_overlay.pr1202_bcidx$r_bcidx1_bits.pr1202_bcidx$v_row #define pr1202_bcsts$v_err_summary pr1202r_pr1202bcsts_bits.pr1202_bcsts$v_err_summary #define pr1202_bcsts$v_bts_tperr pr1202r_pr1202bcsts_bits.pr1202_bcsts$v_bts_tperr #define pr1202_bcsts$v_bts_vdperr pr1202r_pr1202bcsts_bits.pr1202_bcsts$v_bts_vdperr #define pr1202_bcsts$v_i_perr pr1202r_pr1202bcsts_bits.pr1202_bcsts$v_i_perr #define pr1202_bcsts$v_fill_abort pr1202r_pr1202bcsts_bits.pr1202_bcsts$v_fill_abort #define pr1202_bcsts$v_ac_perr pr1202r_pr1202bcsts_bits.pr1202_bcsts$v_ac_perr #define pr1202_bcsts$v_second_err pr1202r_pr1202bcsts_bits.pr1202_bcsts$v_second_err #define pr1202_bcsts$v_bts_hit pr1202r_pr1202bcsts_bits.pr1202_bcsts$v_bts_hit #define pr1202_bcsts$v_bts_compare pr1202r_pr1202bcsts_bits.pr1202_bcsts$v_bts_compare #define pr1202_bcsts$v_ppg pr1202r_pr1202bcsts_bits.pr1202_bcsts$v_ppg #define pr1202_bcsts$v_pts_parity pr1202r_pr1202bcsts_bits.pr1202_bcsts$v_pts_parity #define pr1202_bcsts$v_ibus_cycle pr1202r_pr1202bcsts_bits.pr1202_bcsts$v_ibus_cycle #define pr1202_bcsts$v_ibus_cmd pr1202r_pr1202bcsts_bits.pr1202_bcsts$v_ibus_cmd #define pr1202_bcsts$v_dal_cmd pr1202r_pr1202bcsts_bits.pr1202_bcsts$v_dal_cmd #define pr1202_bcsts$v_dmg_l pr1202r_pr1202bcsts_bits.pr1202_bcsts$v_dmg_l #define pr1202_bcsts$v_sync_l pr1202r_pr1202bcsts_bits.pr1202_bcsts$v_sync_l #define pr1202_bcsts$v_ac_parity pr1202r_pr1202bcsts_bits.pr1202_bcsts$v_ac_parity #define pr1202_bcsts$v_oread_pending pr1202r_pr1202bcsts_bits.pr1202_bcsts$v_oread_pending #define pr1202_bcctl$v_force_bhit pr1202r_pr1202bcctl_bits.pr1202_bcctl$v_force_bhit #define pr1202_bcctl$v_enable_bts pr1202r_pr1202bcctl_bits.pr1202_bcctl$v_enable_bts #define pr1202_bcctl$v_bts_error_tran pr1202r_pr1202bcctl_bits.pr1202_bcctl$v_bts_error_tran #define pr1202_bcctl$v_gen_bad_acp pr1202r_pr1202bcctl_bits.pr1202_bcctl$v_gen_bad_acp #define pr1202_bcbts$v_valid pr1202r_pr1202bcbts_bits.pr1202_bcbts$v_valid #define pr1202_bcbts$v_dirty pr1202r_pr1202bcbts_bits.pr1202_bcbts$v_dirty #define pr1202_bcbts$v_vd_parity pr1202r_pr1202bcbts_bits.pr1202_bcbts$v_vd_parity #define pr1202_bcbts$v_tag_parity pr1202r_pr1202bcbts_bits.pr1202_bcbts$v_tag_parity #define pr1202_bcbts$v_tag pr1202r_pr1202bcbts_bits.pr1202_bcbts$v_tag #define pr1202_bcert$v_valid pr1202r_pr1202bcert_bits.pr1202_bcert$v_valid #define pr1202_bcert$v_dirty pr1202r_pr1202bcert_bits.pr1202_bcert$v_dirty #define pr1202_bcert$v_vd_dirty pr1202r_pr1202bcert_bits.pr1202_bcert$v_vd_dirty #define pr1202_bcert$v_tag_parity pr1202r_pr1202bcert_bits.pr1202_bcert$v_tag_parity #define pr1202_bcert$v_cache_entry pr1202r_pr1202bcert_bits.pr1202_bcert$v_cache_entry #define pr1202_vintsr$v_vp_absent pr1202r_pr1202vintsr_bits.pr1202_vintsr$v_vp_absent #define pr1202_vintsr$v_vp_serr pr1202r_pr1202vintsr_bits.pr1202_vintsr$v_vp_serr #define pr1202_vintsr$v_vp_herr pr1202r_pr1202vintsr_bits.pr1202_vintsr$v_vp_herr #define pr1202_vintsr$v_vectl_vib_serr pr1202r_pr1202vintsr_bits.pr1202_vintsr$v_vectl_vib_serr #define pr1202_vintsr$v_vectl_vib_herr pr1202r_pr1202vintsr_bits.pr1202_vintsr$v_vectl_vib_herr #define pr1202_vintsr$v_cchip_vib_serr pr1202r_pr1202vintsr_bits.pr1202_vintsr$v_cchip_vib_serr #define pr1202_vintsr$v_cchip_vib_herr pr1202r_pr1202vintsr_bits.pr1202_vintsr$v_cchip_vib_herr #define pr1202_vintsr$v_bus_timeout pr1202r_pr1202vintsr_bits.pr1202_vintsr$v_bus_timeout #define pr1202_vintsr$v_vp_reset pr1202r_pr1202vintsr_bits.pr1202_vintsr$v_vp_reset #define pr1202_vintsr$v_dis_vp_intf pr1202r_pr1202vintsr_bits.pr1202_vintsr$v_dis_vp_intf #define pr1202_vintsr$v_bad_dparity pr1202r_pr1202vintsr_bits.pr1202_vintsr$v_bad_dparity #define pr1202_vintsr$v_bad_cparity pr1202r_pr1202vintsr_bits.pr1202_vintsr$v_bad_cparity #define pr1202_pctag$v_valid pr1202r_pr1202pctag_bits.pr1202_pctag$v_valid #define pr1202_pctag$v_tag pr1202r_pr1202pctag_bits.pr1202_pctag$v_tag #define pr1202_pctag$v_parity pr1202r_pr1202pctag_bits.pr1202_pctag$v_parity #define pr1202_pcidx$v_idx pr1202r_pr1202pcidx_bits.pr1202_pcidx$v_idx #define pr1202_pcsts$v_force_hit pr1202r_pr1202pcsts_bits.pr1202_pcsts$v_force_hit #define pr1202_pcsts$v_enable_pts pr1202r_pr1202pcsts_bits.pr1202_pcsts$v_enable_pts #define pr1202_pcsts$v_flush pr1202r_pr1202pcsts_bits.pr1202_pcsts$v_flush #define pr1202_pcsts$v_p_cache_hit pr1202r_pr1202pcsts_bits.pr1202_pcsts$v_p_cache_hit #define pr1202_pcsts$v_interrupt pr1202r_pr1202pcsts_bits.pr1202_pcsts$v_interrupt #define pr1202_pcsts$v_trap2 pr1202r_pr1202pcsts_bits.pr1202_pcsts$v_trap2 #define pr1202_pcsts$v_trap1 pr1202r_pr1202pcsts_bits.pr1202_pcsts$v_trap1 #define pr1202_pcsts$v_tag_parity_err pr1202r_pr1202pcsts_bits.pr1202_pcsts$v_tag_parity_err #define pr1202_pcsts$v_dal_parity_err pr1202r_pr1202pcsts_bits.pr1202_pcsts$v_dal_parity_err #define pr1202_pcsts$v_data_parity_err pr1202r_pr1202pcsts_bits.pr1202_pcsts$v_data_parity_err #define pr1202_pcsts$v_bus_err pr1202r_pr1202pcsts_bits.pr1202_pcsts$v_bus_err #define pr1202_pcsts$v_b_cache_hit pr1202r_pr1202pcsts_bits.pr1202_pcsts$v_b_cache_hit #endif /* #if !defined(__VAXC) && !defined(VAXC) */ #ifdef __cplusplus } #endif #pragma standard #endif /* __PR1202DEF_LOADED */