%IF %DECLARED ( %BASIC$QUADWORD_DECLARED ) = 0 %THEN RECORD BASIC$QUADWORD LONG FILL ( 2 ) END RECORD %LET %BASIC$QUADWORD_DECLARED = 1 %END %IF %IF %DECLARED ( %BASIC$OCTAWORD_DECLARED ) = 0 %THEN RECORD BASIC$OCTAWORD LONG FILL ( 4 ) END RECORD %LET %BASIC$OCTAWORD_DECLARED = 1 %END %IF %IF %DECLARED ( %BASIC$F_FLOATING_COMPLEX_DECL ) = 0 %THEN RECORD BASIC$F_FLOATING_COMPLEX SINGLE REAL_PART SINGLE IMAGINARY_PART END RECORD %LET %BASIC$F_FLOATING_COMPLEX_DECL = 1 %END %IF %IF %DECLARED ( %BASIC$D_FLOATING_COMPLEX_DECL ) = 0 %THEN RECORD BASIC$D_FLOATING_COMPLEX DOUBLE REAL_PART DOUBLE IMAGINARY_PART END RECORD %LET %BASIC$D_FLOATING_COMPLEX_DECL = 1 %END %IF %IF %DECLARED ( %BASIC$G_FLOATING_COMPLEX_DECL ) = 0 %THEN RECORD BASIC$G_FLOATING_COMPLEX GFLOAT REAL_PART GFLOAT IMAGINARY_PART END RECORD %LET %BASIC$G_FLOATING_COMPLEX_DECL = 1 %END %IF %IF %DECLARED ( %BASIC$H_FLOATING_COMPLEX_DECL ) = 0 %THEN RECORD BASIC$H_FLOATING_COMPLEX HFLOAT REAL_PART HFLOAT IMAGINARY_PART END RECORD %LET %BASIC$H_FLOATING_COMPLEX_DECL = 1 %END %IF DECLARE LONG CONSTANT XRV$_PR_VIADR = 157 ! Vector indirect address DECLARE LONG CONSTANT XRV$_PR_VIDLO = 158 ! Vector indirect data low DECLARE LONG CONSTANT XRV$_PR_VIDHI = 159 ! Vector indirect data hi ! + DECLARE LONG CONSTANT XRV$_VIR_VREG0 = 0 ! Vector Register 0 DECLARE LONG CONSTANT XRV$_VIR_VREG1 = 64 ! Vector Register 1 DECLARE LONG CONSTANT XRV$_VIR_VREG2 = 128 ! Vector Register 2 DECLARE LONG CONSTANT XRV$_VIR_VREG3 = 192 ! Vector Register 3 DECLARE LONG CONSTANT XRV$_VIR_VREG4 = 256 ! Vector Register 4 DECLARE LONG CONSTANT XRV$_VIR_VREG5 = 320 ! Vector Register 5 DECLARE LONG CONSTANT XRV$_VIR_VREG6 = 384 ! Vector Register 6 DECLARE LONG CONSTANT XRV$_VIR_VREG7 = 448 ! Vector Register 7 DECLARE LONG CONSTANT XRV$_VIR_VREG8 = 512 ! Vector Register 8 DECLARE LONG CONSTANT XRV$_VIR_VREG9 = 576 ! Vector Register 9 DECLARE LONG CONSTANT XRV$_VIR_VREG10 = 640 ! Vector Register 10 DECLARE LONG CONSTANT XRV$_VIR_VREG11 = 704 ! Vector Register 11 DECLARE LONG CONSTANT XRV$_VIR_VREG12 = 768 ! Vector Register 12 DECLARE LONG CONSTANT XRV$_VIR_VREG13 = 832 ! Vector Register 13 DECLARE LONG CONSTANT XRV$_VIR_VREG14 = 832 ! Vector Register 14 DECLARE LONG CONSTANT XRV$_VIR_VREG15 = 960 ! Vector Register 15 DECLARE LONG CONSTANT XRV$_VIR_ALU_OP = 1088 ! Arithmetic opcode DECLARE LONG CONSTANT XRV$_VIR_ALU_SCOP_LO = 1096 ! Scalar operand LO DECLARE LONG CONSTANT XRV$_VIR_ALU_SCOP_HI = 1100 ! Scalar operand HI DECLARE LONG CONSTANT XRV$_VIR_ALU_MASK_LO = 1100 ! Vector mask LO DECLARE LONG CONSTANT XRV$_VIR_ALU_MASK_HI = 1104 ! Vector mask HI DECLARE LONG CONSTANT XRV$_VIR_ALU_EXC = 1108 ! ALU exception reg. ! Location 458 reserved DECLARE LONG CONSTANT XRV$_VIR_ALU_DIAG_CTRL = 1116 ! Diagnostic control DECLARE LONG CONSTANT XRV$M_VIR_ALU_DIAG_CTRL_ISL = x'00000001' DECLARE LONG CONSTANT XRV$M_VIR_ALU_DIAG_CTRL_ISH = x'00000002' DECLARE LONG CONSTANT XRV$M_VIR_ALU_DIAG_CTRL_IBL = x'00000004' DECLARE LONG CONSTANT XRV$M_VIR_ALU_DIAG_CTRL_IBH = x'00000008' DECLARE LONG CONSTANT XRV$M_VIR_ALU_DIAG_CTRL_ICL = x'00000010' DECLARE LONG CONSTANT XRV$M_VIR_ALU_DIAG_CTRL_ICH = x'00000020' DECLARE LONG CONSTANT XRV$M_VIR_ALU_DIAG_CTRL_ICI = x'00000040' DECLARE LONG CONSTANT XRV$M_VIR_ALU_DIAG_CTRL_ABE = x'00000100' DECLARE LONG CONSTANT XRV$M_VIR_ALU_DIAG_CTRL_CPE = x'00000200' DECLARE LONG CONSTANT XRV$M_VIR_ALU_DIAG_CTRL_IFO = x'00000400' DECLARE LONG CONSTANT XRV$_VIR_VERSE_CHIP0 = 1116 ! Verse Chip 0 reg. DECLARE LONG CONSTANT XRV$_VIR_VERSE_CHIP1 = 1117 ! Verse Chip 1 reg. DECLARE LONG CONSTANT XRV$_VIR_VERSE_CHIP2 = 1118 ! Verse Chip 2 reg. DECLARE LONG CONSTANT XRV$_VIR_VERSE_CHIP3 = 1119 ! Verse Chip 3 reg. DECLARE LONG CONSTANT XRV$_VIR_VCTL_CALU = 1152 ! Current ALU instr. DECLARE LONG CONSTANT XRV$_VIR_VCTL_DALU = 1153 ! Defered ALU instr. DECLARE LONG CONSTANT XRV$_VIR_VCTL_COP_LO = 1154 ! Current ALU oper. LO DECLARE LONG CONSTANT XRV$_VIR_VCTL_COP_HI = 1155 ! Current ALU oper. HI DECLARE LONG CONSTANT XRV$_VIR_VCTL_DOP_LO = 1156 ! Defered ALU oper. LO DECLARE LONG CONSTANT XRV$_VIR_VCTL_DOP_HI = 1157 ! Defered ALU oper. HI DECLARE LONG CONSTANT XRV$_VIR_VCTL_LS = 1158 ! Load/Store instr. DECLARE LONG CONSTANT XRV$_VIR_VCTL_STRIDE = 1159 ! Load/Store stride DECLARE LONG CONSTANT XRV$_VIR_VCTL_ILL = 1160 ! Illegal instruction DECLARE LONG CONSTANT XRV$_VIR_VCTL_CSR = 1161 ! Controller Status DECLARE LONG CONSTANT XRV$M_VIR_VCTL_CSR_LSS = x'00000001' DECLARE LONG CONSTANT XRV$M_VIR_VCTL_CSR_LSH = x'00000002' DECLARE LONG CONSTANT XRV$M_VIR_VCTL_CSR_CDS = x'00000004' DECLARE LONG CONSTANT XRV$M_VIR_VCTL_CSR_CDH = x'00000008' DECLARE LONG CONSTANT XRV$M_VIR_VCTL_CSR_VIS = x'00000010' DECLARE LONG CONSTANT XRV$M_VIR_VCTL_CSR_VIH = x'00000020' DECLARE LONG CONSTANT XRV$M_VIR_VCTL_CSR_ISE = x'00000040' DECLARE LONG CONSTANT XRV$M_VIR_VCTL_CSR_STF = x'00000200' DECLARE LONG CONSTANT XRV$M_VIR_VCTL_CSR_ETF = x'00000400' DECLARE LONG CONSTANT XRV$M_VIR_VCTL_CSR_VHE = x'00000800' DECLARE LONG CONSTANT XRV$M_VIR_VCTL_CSR_SEE = x'00040000' DECLARE LONG CONSTANT XRV$M_VIR_VCTL_CSR_HEE = x'00080000' DECLARE LONG CONSTANT XRV$M_VIR_VCTL_CSR_FRL = x'00100000' DECLARE LONG CONSTANT XRV$M_VIR_VCTL_CSR_FRH = x'00200000' DECLARE LONG CONSTANT XRV$M_VIR_VCTL_CSR_FDL = x'00400000' DECLARE LONG CONSTANT XRV$M_VIR_VCTL_CSR_FDH = x'00800000' DECLARE LONG CONSTANT XRV$M_VIR_VCTL_CSR_FSE = x'10000000' DECLARE LONG CONSTANT XRV$M_VIR_VCTL_CSR_FVP = x'20000000' DECLARE LONG CONSTANT XRV$M_VIR_VCTL_CSR_IMP = x'80000000' DECLARE LONG CONSTANT XRV$_VIR_MOD_REV = 1162 ! Module revision level DECLARE LONG CONSTANT XRV$M_VIR_MOD_REV_FIXUP_LS = x'00000080' DECLARE LONG CONSTANT XRV$_VIR_LSX_P0BR = 1280 ! P0 base register DECLARE LONG CONSTANT XRV$_VIR_LSX_P0LR = 1281 ! P0 length register DECLARE LONG CONSTANT XRV$_VIR_LSX_P1BR = 1282 ! P1 base register DECLARE LONG CONSTANT XRV$_VIR_LSX_P1LR = 1283 ! P1 length register DECLARE LONG CONSTANT XRV$_VIR_LSX_SBR = 1284 ! System base register DECLARE LONG CONSTANT XRV$_VIR_LSX_SLR = 1285 ! System len. register ! 506-507 reserved DECLARE LONG CONSTANT XRV$_VIR_LSX_EXC = 1288 ! L/S exception reg. DECLARE LONG CONSTANT XRV$_VIR_LSX_TBCSR = 1289 ! TB control register DECLARE LONG CONSTANT XRV$_VIR_LSX_MAPEN = 1290 ! Map enable register DECLARE LONG CONSTANT XRV$_VIR_LSX_TBIA = 1291 ! TB invalidate all DECLARE LONG CONSTANT XRV$_VIR_LSX_TBIS = 1292 ! TB invalidate single ! 50D-50F reserved DECLARE LONG CONSTANT XRV$_VIR_LSX_MASKLO = 1296 ! Mask register LO DECLARE LONG CONSTANT XRV$_VIR_LSX_MASKHI = 1297 ! Mask register HI DECLARE LONG CONSTANT XRV$_VIR_LSX_STRIDE = 1298 ! L/S stride register DECLARE LONG CONSTANT XRV$_VIR_LSX_INST = 1299 ! L/S instruction DECLARE LONG CONSTANT XRV$_VIR_LSX_AGDIAG = 1300 ! AG diagnostic reg. ! 515-517 reserved DECLARE LONG CONSTANT XRV$_VIR_LSX_XBE = 1304 ! XMI bus error reg. DECLARE LONG CONSTANT XRV$_VIR_LSX_XFADR = 1305 ! XMI failed addr reg. ! 51A-51F reserved DECLARE LONG CONSTANT XRV$_VIR_LSX_CCSR = 1312 ! Cache control reg. ! 521-527 reserved DECLARE LONG CONSTANT XRV$M_VIR_LSX_CCSR_ACT = x'00000001' DECLARE LONG CONSTANT XRV$M_VIR_LSX_CCSR_CPE = x'00000200' DECLARE LONG CONSTANT XRV$M_VIR_LSX_CCSR_XSE = x'00000400' DECLARE LONG CONSTANT XRV$M_VIR_LSX_CCSR_XHE = x'00000800' DECLARE LONG CONSTANT XRV$M_FILL_7 = x'00007000' DECLARE LONG CONSTANT XRV$M_VIR_LSX_CCSR_CEE = x'00008000' DECLARE LONG CONSTANT XRV$M_VIR_LSX_CCSR_SEE = x'00010000' DECLARE LONG CONSTANT XRV$M_VIR_LSX_CCSR_ENA = x'00020000' DECLARE LONG CONSTANT XRV$M_VIR_LSX_CCSR_HIT = x'00040000' DECLARE LONG CONSTANT XRV$M_VIR_LSX_CCSR_FHT = x'00080000' DECLARE LONG CONSTANT XRV$M_VIR_LSX_CCSR_FLU = x'00100000' DECLARE LONG CONSTANT XRV$M_FILL_8 = x'00600000' DECLARE LONG CONSTANT XRV$M_VIR_LSX_CCSR_FRL = x'00800000' DECLARE LONG CONSTANT XRV$M_VIR_LSX_CCSR_FDL = x'01000000' DECLARE LONG CONSTANT XRV$M_VIR_LSX_CCSR_FDH = x'02000000' DECLARE LONG CONSTANT XRV$M_VIR_LSX_CCSR_IVS = x'04000000' DECLARE LONG CONSTANT XRV$M_VIR_LSX_CCSR_IPS = x'08000000' DECLARE LONG CONSTANT XRV$M_VIR_LSX_CCSR_DXT = x'10000000' DECLARE LONG CONSTANT XRV$M_VIR_LSX_CCSR_IDV = x'20000000' DECLARE LONG CONSTANT XRV$M_VIR_LSX_CCSR_IDP = x'40000000' DECLARE LONG CONSTANT XRV$M_VIR_LSX_CCSR_DTC = x'80000000' DECLARE LONG CONSTANT XRV$_VIR_LSX_WBDIAG = 1320 ! WB diagnostic reg DECLARE LONG CONSTANT XRV$_VIR_LSX_VMAC1 = 1321 ! Memory active start DECLARE LONG CONSTANT XRV$_VIR_LSX_VMAC2 = 1322 ! Memory active check ! 52B-51F reserved DECLARE LONG CONSTANT XRV$_VIR_LSX_TAG = 1328 ! TB tag register DECLARE LONG CONSTANT XRV$_VIR_LSX_PTE = 1329 ! TB PTE register ! 532-53F reserved DECLARE LONG CONSTANT XRVS_XRVDEF = 4 record XRVDEF variant ! + ! Internal Processor register definitions for XRV Vector Processor ! - ! Indirect register definitions for XRV Vector Processor ! - case group XRVR_XRV_VIR_ALU_DIAG_CTRL_BITS ! Invert scalar operand parity low ! Invert scalar operand parity high ! Invert B parity low ! Invert B parity high ! Invert CD bus parity low ! Invert CD bus parity high ! Invert internally generated CP parity ! AB parity error ! C bus parity error ! Illegal FAVOR opcode LONG VIR_ALU_DIAG_CTRL_ISL_bits ! COMMENT ADDED BY SDL - VIR_ALU_DIAG_CTRL_ISL_bits contains bits & ! VIR_ALU_DIAG_CTRL_ISL through FILL_2 end group XRVR_XRV_VIR_ALU_DIAG_CTRL_BITS case group XRVR_XRV_VIR_VCTL_CSR_BITS ! Load store chip soft error ! Load store chip hard error ! Soft internal bus parity error ! Hard internal bus parity error ! VIB bus soft error ! VIB* bus hard error ! Illegal sequence error ! Machine check code ! Self test failed ! Extended test failed ! Verse hard error ! Soft error enable ! Hard error enable ! Force bad RFA low parity ! Force bad RFA high parity ! Force bad CD bus low data parity ! Force bad CD bus high data parity ! Current mode during error ! Force soft error ! Force bad VIB bus parity data parity ! Implementation specific error LONG VIR_VCTL_CSR_LSS_bits ! COMMENT ADDED BY SDL - VIR_VCTL_CSR_LSS_bits contains bits VIR_VCTL_CSR_LSS & ! through VIR_VCTL_CSR_IMP end group XRVR_XRV_VIR_VCTL_CSR_BITS case group XRVR_XRV_VIR_MOD_REV_BITS ! Module revision ! Load store fixup trigger LONG VIR_MOD_REV_REVISION_bits ! COMMENT ADDED BY SDL - VIR_MOD_REV_REVISION_bits contains bits & ! VIR_MOD_REV_REVISION through FILL_6 end group XRVR_XRV_VIR_MOD_REV_BITS case group XRVR_XRV_VIR_LSX_CCSR_BITS ! Memory activity ! Load store chip revision ! XMI node id ! Cache parity error ! XMI interface soft error ! XMI interface hard error ! Cache error enable ! Soft error enable ! Cache enable ! Cache hit ! Force cache hit ! Invalidate cache ! Force bad low RFA parity ! Force bad low data parity ! Force bad high data parity ! Invert valid bit sense ! Invert parity sense ! Disable XMI transactions ! Invert duplicate tag valid sense ! Invert duplicate tag parity sense ! Duplicate tag check LONG VIR_LSX_CCSR_ACT_bits ! COMMENT ADDED BY SDL - VIR_LSX_CCSR_ACT_bits contains bits VIR_LSX_CCSR_ACT & ! through VIR_LSX_CCSR_DTC end group XRVR_XRV_VIR_LSX_CCSR_BITS end variant end record XRVDEF