%IF %DECLARED ( %BASIC$QUADWORD_DECLARED ) = 0 %THEN
	RECORD BASIC$QUADWORD
		LONG FILL ( 2 )
	END RECORD
    %LET %BASIC$QUADWORD_DECLARED = 1
    %END %IF
    %IF %DECLARED ( %BASIC$OCTAWORD_DECLARED ) = 0 %THEN
	RECORD BASIC$OCTAWORD
		LONG FILL ( 4 )
	END RECORD
    %LET %BASIC$OCTAWORD_DECLARED = 1
    %END %IF
    %IF %DECLARED ( %BASIC$F_FLOATING_COMPLEX_DECL ) = 0 %THEN
    	RECORD BASIC$F_FLOATING_COMPLEX
    		SINGLE REAL_PART
    		SINGLE IMAGINARY_PART
    	END RECORD
    %LET %BASIC$F_FLOATING_COMPLEX_DECL = 1
    %END %IF
    %IF %DECLARED ( %BASIC$D_FLOATING_COMPLEX_DECL ) = 0 %THEN
    	RECORD BASIC$D_FLOATING_COMPLEX
    		DOUBLE REAL_PART
    		DOUBLE IMAGINARY_PART
    	END RECORD
    %LET %BASIC$D_FLOATING_COMPLEX_DECL = 1
    %END %IF
    %IF %DECLARED ( %BASIC$G_FLOATING_COMPLEX_DECL ) = 0 %THEN
    	RECORD BASIC$G_FLOATING_COMPLEX
    		GFLOAT REAL_PART
    		GFLOAT IMAGINARY_PART
    	END RECORD
    %LET %BASIC$G_FLOATING_COMPLEX_DECL = 1
    %END %IF
    %IF %DECLARED ( %BASIC$H_FLOATING_COMPLEX_DECL ) = 0 %THEN
    	RECORD BASIC$H_FLOATING_COMPLEX
    		HFLOAT REAL_PART
    		HFLOAT IMAGINARY_PART
    	END RECORD
    %LET %BASIC$H_FLOATING_COMPLEX_DECL = 1
    %END %IF
    
    
    ! +
    !  Vector Processor Status Register field definitions
    ! -
      DECLARE LONG CONSTANT VPSR$M_VEN = x'00000001'
      DECLARE LONG CONSTANT VPSR$M_RST = x'00000002'
      DECLARE LONG CONSTANT VPSR$M_STS = x'00000004'
      DECLARE LONG CONSTANT VPSR$M_RLD = x'00000008'
      DECLARE LONG CONSTANT VPSR$M_MF = x'00000020'
      DECLARE LONG CONSTANT VPSR$M_PMF = x'00000040'
      DECLARE LONG CONSTANT VPSR$M_AEX = x'00000080'
      DECLARE LONG CONSTANT VPSR$M_IMP = x'01000000'
      DECLARE LONG CONSTANT VPSR$M_IVO = x'02000000'
      DECLARE LONG CONSTANT VPSR$M_BSY = x'80000000'
      DECLARE LONG CONSTANT VPSR$S_VPSRDEF = 4
      record VPSRDEF
         variant
            case
               group VPSR$R_VPSRDEF_BITS
                   ! Enabled
                   ! Reset
                   ! State store
                   ! State reload
                   ! Must be zero
                   ! Memory fault
                   ! Pending memory fault
                   ! Arithmetic exception
                   ! Must be zero
                   ! Implementation-specific error
                   ! Illegal vector opcode
                   ! Must be zero
                   ! Busy
                  LONG VEN_bits   ! COMMENT ADDED BY SDL - VEN_bits contains bits VEN through BSY
               end group VPSR$R_VPSRDEF_BITS
         end variant
      end record VPSRDEF