%IF %DECLARED ( %BASIC$QUADWORD_DECLARED ) = 0 %THEN
	RECORD BASIC$QUADWORD
		LONG FILL ( 2 )
	END RECORD
    %LET %BASIC$QUADWORD_DECLARED = 1
    %END %IF
    %IF %DECLARED ( %BASIC$OCTAWORD_DECLARED ) = 0 %THEN
	RECORD BASIC$OCTAWORD
		LONG FILL ( 4 )
	END RECORD
    %LET %BASIC$OCTAWORD_DECLARED = 1
    %END %IF
    %IF %DECLARED ( %BASIC$F_FLOATING_COMPLEX_DECL ) = 0 %THEN
    	RECORD BASIC$F_FLOATING_COMPLEX
    		SINGLE REAL_PART
    		SINGLE IMAGINARY_PART
    	END RECORD
    %LET %BASIC$F_FLOATING_COMPLEX_DECL = 1
    %END %IF
    %IF %DECLARED ( %BASIC$D_FLOATING_COMPLEX_DECL ) = 0 %THEN
    	RECORD BASIC$D_FLOATING_COMPLEX
    		DOUBLE REAL_PART
    		DOUBLE IMAGINARY_PART
    	END RECORD
    %LET %BASIC$D_FLOATING_COMPLEX_DECL = 1
    %END %IF
    %IF %DECLARED ( %BASIC$G_FLOATING_COMPLEX_DECL ) = 0 %THEN
    	RECORD BASIC$G_FLOATING_COMPLEX
    		GFLOAT REAL_PART
    		GFLOAT IMAGINARY_PART
    	END RECORD
    %LET %BASIC$G_FLOATING_COMPLEX_DECL = 1
    %END %IF
    %IF %DECLARED ( %BASIC$H_FLOATING_COMPLEX_DECL ) = 0 %THEN
    	RECORD BASIC$H_FLOATING_COMPLEX
    		HFLOAT REAL_PART
    		HFLOAT IMAGINARY_PART
    	END RECORD
    %LET %BASIC$H_FLOATING_COMPLEX_DECL = 1
    %END %IF
    
    
      DECLARE LONG CONSTANT PR9RR$_ICCS = 24  !  Interval Clock Control/Status
      DECLARE LONG CONSTANT ICCS$M_IE = x'00000040'
      DECLARE LONG CONSTANT PR9RR$_TODR = 27  !  Time of Year Clock
      DECLARE LONG CONSTANT PR9RR$_RXCS = 32  !  Console Receiver Control/Status
      DECLARE LONG CONSTANT RXCS$M_RX_IE = x'00000040'
      DECLARE LONG CONSTANT RXCS$M_RX_DONE = x'00000080'
      DECLARE LONG CONSTANT PR9RR$_RXDB = 33  !  Console Receiver Data Buffer
      DECLARE LONG CONSTANT RXDB$M_DATA = x'000000FF'
      DECLARE LONG CONSTANT RXDB$M_RCV_BRK = x'00000800'
      DECLARE LONG CONSTANT RXDB$M_FRM_ERR = x'00002000'
      DECLARE LONG CONSTANT RXDB$M_OVR_ERR = x'00004000'
      DECLARE LONG CONSTANT RXDB$M_ERR_9RR = x'00008000'
      DECLARE LONG CONSTANT PR9RR$_TXCS = 34  !  Console Transmit Control/Status
      DECLARE LONG CONSTANT TXCS$M_XMIT_BRK = x'00000001'
      DECLARE LONG CONSTANT TXCS$M_LOOPBACK = x'00000004'
      DECLARE LONG CONSTANT TXCS$M_TX_IE = x'00000040'
      DECLARE LONG CONSTANT TXCS$M_TX_RDY = x'00000080'
      DECLARE LONG CONSTANT PR9RR$_TXDB = 35  !  Console Transmit Data Buffer
      DECLARE LONG CONSTANT TXDB$M_DATA = x'000000FF'
      DECLARE LONG CONSTANT PR9RR$_MCESR = 38  !  Machine Check Error Register
      DECLARE LONG CONSTANT PR9RR$_ACCS = 40  !  Floating Point Accelerator Register
      DECLARE LONG CONSTANT ACCS$M_VECTOR_PRESENT = x'00000001'
      DECLARE LONG CONSTANT ACCS$M_FCHIP_PRESENT = x'00000002'
      DECLARE LONG CONSTANT ACCS$M_WRITE_EVEN_PARITY = x'80000000'
      DECLARE LONG CONSTANT PR9RR$_SAVPC = 42  !  Console SAVED PC
      DECLARE LONG CONSTANT PR9RR$_SAVPSL = 43  !  Console SAVED PSL
      DECLARE LONG CONSTANT SAVPSL$M_HALT_CODE = x'00003F00'
      DECLARE LONG CONSTANT SAVPSL$M_INVALID = x'00004000'
      DECLARE LONG CONSTANT SAVPSL$M_MAPEN = x'00008000'
      DECLARE LONG CONSTANT PR9RR$_TBTAG = 47  !  Translation Buffer Tag
      DECLARE LONG CONSTANT PR9RR$_IORESET = 55  !  IO BUS RESET
      DECLARE LONG CONSTANT PR9RR$_TBDATA = 59  !  Translation Buffer Data
      DECLARE LONG CONSTANT PR9RR$_SID = 62  !  System Identification Register 
      DECLARE LONG CONSTANT XSID$M_ARCH = x'000000FF'
      DECLARE LONG CONSTANT XSID$M_SYS_VAR = x'0000FF00'
      DECLARE LONG CONSTANT XSID$M_XRPFWREV = x'00FF0000'
      DECLARE LONG CONSTANT PR9RR$_BCBTS = 113  !  Backup Cache Tag Store
      DECLARE LONG CONSTANT BCBTS$M_VALID = x'0000003C'
      DECLARE LONG CONSTANT BCBTS$M_TAG = x'1FFE0000'
      DECLARE LONG CONSTANT BCBTS$M_PARITY = x'20000000'
      DECLARE LONG CONSTANT PR9RR$_BCP1TS = 114  !  Backup cache primary tag array, first half bits
      DECLARE LONG CONSTANT BCPTS$M_VALID = x'00000004'
      DECLARE LONG CONSTANT BCPTS$M_TAG = x'1FFFFFF8'
      DECLARE LONG CONSTANT BCPTS$M_PARITY = x'20000000'
      DECLARE LONG CONSTANT PR9RR$_BCP2TS = 115  !  Backup cache primary tag array, second half bits
    !   PR9RRBCP2TS_BITS structure fill prefix BCPTS$;
      DECLARE LONG CONSTANT PR9RR$_BCRFR = 116  !  Backup Cache Refresh Register
      DECLARE LONG CONSTANT BCRFR$M_PTS = x'000001F0'
      DECLARE LONG CONSTANT BCRFR$M_BTS = x'0001FE00'
      DECLARE LONG CONSTANT PR9RR$_BCIDX = 117  !  Backup Cache Index Register
      DECLARE LONG CONSTANT BCIDX$M_BTS = x'0001FFC0'
      DECLARE LONG CONSTANT BCIDX$M_PTS = x'000007F0'
      DECLARE LONG CONSTANT PR9RR$_BCSTS = 118  !  Backup Cache Status Register
      DECLARE LONG CONSTANT BCSTS$M_LOCK = x'00000001'
      DECLARE LONG CONSTANT BCSTS$M_BTS_PERR = x'00000002'
      DECLARE LONG CONSTANT BCSTS$M_P1TS_PERR = x'00000004'
      DECLARE LONG CONSTANT BCSTS$M_P2TS_PERR = x'00000008'
      DECLARE LONG CONSTANT BCSTS$M_BUS_ERR = x'00000010'
      DECLARE LONG CONSTANT BCSTS$M_BTS_COMP = x'00020000'
      DECLARE LONG CONSTANT BCSTS$M_BTS_HIT = x'00040000'
      DECLARE LONG CONSTANT BCSTS$M_P1TS_HIT = x'00080000'
      DECLARE LONG CONSTANT BCSTS$M_P2TS_HIT = x'00100000'
      DECLARE LONG CONSTANT BCSTS$M_CMD = x'01E00000'
      DECLARE LONG CONSTANT BCSTS$M_IBUS_CYC = x'02000000'
      DECLARE LONG CONSTANT BCSTS$M_PRED_PAR = x'04000000'
      DECLARE LONG CONSTANT PR9RR$_BCCTL = 119  !  Backup Cache Control Register
      DECLARE LONG CONSTANT BCCTL$M_FRCHIT = x'00000001'
      DECLARE LONG CONSTANT BCCTL$M_ENABTS = x'00000002'
      DECLARE LONG CONSTANT BCCTL$M_ENAPTS = x'00000004'
      DECLARE LONG CONSTANT BCCTL$M_ENARFR = x'00000008'
      DECLARE LONG CONSTANT BCCTL$M_RAMSPD = x'00000010'
      DECLARE LONG CONSTANT BCCTL$K_RAMSPD = 0  !  Use fast RAMs
      DECLARE LONG CONSTANT PR9RR$_BCERR = 120  !  Backup Cache Error Address Register
      DECLARE LONG CONSTANT PR9RR$_BCFBTS = 121  !  Backup Cache Backup Tag Store Flush Register
      DECLARE LONG CONSTANT BCFBTS$K_FLUSH = 0
      DECLARE LONG CONSTANT PR9RR$_BCFPTS = 122  !  Backup Cache Primary Tag Store Flush Register
      DECLARE LONG CONSTANT BCFPTS$K_FLUSH = 0
      DECLARE LONG CONSTANT PR9RR$_VINTSR = 123  !  Vector interface error status register
      DECLARE LONG CONSTANT VINTSR$M_VECTOR_UNIT_ABSENT = x'00000001'
      DECLARE LONG CONSTANT VINTSR$M_VECTOR_UNIT_SERR = x'00000002'
      DECLARE LONG CONSTANT VINTSR$M_VECTOR_UNIT_HERR = x'00000004'
      DECLARE LONG CONSTANT VINTSR$M_VECTL_VIB_SERR = x'00000008'
      DECLARE LONG CONSTANT VINTSR$M_VECTL_VIB_HERR = x'00000010'
      DECLARE LONG CONSTANT VINTSR$M_CCHIP_VIB_SERR = x'00000020'
      DECLARE LONG CONSTANT VINTSR$M_CCHIP_VIB_HERR = x'00000040'
      DECLARE LONG CONSTANT VINTSR$M_BUS_TIMEOUT = x'00000080'
      DECLARE LONG CONSTANT VINTSR$M_VECTOR_MODULE_RESET = x'00000100'
      DECLARE LONG CONSTANT VINTSR$M_DISABLE_VECT_INTF = x'00000200'
      DECLARE LONG CONSTANT PR9RR$_PCTAG = 124  !  Primary Cache Tag Store
      DECLARE LONG CONSTANT PCTAG$M_TAG = x'1FFFF800'
      DECLARE LONG CONSTANT PCTAG$M_PARITY = x'40000000'
      DECLARE LONG CONSTANT PCTAG$M_VALID = x'80000000'
      DECLARE LONG CONSTANT PR9RR$_PCIDX = 125  !  Primary Cache Index Register
      DECLARE LONG CONSTANT PCIDX$M_IDX = x'000007F8'
      DECLARE LONG CONSTANT PR9RR$_PCERR = 126  !  Primary Cache Error Address Register
      DECLARE LONG CONSTANT PR9RR$_PCSTS = 127  !  Primary Cache Status Register
      DECLARE LONG CONSTANT PCSTS$M_FRCHIT = x'00000001'
      DECLARE LONG CONSTANT PCSTS$M_ENAPTS = x'00000002'
      DECLARE LONG CONSTANT PCSTS$M_FLUSH = x'00000004'
      DECLARE LONG CONSTANT PCSTS$M_ENARFR = x'00000008'
      DECLARE LONG CONSTANT PCSTS$M_HIT = x'00000010'
      DECLARE LONG CONSTANT PCSTS$M_INTERRUPT = x'00000020'
      DECLARE LONG CONSTANT PCSTS$M_TRAP2 = x'00000040'
      DECLARE LONG CONSTANT PCSTS$M_TRAP1 = x'00000080'
      DECLARE LONG CONSTANT PCSTS$M_TAG_PERR = x'00000100'
      DECLARE LONG CONSTANT PCSTS$M_DAL_PERR = x'00000200'
      DECLARE LONG CONSTANT PCSTS$M_DATA_PERR = x'00000400'
      DECLARE LONG CONSTANT PCSTS$M_BUSERR = x'00000800'
      DECLARE LONG CONSTANT PCSTS$M_BC_HIT = x'00001000'
      DECLARE LONG CONSTANT PR9RRS_PR9RRDEF = 4
      record PR9RRDEF
         variant
            case
               group PR9RRR_PR9RRICCS_BITS
                   !  Interrupt enable
                  BYTE FILL_1_bits   ! COMMENT ADDED BY SDL - FILL_1_bits contains bits FILL_1 through fill_82
               end group PR9RRR_PR9RRICCS_BITS
            case
               group PR9RRR_PR9RRRXCS_BITS
                   !  Interrupt enable
                   !  Receiver done
                  BYTE FILL_1_bits   ! COMMENT ADDED BY SDL - FILL_1_bits contains bits FILL_1 through RX_DONE
               end group PR9RRR_PR9RRRXCS_BITS
            case
               group PR9RRR_PR9RRRXDB_BITS
                   !  Received data
                   !  Break or CTRL/P received
                   !  Framing error
                   !  Overrun error
                   !  Error
                  WORD DATA_bits   ! COMMENT ADDED BY SDL - DATA_bits contains bits DATA through ERR_9RR
               end group PR9RRR_PR9RRRXDB_BITS
            case
               group PR9RRR_PR9RRTXCS_BITS
                   !  Transmit break
                   !  Loopback
                   !  Interrupt enable
                   !  Transmitter ready
                  BYTE XMIT_BRK_bits   ! COMMENT ADDED BY SDL - XMIT_BRK_bits contains bits XMIT_BRK through TX_RDY
               end group PR9RRR_PR9RRTXCS_BITS
            case
               group PR9RRR_PR9RRTXDB_BITS
                   !  Data to transmit
                  BYTE DATA_bits   ! COMMENT ADDED BY SDL - DATA_bits contains bits DATA through DATA
               end group PR9RRR_PR9RRTXDB_BITS
            case
               group PR9RRR_PR9RRACCS_BITS
                   !  Vector unit present
                   !  F-Chip present
                   !  Write even parity
                  LONG VECTOR_PRESENT_bits   ! COMMENT ADDED BY SDL - VECTOR_PRESENT_bits contains bits VECTOR_PRESENT through  &
 ! WRITE_EVEN_PARITY
               end group PR9RRR_PR9RRACCS_BITS
            case
               group PR9RRR_PR9RRSAVPSL_BITS
                   !  Halt code
                   !  Saved PSL invalid
                   !  Saved MAPEN
                  WORD FILL_1_bits   ! COMMENT ADDED BY SDL - FILL_1_bits contains bits FILL_1 through MAPEN
               end group PR9RRR_PR9RRSAVPSL_BITS
            case
               group PR9RRR_PR9RRSID_BITS
                   !   9RR chip µcode rev level 
                  BYTE RVAXREV_bits   ! COMMENT ADDED BY SDL - RVAXREV_bits contains bits RVAXREV through RVAXREV
               end group PR9RRR_PR9RRSID_BITS
    !  XSID (SYS_TYPE) Register bits
            case
               group PR9RRR_PR9RRXSID_BITS
                   !  Architectural ID (=1)
                   !  System Variant (=1)
                   !  XRP firmware revision level 
                  LONG ARCH_bits   ! COMMENT ADDED BY SDL - ARCH_bits contains bits ARCH through XRPFWREV
               end group PR9RRR_PR9RRXSID_BITS
            case
               group PR9RRR_PR9RRBCBTS_BITS
                   !  Four valid bits
                   !  Cache tag
                   !  Parity bit
                  LONG FILL_1_bits   ! COMMENT ADDED BY SDL - FILL_1_bits contains bits FILL_1 through fill_83
               end group PR9RRR_PR9RRBCBTS_BITS
            case
               group PR9RRR_PR9RRBCP1TS_BITS
                   !  Valid bit
                   !  Cache tag
                   !  Parity bit
                  LONG FILL_1_bits   ! COMMENT ADDED BY SDL - FILL_1_bits contains bits FILL_1 through fill_84
               end group PR9RRR_PR9RRBCP1TS_BITS
    !   end PR9RRBCP2TS_BITS; /* Bit definitions are the same as PR9RR$_BCP1TS
            case
               group PR9RRR_PR9RRBCRFR_BITS
                   !  PTS refresh index
                   !  BTS refresh index
                  LONG FILL_1_bits   ! COMMENT ADDED BY SDL - FILL_1_bits contains bits FILL_1 through fill_85
               end group PR9RRR_PR9RRBCRFR_BITS
            case
               group PR9RRR_PR9RRBCIDX_BITS
                  variant
                  case
                     group BCIDX$R_PR9RRBCIDX_BTS
                         !  BTS index
                        LONG FILL_1_bits   ! COMMENT ADDED BY SDL - FILL_1_bits contains bits FILL_1 through fill_86
                     end group BCIDX$R_PR9RRBCIDX_BTS
                  case
                     group BCIDX$R_PR9RRBCIDX_PTS
                         !  PTS index
                        WORD FILL_2_bits   ! COMMENT ADDED BY SDL - FILL_2_bits contains bits FILL_2 through fill_87
                     end group BCIDX$R_PR9RRBCIDX_PTS
                  end variant
               end group PR9RRR_PR9RRBCIDX_BITS
            case
               group PR9RRR_PR9RRBCSTS_BITS
                   !  Error lock
                   !  BTS parity error
                   !  P1TS parity error
                   !  P2TS parity error
                   !  Bus error
                   !  BTS compare
                   !  BTS hit
                   !  P1TS hit
                   !  P2TS hit
                   !  Last DAL command
                   !  I-bus cycle
                   !  Predicted parity
                  LONG LOCK_bits   ! COMMENT ADDED BY SDL - LOCK_bits contains bits LOCK through fill_88
               end group PR9RRR_PR9RRBCSTS_BITS
            case
               group PR9RRR_PR9RRBCCTL_BITS
                   !  Force hit
                   !  Enable BTS (cache on)
                   !  Enable PTS (filter on)
                   !  Enable refresh
                   !  Cache RAM speed (0 = 1 cycle, 1 = 2 cycles)
                  BYTE FRCHIT_bits   ! COMMENT ADDED BY SDL - FRCHIT_bits contains bits FRCHIT through fill_89
               end group PR9RRR_PR9RRBCCTL_BITS
            case
               group PR9RRR_PR9RRVINTSR_BITS
                   !  Vector unit absent
                   !  Vector soft error
                   !  Vector soft error
                   !  Vector soft error
                   !  Vector soft error
                   !  Vector soft error
                   !  Vector soft error
                   !  Bus timeout during vector transfer
                   !  Vector module reset
                   !  Vector module reset
                  WORD VECTOR_UNIT_ABSENT_bits   ! COMMENT ADDED BY SDL - VECTOR_UNIT_ABSENT_bits contains bits  &
 ! VECTOR_UNIT_ABSENT through fill_90
               end group PR9RRR_PR9RRVINTSR_BITS
            case
               group PR9RRR_PR9RRPCTAG_BITS
                   !  Cache tag
                   !  Parity bit
                   !  Valid bit
                  LONG FILL_1_bits   ! COMMENT ADDED BY SDL - FILL_1_bits contains bits FILL_1 through VALID
               end group PR9RRR_PR9RRPCTAG_BITS
            case
               group PR9RRR_PR9RRPCIDX_BITS
                   !  Tag index
                  WORD FILL_1_bits   ! COMMENT ADDED BY SDL - FILL_1_bits contains bits FILL_1 through fill_91
               end group PR9RRR_PR9RRPCIDX_BITS
            case
               group PR9RRR_PR9RRPCSTS_BITS
                   !  Force hit
                   !  Enable tag store (cache on)
                   !  Flush cache
                   !  Enable refresh
                   !  Reference hit
                   !  Error interrupt pending
                   !  Double error lock
                   !  Error lock
                   !  Tag parity error
                   !  DAL data parity error
                   !  Data parity error
                   !  Bus error
                   !  Reference hit in Bcache
                  WORD FRCHIT_bits   ! COMMENT ADDED BY SDL - FRCHIT_bits contains bits FRCHIT through fill_92
               end group PR9RRR_PR9RRPCSTS_BITS
         end variant
      end record PR9RRDEF