%IF %DECLARED ( %BASIC$QUADWORD_DECLARED ) = 0 %THEN
	RECORD BASIC$QUADWORD
		LONG FILL ( 2 )
	END RECORD
    %LET %BASIC$QUADWORD_DECLARED = 1
    %END %IF
    %IF %DECLARED ( %BASIC$OCTAWORD_DECLARED ) = 0 %THEN
	RECORD BASIC$OCTAWORD
		LONG FILL ( 4 )
	END RECORD
    %LET %BASIC$OCTAWORD_DECLARED = 1
    %END %IF
    %IF %DECLARED ( %BASIC$F_FLOATING_COMPLEX_DECL ) = 0 %THEN
    	RECORD BASIC$F_FLOATING_COMPLEX
    		SINGLE REAL_PART
    		SINGLE IMAGINARY_PART
    	END RECORD
    %LET %BASIC$F_FLOATING_COMPLEX_DECL = 1
    %END %IF
    %IF %DECLARED ( %BASIC$D_FLOATING_COMPLEX_DECL ) = 0 %THEN
    	RECORD BASIC$D_FLOATING_COMPLEX
    		DOUBLE REAL_PART
    		DOUBLE IMAGINARY_PART
    	END RECORD
    %LET %BASIC$D_FLOATING_COMPLEX_DECL = 1
    %END %IF
    %IF %DECLARED ( %BASIC$G_FLOATING_COMPLEX_DECL ) = 0 %THEN
    	RECORD BASIC$G_FLOATING_COMPLEX
    		GFLOAT REAL_PART
    		GFLOAT IMAGINARY_PART
    	END RECORD
    %LET %BASIC$G_FLOATING_COMPLEX_DECL = 1
    %END %IF
    %IF %DECLARED ( %BASIC$H_FLOATING_COMPLEX_DECL ) = 0 %THEN
    	RECORD BASIC$H_FLOATING_COMPLEX
    		HFLOAT REAL_PART
    		HFLOAT IMAGINARY_PART
    	END RECORD
    %LET %BASIC$H_FLOATING_COMPLEX_DECL = 1
    %END %IF
    
    
      DECLARE LONG CONSTANT PR8SS$_IPIR = 22  !  Interprocessor Interrupt Reg.
      DECLARE LONG CONSTANT PR8SS$_NICR = 25  !  Interval Clock Next Interval Register
      DECLARE LONG CONSTANT PR8SS$_ICR = 26  !  Interval Clock Interval Count Register
      DECLARE LONG CONSTANT PR8SS$_TODR = 27  !  Time Of Day Register
      DECLARE LONG CONSTANT PR8SS$_TBDR = 36  !  Translation Buffer Disable Register
      DECLARE LONG CONSTANT PR8SS$_CADR = 37  !  Cache Disable Register
      DECLARE LONG CONSTANT PR8SS$_MCESR = 38  !  Machine Check Error Summary Register
      DECLARE LONG CONSTANT PR8SS$_ACCS = 40  !  Floating Point Accellerator Register
      DECLARE LONG CONSTANT PR8SS$_WCSA = 44  !  WCS Address Register
      DECLARE LONG CONSTANT PR8SS$_WCSD = 45  !  WCS Data Register
      DECLARE LONG CONSTANT PR8SS$_WCSC = 46  !  WCS Cam Register
      DECLARE LONG CONSTANT PR8SS$_PME = 61  !  Performance Monitor Enable
      DECLARE LONG CONSTANT PR8SS$_RXCS1 = 80  !  Serial Line 1 Receive CSR
      DECLARE LONG CONSTANT PR8SS$_RXDB1 = 81  !  Serial Line 1 Receive Data Buffer
      DECLARE LONG CONSTANT PR8SS$_TXCS1 = 82  !  Serial Line 1 Transmit CSR
      DECLARE LONG CONSTANT PR8SS$_TXDB1 = 83  !  Serial Line 1 Transmit Data Buffer
      DECLARE LONG CONSTANT PR8SS$_RXCS2 = 84  !  Serial Line 2 Receive CSR
      DECLARE LONG CONSTANT PR8SS$_RXDB2 = 85  !  Serial Line 2 Receive Data Buffer
      DECLARE LONG CONSTANT PR8SS$_TXCS2 = 86  !  Serial Line 2 Transmit CSR
      DECLARE LONG CONSTANT PR8SS$_TXDB2 = 87  !  Serial Line 2 Transmit Data Buffer
      DECLARE LONG CONSTANT PR8SS$_RXCS3 = 88  !  Serial Line 3 Receive CSR
      DECLARE LONG CONSTANT PR8SS$_RXDB3 = 89  !  Serial Line 3 Receive Data Buffer
      DECLARE LONG CONSTANT PR8SS$_TXCS3 = 90  !  Serial Line 3 Transmit CSR
      DECLARE LONG CONSTANT PR8SS$_TXDB3 = 91  !  Serial Line 3 Transmit Data Buffer
      DECLARE LONG CONSTANT PR8SS$_RXCD = 92  !  Receive Console Data Register
      DECLARE LONG CONSTANT PR8SS$_CACHEX = 93  !  Cache Invalidate Register
      DECLARE LONG CONSTANT PR8SS$_BINID = 94  !  BI Node ID Register
      DECLARE LONG CONSTANT PR8SS$_BIINIT = 95  !  BI Init Nodes Register
      DECLARE LONG CONSTANT PR8SS$M_SID_SECP = x'00000100'
      DECLARE LONG CONSTANT PR8SS$M_RXCS_IE = x'00000040'
      DECLARE LONG CONSTANT PR8SS$M_RXCS_DONE = x'00000080'
      DECLARE LONG CONSTANT PR8SS$M_RXDB_ERR = x'00008000'
      DECLARE LONG CONSTANT PR8SS$M_TXCS_IE = x'00000040'
      DECLARE LONG CONSTANT PR8SS$M_TXCS_RDY = x'00000080'
      DECLARE LONG CONSTANT PR8SS$M_TXCS_BRE = x'00000100'
      DECLARE LONG CONSTANT PR8SS$_BAUD300 = 0  !  Baud Rate of 300
      DECLARE LONG CONSTANT PR8SS$_BAUD600 = 1  !  Baud Rate of 600
      DECLARE LONG CONSTANT PR8SS$_BAUD1200 = 2  !  Baud Rate of 1200
      DECLARE LONG CONSTANT PR8SS$_BAUD2400 = 3  !  Baud Rate of 2400
      DECLARE LONG CONSTANT PR8SS$_BAUD4800 = 4  !  Baud Rate of 4800
      DECLARE LONG CONSTANT PR8SS$_BAUD9600 = 5  !  Baud Rate of 9600
      DECLARE LONG CONSTANT PR8SS$_BAUD19200 = 6  !  Baud Rate of 19200
      DECLARE LONG CONSTANT PR8SS$_BAUD38400 = 7  !  Baud Rate of 38400
      DECLARE LONG CONSTANT PR8SS$_BOOTCPU = 2  !  Boot CPU Command
      DECLARE LONG CONSTANT PR8SS$_CLRWARM = 3  !  Clear Warm-start Flag
      DECLARE LONG CONSTANT PR8SS$_CLRCOLD = 4  !  Clear Cold-start Flag
      DECLARE LONG CONSTANT PR8SS$M_CADR_D = x'00000001'
      DECLARE LONG CONSTANT PR8SS$M_CADR_H = x'00000002'
      DECLARE LONG CONSTANT PR8SS$M_RXCD_BSY = x'00008000'
      DECLARE LONG CONSTANT PR8SS$S_PR8SSDEF = 4
      record PR8SSDEF
         variant
            case
               group PR8SS$R_PR8SSSID_BITS  !  Read only SID register
                   !  Ucode Revision Level
                   !  Secondary Patch Bit
                   !  Patch Rev Level
                   !  CPU Rev level
                   !  1=8250 (KA825), 0=8200 (KA820) 
                   !  CPU Type Code
                  LONG SID_UCREV_bits   ! COMMENT ADDED BY SDL - SID_UCREV_bits contains bits SID_UCREV through SID_TYPE
               end group PR8SS$R_PR8SSSID_BITS
            case
               group PR8SS$R_PR8SSRXCS_BITS  !  Console RCV CSR
                   !  Interrupt Enable
                   !  1=> Char. received
                  BYTE FILL_1_bits   ! COMMENT ADDED BY SDL - FILL_1_bits contains bits FILL_1 through RXCS_DONE
               end group PR8SS$R_PR8SSRXCS_BITS
            case
               group PR8SS$R_PR8SSRXDB_BITS  !  Console RCV Data Register
                   !  Received Data
                   !  Error
                  WORD RXDB_DATA_bits   ! COMMENT ADDED BY SDL - RXDB_DATA_bits contains bits RXDB_DATA through RXDB_ERR
               end group PR8SS$R_PR8SSRXDB_BITS
            case
               group PR8SS$R_PR8SSTXCS_BITS  !  Console Transmit CSR
                   !  Interrupt Enable
                   !  Ready
                   !  (WO) Baud Rate Enable
                   !  Baud Rate
    !  Values to set baud rates
                  WORD FILL_3_bits   ! COMMENT ADDED BY SDL - FILL_3_bits contains bits FILL_3 through fill_77
               end group PR8SS$R_PR8SSTXCS_BITS
            case
               group PR8SS$R_PR8SSTXDB_BITS  !  Console Transmit Data Register
                   !  Data to Transmit
                   !  ID - Destination of
    !   transmitted data -
    !   0=>UART0, F=>Console
    !   command
    !  Possible Console Commands
                  WORD TXDB_DATA_bits   ! COMMENT ADDED BY SDL - TXDB_DATA_bits contains bits TXDB_DATA through fill_78
               end group PR8SS$R_PR8SSTXDB_BITS
            case
               group PR8SS$R_PR8SSCADR_BITS  !  Cache Disable Register
                   !  Disable Cache
                   !  Force 100% Cache Hits
                  BYTE CADR_D_bits   ! COMMENT ADDED BY SDL - CADR_D_bits contains bits CADR_D through fill_79
               end group PR8SS$R_PR8SSCADR_BITS
            case
               group PR8SS$R_PR8SSWCSA_BITS  !  WCS  ( Patch ) Address Reg
                   !  High Order Data Bits
                   !  Ram Address
                  LONG WCSA_DATA_bits   ! COMMENT ADDED BY SDL - WCSA_DATA_bits contains bits WCSA_DATA through WCSA_RAMADR
               end group PR8SS$R_PR8SSWCSA_BITS
            case
               group PR8SS$R_PR8SSWCSC_BITS  !  WCS  ( Patch ) CAM Reg
                   !  Cam Address
                   !  Rom Address
                  LONG FILL_6_bits   ! COMMENT ADDED BY SDL - FILL_6_bits contains bits FILL_6 through WCSC_ROMADR
               end group PR8SS$R_PR8SSWCSC_BITS
            case
               group PR8SS$R_PR8SSRXCD_BITS  !  Receive Console Data Register
                   !  Received Data
                   !  Sender's Node ID
                   !  Set=>Data has been received
                  WORD RXCD_DATA_bits   ! COMMENT ADDED BY SDL - RXCD_DATA_bits contains bits RXCD_DATA through RXCD_BSY
               end group PR8SS$R_PR8SSRXCD_BITS
            case
               group PR8SS$R_PR8SSCACHEX_BITS  !  Cache Invalidate Register
                   !  Physical Page Number
                  LONG FILL_8_bits   ! COMMENT ADDED BY SDL - FILL_8_bits contains bits FILL_8 through fill_80
               end group PR8SS$R_PR8SSCACHEX_BITS
            case
               group PR8SS$R_PR8SSBINID_BITS  !  BI Node ID Register
                   !  BI Node ID this node
                  BYTE BINID_NID_bits   ! COMMENT ADDED BY SDL - BINID_NID_bits contains bits BINID_NID through fill_81
               end group PR8SS$R_PR8SSBINID_BITS
         end variant
      end record PR8SSDEF