%IF %DECLARED ( %BASIC$QUADWORD_DECLARED ) = 0 %THEN RECORD BASIC$QUADWORD LONG FILL ( 2 ) END RECORD %LET %BASIC$QUADWORD_DECLARED = 1 %END %IF %IF %DECLARED ( %BASIC$OCTAWORD_DECLARED ) = 0 %THEN RECORD BASIC$OCTAWORD LONG FILL ( 4 ) END RECORD %LET %BASIC$OCTAWORD_DECLARED = 1 %END %IF %IF %DECLARED ( %BASIC$F_FLOATING_COMPLEX_DECL ) = 0 %THEN RECORD BASIC$F_FLOATING_COMPLEX SINGLE REAL_PART SINGLE IMAGINARY_PART END RECORD %LET %BASIC$F_FLOATING_COMPLEX_DECL = 1 %END %IF %IF %DECLARED ( %BASIC$D_FLOATING_COMPLEX_DECL ) = 0 %THEN RECORD BASIC$D_FLOATING_COMPLEX DOUBLE REAL_PART DOUBLE IMAGINARY_PART END RECORD %LET %BASIC$D_FLOATING_COMPLEX_DECL = 1 %END %IF %IF %DECLARED ( %BASIC$G_FLOATING_COMPLEX_DECL ) = 0 %THEN RECORD BASIC$G_FLOATING_COMPLEX GFLOAT REAL_PART GFLOAT IMAGINARY_PART END RECORD %LET %BASIC$G_FLOATING_COMPLEX_DECL = 1 %END %IF %IF %DECLARED ( %BASIC$H_FLOATING_COMPLEX_DECL ) = 0 %THEN RECORD BASIC$H_FLOATING_COMPLEX HFLOAT REAL_PART HFLOAT IMAGINARY_PART END RECORD %LET %BASIC$H_FLOATING_COMPLEX_DECL = 1 %END %IF DECLARE LONG CONSTANT PR60$_CPUID = 14 ! Hardware CPU id DECLARE LONG CONSTANT PR60$_WHAMI = 15 ! Software CPU id DECLARE LONG CONSTANT PR60$_CADR = 37 ! CACHE DISABLE DECLARE LONG CONSTANT PR60$_MSER = 39 ! MEMORY SYSTEM ERROR DECLARE LONG CONSTANT PR60$_SAVGPR = 41 ! Console halt code DECLARE LONG CONSTANT PR60$_SAVPC = 42 ! CONSOLE SAVED PC REGISTER DECLARE LONG CONSTANT PR60$_SAVPSL = 43 ! CONSOLE SAVED PSL REGISTER DECLARE LONG CONSTANT PR60$S_PR60SID = 4 record PR60SID BYTE PR60$B_SID_CVAXREV ! CVAX chip microcode revision level WORD PR60$W_SID_RSVD BYTE PR60$B_SID_TYPE ! Processor type ( 10 = CVAX ) end record PR60SID ! System ID Extension Longword DECLARE LONG CONSTANT PR60$S_PR60XSID = 4 record PR60XSID WORD PR60$W_XSID_FILL1 ! Reserved BYTE PR60$B_XSID_ROMVER ! Boot ROM version BYTE PR60$B_XSID_SYSCODE ! System code. 3 ( Firefox ) end record PR60XSID ! Cache Disable register DECLARE LONG CONSTANT PR60$M_CADR_DIA = x'00000001' DECLARE LONG CONSTANT PR60$M_CADR_WW = x'00000002' DECLARE LONG CONSTANT PR60$M_CADR_DSTREAM = x'00000010' DECLARE LONG CONSTANT PR60$M_CADR_ISTREAM = x'00000020' DECLARE LONG CONSTANT PR60$M_CADR_SET1 = x'00000040' DECLARE LONG CONSTANT PR60$M_CADR_SET2 = x'00000080' DECLARE LONG CONSTANT PR60$S_PR60CADR = 1 record PR60CADR ! Diagnostic mode ! Write wrong parity ! Filler ! Data stream enabled ! Instruction stream enabled ! Set 1 enabled ! Set 2 enabled BYTE CADR_DIA_bits ! COMMENT ADDED BY SDL - CADR_DIA_bits contains bits CADR_DIA through CADR_SET2 end record PR60CADR ! Memory System Error Register DECLARE LONG CONSTANT PR60$M_MSER_TAG = x'00000001' DECLARE LONG CONSTANT PR60$M_MSER_DATA = x'00000002' DECLARE LONG CONSTANT PR60$M_MSER_MCC = x'00000010' DECLARE LONG CONSTANT PR60$M_MSER_MCD = x'00000020' DECLARE LONG CONSTANT PR60$M_MSER_DAL = x'00000040' DECLARE LONG CONSTANT PR60$M_MSER_HM = x'00000080' DECLARE LONG CONSTANT PR60$S_PR60MSER = 1 record PR60MSER ! Tag error ! Data error ! Filler ! Machine check - cache parity ! Machine check - DAL parity ! DAL parity error ! Hit/miss BYTE MSER_TAG_bits ! COMMENT ADDED BY SDL - MSER_TAG_bits contains bits MSER_TAG through MSER_HM end record PR60MSER ! Interval Control Clock and Status register DECLARE LONG CONSTANT PR60$M_ICCS_IE = x'00000040' DECLARE LONG CONSTANT PR60$S_PR60ICCS = 1 record PR60ICCS ! Filler ! Interrupt enable BYTE ICCS_FILL_bits ! COMMENT ADDED BY SDL - ICCS_FILL_bits contains bits ICCS_FILL through fill_65 end record PR60ICCS