%IF %DECLARED ( %BASIC$QUADWORD_DECLARED ) = 0 %THEN RECORD BASIC$QUADWORD LONG FILL ( 2 ) END RECORD %LET %BASIC$QUADWORD_DECLARED = 1 %END %IF %IF %DECLARED ( %BASIC$OCTAWORD_DECLARED ) = 0 %THEN RECORD BASIC$OCTAWORD LONG FILL ( 4 ) END RECORD %LET %BASIC$OCTAWORD_DECLARED = 1 %END %IF %IF %DECLARED ( %BASIC$F_FLOATING_COMPLEX_DECL ) = 0 %THEN RECORD BASIC$F_FLOATING_COMPLEX SINGLE REAL_PART SINGLE IMAGINARY_PART END RECORD %LET %BASIC$F_FLOATING_COMPLEX_DECL = 1 %END %IF %IF %DECLARED ( %BASIC$D_FLOATING_COMPLEX_DECL ) = 0 %THEN RECORD BASIC$D_FLOATING_COMPLEX DOUBLE REAL_PART DOUBLE IMAGINARY_PART END RECORD %LET %BASIC$D_FLOATING_COMPLEX_DECL = 1 %END %IF %IF %DECLARED ( %BASIC$G_FLOATING_COMPLEX_DECL ) = 0 %THEN RECORD BASIC$G_FLOATING_COMPLEX GFLOAT REAL_PART GFLOAT IMAGINARY_PART END RECORD %LET %BASIC$G_FLOATING_COMPLEX_DECL = 1 %END %IF %IF %DECLARED ( %BASIC$H_FLOATING_COMPLEX_DECL ) = 0 %THEN RECORD BASIC$H_FLOATING_COMPLEX HFLOAT REAL_PART HFLOAT IMAGINARY_PART END RECORD %LET %BASIC$H_FLOATING_COMPLEX_DECL = 1 %END %IF DECLARE LONG CONSTANT PR1701$K_REVISION = 1 ! Revision number of this file ! In the definitions below, registers are annotated with one of the following ! symbols: ! ! RW - The register may be read and written ! RO - The register may only be read ! WO - The register may only be written ! ! For RO and WO registers, all bits and fields within the register are also ! read-only or write-only. For RW registers, each bit or field within ! the register is annotated with one of the following: ! ! RW - The bit/field may be read and written ! RO - The bit/field may be read; writes are ignored ! WO - The bit/field may be written; reads return an UNPREDICTABLE result. ! WZ - The bit/field may be written; reads return a 0 ! WC - The bit/field may be read; writes cause state to clear ! RC - The bit/field may be read, which also causes state to clear; writes are ignored DECLARE LONG CONSTANT PR1701$_IPL = 18 ! Interrupt Priority Level DECLARE LONG CONSTANT PR1701$_ICCS = 24 ! Interval Clock Control/Status DECLARE LONG CONSTANT PR1701$_NICR = 25 ! Next Interval Count DECLARE LONG CONSTANT PR1701$_ICR = 26 ! Interval Count DECLARE LONG CONSTANT PR1701$_TODR = 27 ! Time Of Year Register ( RW ) DECLARE LONG CONSTANT PR1701$_MCESR = 38 ! Machine check error register ( WO ) DECLARE LONG CONSTANT PR1701$_SAVPC = 42 ! Console saved PC ( RO ) DECLARE LONG CONSTANT PR1701$_SAVPSL = 43 ! Console saved PSL ( RO ) DECLARE LONG CONSTANT PR17_SAVPSL$M_PSL_LO = x'000000FF' DECLARE LONG CONSTANT PR17_SAVPSL$M_HALTCODE = x'00003F00' DECLARE LONG CONSTANT PR17_SAVPSL$K_HALT_HLTPIN = 2 ! HALT_L pin asserted DECLARE LONG CONSTANT PR17_SAVPSL$K_HALT_PWRUP = 3 ! Initial powerup DECLARE LONG CONSTANT PR17_SAVPSL$K_HALT_INTSTK = 4 ! Interrupt stack not valid DECLARE LONG CONSTANT PR17_SAVPSL$K_HALT_DOUBLE = 5 ! Machine check during exception processing DECLARE LONG CONSTANT PR17_SAVPSL$K_HALT_HLTINS = 6 ! Halt instruction in kernel mode DECLARE LONG CONSTANT PR17_SAVPSL$K_HALT_ILLVEC = 7 ! Illegal SCB vector ( bits<1:0>=11 ) DECLARE LONG CONSTANT PR17_SAVPSL$K_HALT_WCSVEC = 8 ! WCS SCB vector ( bits<1:0>=10 ) DECLARE LONG CONSTANT PR17_SAVPSL$K_HALT_CHMFI = 10 ! CHMx on interrupt stack DECLARE LONG CONSTANT PR17_SAVPSL$K_HALT_IE0 = 16 ! ACV/TNV during machine check processing DECLARE LONG CONSTANT PR17_SAVPSL$K_HALT_IE1 = 17 ! ACV/TNV during KSNV processing DECLARE LONG CONSTANT PR17_SAVPSL$K_HALT_IE2 = 18 ! Machine check during machine check processing DECLARE LONG CONSTANT PR17_SAVPSL$K_HALT_IE3 = 19 ! Machine check during KSNV processing DECLARE LONG CONSTANT PR17_SAVPSL$K_HALT_IE_PSL_101 = 25 ! PSL<26:24>=101 during interrupt or exception DECLARE LONG CONSTANT PR17_SAVPSL$K_HALT_IE_PSL_110 = 26 ! PSL<26:24>=110 during interrupt or exception DECLARE LONG CONSTANT PR17_SAVPSL$K_HALT_IE_PSL_111 = 27 ! PSL<26:24>=111 during interrupt or exception DECLARE LONG CONSTANT PR17_SAVPSL$K_HALT_REI_PSL_101 = 29 ! PSL<26:24>=101 during REI DECLARE LONG CONSTANT PR17_SAVPSL$K_HALT_REI_PSL_110 = 30 ! PSL<26:24>=110 during REI DECLARE LONG CONSTANT PR17_SAVPSL$K_HALT_REI_PSL_111 = 31 ! PSL<26:24>=111 during REI DECLARE LONG CONSTANT PR17_SAVPSL$M_INVALID = x'00004000' DECLARE LONG CONSTANT PR17_SAVPSL$M_MAPEN = x'00008000' DECLARE LONG CONSTANT PR17_SAVPSL$M_PSL_HI = x'FFFF0000' DECLARE LONG CONSTANT PR1701$_IORESET = 55 ! I/O system reset register ( WO ) DECLARE LONG CONSTANT PR1701$_PME = 61 ! Performance monitoring enable ( RW ) ! System-level required registers. DECLARE LONG CONSTANT PR1701$_IAK14 = 64 ! Level 14 interrupt acknowledge ( RO ) DECLARE LONG CONSTANT PR1701$_IAK15 = 65 ! Level 15 interrupt acknowledge ( RO ) DECLARE LONG CONSTANT PR1701$_IAK16 = 66 ! Level 16 interrupt acknowledge ( RO ) DECLARE LONG CONSTANT PR1701$_IAK17 = 67 ! Level 17 interrupt acknowledge ( RO ) DECLARE LONG CONSTANT IAK$M_IPL17 = x'00000001' DECLARE LONG CONSTANT IAK$M_PR = x'00000002' DECLARE LONG CONSTANT IAK$M_SCB_OFFSET = x'0000FFFC' DECLARE LONG CONSTANT PR1701$_CWB = 68 ! Clear write buffers ( RW ) DECLARE LONG CONSTANT PR1701$_LMBOX = 121 ! Laser Mailbox ! Ebox registers. DECLARE LONG CONSTANT PR1701$_INTSYS = 122 ! Interrupt system status register ( RW ) DECLARE LONG CONSTANT INTSYS$M_ICCS6 = x'00000001' DECLARE LONG CONSTANT INTSYS$M_SISR = x'0000FFFE' DECLARE LONG CONSTANT INTSYS$M_INT_ID = x'001F0000' DECLARE LONG CONSTANT INTSYS$K_INT_ID_HALT = 31 ! Halt pin DECLARE LONG CONSTANT INTSYS$K_INT_ID_PWRFL = 30 ! Power fail DECLARE LONG CONSTANT INTSYS$K_INT_ID_H_ERR = 29 ! Hard error DECLARE LONG CONSTANT INTSYS$K_INT_ID_INT_TIM = 28 ! Interval timer DECLARE LONG CONSTANT INTSYS$K_INT_ID_PMON = 27 ! Performance monitor DECLARE LONG CONSTANT INTSYS$K_INT_ID_S_ERR = 26 ! Soft error DECLARE LONG CONSTANT INTSYS$K_INT_ID_IRQ3 = 23 ! IPL 17 device interrupt DECLARE LONG CONSTANT INTSYS$K_INT_ID_IRQ2 = 22 ! IPL 16 device interrupt DECLARE LONG CONSTANT INTSYS$K_INT_ID_IRQ1 = 21 ! IPL 15 device interrupt DECLARE LONG CONSTANT INTSYS$K_INT_ID_IRQ0 = 20 ! IPL 14 device interrupt DECLARE LONG CONSTANT INTSYS$K_INT_ID_SISR15 = 15 ! SISR<15> DECLARE LONG CONSTANT INTSYS$K_INT_ID_SISR14 = 14 ! SISR<14> DECLARE LONG CONSTANT INTSYS$K_INT_ID_SISR13 = 13 ! SISR<13> DECLARE LONG CONSTANT INTSYS$K_INT_ID_SISR12 = 12 ! SISR<12> DECLARE LONG CONSTANT INTSYS$K_INT_ID_SISR11 = 11 ! SISR<11> DECLARE LONG CONSTANT INTSYS$K_INT_ID_SISR10 = 10 ! SISR<10> DECLARE LONG CONSTANT INTSYS$K_INT_ID_SISR9 = 9 ! SISR<9> DECLARE LONG CONSTANT INTSYS$K_INT_ID_SISR8 = 8 ! SISR<8> DECLARE LONG CONSTANT INTSYS$K_INT_ID_SISR7 = 7 ! SISR<7> DECLARE LONG CONSTANT INTSYS$K_INT_ID_SISR6 = 6 ! SISR<6> DECLARE LONG CONSTANT INTSYS$K_INT_ID_SISR5 = 5 ! SISR<5> DECLARE LONG CONSTANT INTSYS$K_INT_ID_SISR4 = 4 ! SISR<4> DECLARE LONG CONSTANT INTSYS$K_INT_ID_SISR3 = 3 ! SISR<3> DECLARE LONG CONSTANT INTSYS$K_INT_ID_SISR2 = 2 ! SISR<2> DECLARE LONG CONSTANT INTSYS$K_INT_ID_SISR1 = 1 ! SISR<1> DECLARE LONG CONSTANT INTSYS$K_INT_ID_NO_INT = 0 ! No interrupt DECLARE LONG CONSTANT INTSYS$M_INT_TIM_RESET = x'01000000' DECLARE LONG CONSTANT INTSYS$M_S_ERR_RESET = x'08000000' DECLARE LONG CONSTANT INTSYS$M_PMON_RESET = x'10000000' DECLARE LONG CONSTANT INTSYS$M_H_ERR_RESET = x'20000000' DECLARE LONG CONSTANT INTSYS$M_PWRFL_RESET = x'40000000' DECLARE LONG CONSTANT INTSYS$M_HALT_RESET = x'80000000' DECLARE LONG CONSTANT PR1701$_PMFCNT = 123 ! Performance monitoring facility count register ( RW ) DECLARE LONG CONSTANT PMFCNT$M_PMCTR0 = x'0000FFFF' DECLARE LONG CONSTANT PMFCNT$M_PMCTR1 = x'FFFF0000' DECLARE LONG CONSTANT PR1701$_PCSCR = 124 ! Patchable control store control register ( WO ) DECLARE LONG CONSTANT PCSCR$M_PAR_PORT_DIS = x'00000100' DECLARE LONG CONSTANT PCSCR$M_PCS_ENB = x'00000200' DECLARE LONG CONSTANT PCSCR$M_PCS_WRITE = x'00000400' DECLARE LONG CONSTANT PCSCR$M_RWL_SHIFT = x'00000800' DECLARE LONG CONSTANT PCSCR$M_DATA = x'00001000' DECLARE LONG CONSTANT PCSCR$M_NONSTANDARD_PATCH = x'00800000' DECLARE LONG CONSTANT PCSCR$M_PATCH_REV = x'1F000000' DECLARE LONG CONSTANT PR1701$_ECR = 125 ! Ebox control register ( RW ) DECLARE LONG CONSTANT ECR$M_VECTOR_PRESENT = x'00000001' DECLARE LONG CONSTANT ECR$M_FBOX_ENABLE = x'00000002' DECLARE LONG CONSTANT ECR$M_TIMEOUT_EXT = x'00000004' DECLARE LONG CONSTANT ECR$M_FBOX_ST4_BYPASS_ENABLE = x'00000008' DECLARE LONG CONSTANT ECR$M_TIMEOUT_OCCURRED = x'00000010' DECLARE LONG CONSTANT ECR$M_TIMEOUT_TEST = x'00000020' DECLARE LONG CONSTANT ECR$M_TIMEOUT_CLOCK = x'00000040' DECLARE LONG CONSTANT ECR$M_FBOX_TEST_ENABLE = x'00002000' DECLARE LONG CONSTANT ECR$M_PMF_ENABLE = x'00010000' DECLARE LONG CONSTANT ECR$M_PMF_PMUX = x'00060000' DECLARE LONG CONSTANT ECR$K_PMUX_IBOX = 0 ! Select Ibox DECLARE LONG CONSTANT ECR$K_PMUX_EBOX = 1 ! Select Ebox DECLARE LONG CONSTANT ECR$K_PMUX_MBOX = 2 ! Select Mbox DECLARE LONG CONSTANT ECR$K_PMUX_CBOX = 3 ! Select Cbox DECLARE LONG CONSTANT ECR$M_PMF_EMUX = x'00380000' DECLARE LONG CONSTANT ECR$K_EMUX_S3_STALL = 0 ! Measure S3 stall against total cycles DECLARE LONG CONSTANT ECR$K_EMUX_EM_PA_STALL = 1 ! Measure EM+PA queue stall against total cycles DECLARE LONG CONSTANT ECR$K_EMUX_CPI = 2 ! Measure instructions retired against total cycles DECLARE LONG CONSTANT ECR$K_EMUX_STALL = 3 ! Measure total stalls against total cycles DECLARE LONG CONSTANT ECR$K_EMUX_S3_STALL_PCT = 4 ! Measure S3 stall against total stalls DECLARE LONG CONSTANT ECR$K_EMUX_EM_PA_STALL_PCT = 5 ! Measure EM+PA queue stall against total stalls DECLARE LONG CONSTANT ECR$K_EMUX_UWORD = 7 ! Count microword increments DECLARE LONG CONSTANT ECR$M_PMF_LFSR = x'00400000' DECLARE LONG CONSTANT ECR$M_PMF_CLEAR = x'80000000' DECLARE LONG CONSTANT PR1701$_MTBTAG = 126 ! Mbox TB tag fill ( WO ) DECLARE LONG CONSTANT MTBTAG$M_TP = x'00000001' DECLARE LONG CONSTANT MTBTAG$M_VPN = x'FFFFFE00' DECLARE LONG CONSTANT PR1701$_MTBPTE = 127 ! Mbox TB PTE fill ( WO ) DECLARE LONG CONSTANT MTBPTE$M_PFN = x'007FFFFF' DECLARE LONG CONSTANT MTBPTE$M_P = x'01000000' DECLARE LONG CONSTANT MTBPTE$M_M = x'04000000' DECLARE LONG CONSTANT MTBPTE$M_PROT = x'18000000' DECLARE LONG CONSTANT MTBPTE$M_V = x'20000000' DECLARE LONG CONSTANT PR1701$_VPSR = 144 ! Vector processor status register ( RW ) DECLARE LONG CONSTANT PR17_VPSR$M_VEN = x'00000001' DECLARE LONG CONSTANT PR17_VPSR$M_RST = x'00000002' DECLARE LONG CONSTANT PR17_VPSR$M_AEX = x'00000080' DECLARE LONG CONSTANT PR17_VPSR$M_IMP = x'01000000' DECLARE LONG CONSTANT PR17_VPSR$M_BSY = x'80000000' DECLARE LONG CONSTANT PR1701$_VAER = 145 ! Vector arithmetic exception register ( RO ) DECLARE LONG CONSTANT PR17_VAER$M_F_UNDF = x'00000001' DECLARE LONG CONSTANT PR17_VAER$M_F_DIVZ = x'00000002' DECLARE LONG CONSTANT PR17_VAER$M_F_ROPR = x'00000004' DECLARE LONG CONSTANT PR17_VAER$M_F_OVFL = x'00000008' DECLARE LONG CONSTANT PR17_VAER$M_I_OVFL = x'00000020' DECLARE LONG CONSTANT PR17_VAER$M_REGISTER_MASK = x'FFFF0000' DECLARE LONG CONSTANT PR1701$_VMAC = 146 ! Vector memory activity register ( RO ) DECLARE LONG CONSTANT PR1701$_VTBIA = 147 ! Vector translation buffer invalidate all ( WO ) ! Cbox registers. DECLARE LONG CONSTANT PR1701$_BIU_CTL = 160 ! Cbox control register ( RW ) DECLARE LONG CONSTANT BIU_CTL$M_BC_EN = x'00000001' DECLARE LONG CONSTANT BIU_CTL$M_ECC = x'00000002' DECLARE LONG CONSTANT BIU_CTL$K_ECC_ECC = 1 ! select ECC mode DECLARE LONG CONSTANT BIU_CTL$K_ECC_PARITY = 0 ! select Parity mode DECLARE LONG CONSTANT BIU_CTL$M_OE = x'00000004' DECLARE LONG CONSTANT BIU_CTL$M_BC_FHIT = x'00000008' DECLARE LONG CONSTANT BIU_CTL$M_BC_SPD = x'000000F0' DECLARE LONG CONSTANT BIU_CTL$K_BC_SPD_2X = 0 ! 2x cpu cycle DECLARE LONG CONSTANT BIU_CTL$K_BC_SPD_3X = 1 ! 3x cpu cycle DECLARE LONG CONSTANT BIU_CTL$K_BC_SPD_4X = 2 ! 4x cpu cycle DECLARE LONG CONSTANT BIU_CTL$M_BC_SIZE = x'70000000' DECLARE LONG CONSTANT BIU_CTL$K_BC_SIZE_128KB = 0 ! Select 128KB Bcache DECLARE LONG CONSTANT BIU_CTL$K_BC_SIZE_256KB = 1 ! Select 256KB Bcache DECLARE LONG CONSTANT BIU_CTL$K_BC_SIZE_512KB = 2 ! Select 512KB Bcache DECLARE LONG CONSTANT BIU_CTL$K_BC_SIZE_1MB = 3 ! Select 1MB Bcache DECLARE LONG CONSTANT BIU_CTL$K_BC_SIZE_2MB = 4 ! Select 2MB Bcache DECLARE LONG CONSTANT BIU_CTL$K_BC_SIZE_4MB = 5 ! Select 4MB Bcache DECLARE LONG CONSTANT BIU_CTL$K_BC_SIZE_8MB = 6 ! Select 8MB Bcache DECLARE LONG CONSTANT BIU_CTL$M_WS_IO = x'80000000' DECLARE LONG CONSTANT PR1701$_BC_TAG = 162 ! Bcache error tag ( RO ) DECLARE LONG CONSTANT BC_TAG$M_HIT = x'00000001' DECLARE LONG CONSTANT BC_TAG$M_CTL_P = x'00000002' DECLARE LONG CONSTANT BC_TAG$M_CTL_S = x'00000004' DECLARE LONG CONSTANT BC_TAG$M_CTL_D = x'00000008' DECLARE LONG CONSTANT BC_TAG$M_CTL_V = x'00000010' DECLARE LONG CONSTANT BC_TAG$M_TAG_P = x'00400000' DECLARE LONG CONSTANT PR1701$_BIU_STAT = 164 ! Bcache error data status ( W1C ) DECLARE LONG CONSTANT BIU_STAT$M_BIU_HERR = x'00000001' DECLARE LONG CONSTANT BIU_STAT$M_BIU_SERR = x'00000002' DECLARE LONG CONSTANT BIU_STAT$M_BC_TPERR = x'00000004' DECLARE LONG CONSTANT BIU_STAT$M_BC_TCPERR = x'00000008' DECLARE LONG CONSTANT BIU_STAT$M_BIU_DSP_CMD = x'00000070' DECLARE LONG CONSTANT BIU_STAT$K_WRITE_UNLOCK_IO = 0 ! WRITE_UNLOCK_IO cmd DECLARE LONG CONSTANT BIU_STAT$K_IREAD = 1 ! IREAD cmd DECLARE LONG CONSTANT BIU_STAT$K_WRITE_UNLOCK = 2 ! WRITE_UNLOCK cmd DECLARE LONG CONSTANT BIU_STAT$K_WRITE = 3 ! WRITE cmd DECLARE LONG CONSTANT BIU_STAT$K_DREAD = 4 ! DREAD cmd DECLARE LONG CONSTANT BIU_STAT$K_DREAD_IO = 5 ! DREAD_IO cmd DECLARE LONG CONSTANT BIU_STAT$K_DREAD_LOCK = 6 ! DREAD_LOCK cmd DECLARE LONG CONSTANT BIU_STAT$M_BIU_SEO = x'00000080' DECLARE LONG CONSTANT BIU_STAT$M_FILL_ECC = x'00000100' DECLARE LONG CONSTANT BIU_STAT$M_FILL_CRD = x'00000200' DECLARE LONG CONSTANT BIU_STAT$M_BIU_DPERR = x'00000400' DECLARE LONG CONSTANT BIU_STAT$M_FILL_IRD = x'00000800' DECLARE LONG CONSTANT BIU_STAT$M_FILL_SEO = x'00004000' DECLARE LONG CONSTANT BIU_STAT$M_RAZ = x'00008000' DECLARE LONG CONSTANT BIU_STAT$M_FILL_DSP_CMD = x'000F0000' DECLARE LONG CONSTANT BIU_STAT$K_F_IREAD = 2 ! IREAD cmd DECLARE LONG CONSTANT BIU_STAT$K_IREAD_IO = 3 ! IREAD_IO cmd DECLARE LONG CONSTANT BIU_STAT$K_F_WRITE_UNLOCK_IO = 4 ! WRITE_UNLOCK_IO cmd DECLARE LONG CONSTANT BIU_STAT$K_WRITE_IO = 5 ! WRITE_IO cmd DECLARE LONG CONSTANT BIU_STAT$K_F_WRITE = 6 ! WRITE cmd DECLARE LONG CONSTANT BIU_STAT$K_F_WRITE_UNLOCK = 7 ! WRITE_UNLOCK cmd DECLARE LONG CONSTANT BIU_STAT$K_F_DREAD = 8 ! DREAD cmd 100X DECLARE LONG CONSTANT BIU_STAT$K_F_DREAD2 = 9 ! DREAD cmd 100X DECLARE LONG CONSTANT BIU_STAT$K_F_DREAD_IO = 10 ! DREAD_IO cmd DECLARE LONG CONSTANT BIU_STAT$K_F_DREAD_LOCK = 12 ! DREAD_LOCK cmd DECLARE LONG CONSTANT BIU_STAT$K_DREAD_LOCK_IO = 13 ! DREAD_LOCK_IO cmd DECLARE LONG CONSTANT BIU_STAT$M_LST_WRT = x'00100000' DECLARE LONG CONSTANT BIU_STAT$M_RSVD = x'0FE00000' DECLARE LONG CONSTANT BIU_STAT$M_BIU_ADDR = x'30000000' DECLARE LONG CONSTANT BIU_STAT$M_FILL_ADDR = x'C0000000' DECLARE LONG CONSTANT PR1701$_BIU_ADDR = 166 ! error address associated with BIU errors ( RO ) DECLARE LONG CONSTANT PR1701$_FILL_SYN = 168 ! Syndrome bits associated with bad quadword during fill ( RO ) DECLARE LONG CONSTANT PR1701$_FILL_ADDR = 170 ! error address associated with FILL errors ( RO ) DECLARE LONG CONSTANT PR1701$_STC_RESULT = 172 ! Result of last store conditional ( RO ) DECLARE LONG CONSTANT STC_RESULT$M_PASS = x'00000004' DECLARE LONG CONSTANT PR1701$_BEDECC = 174 ! Alternate source of ECC check bits ( W ) DECLARE LONG CONSTANT PR1701$_CHALT = 176 ! Console HALT register ( RW ) DECLARE LONG CONSTANT PR1701$_SIO = 178 ! Seral line I/O register ( RW ) DECLARE LONG CONSTANT SIO$M_SIO_IN = x'00000001' DECLARE LONG CONSTANT SIO$M_SIO_OUT = x'00000002' DECLARE LONG CONSTANT PR1701$_SIO_IE = 180 ! Seral line I/O register ( RW ) DECLARE LONG CONSTANT SIO$M_SROM_OE = x'00000001' DECLARE LONG CONSTANT SIO$M_SROM_FAST = x'00000002' DECLARE LONG CONSTANT PR1701$_QW_PACK = 184 ! Pack next two longword writes ( WO ) DECLARE LONG CONSTANT PR1701$_CLR_IO_PACK = 185 ! Clear QW IO Pack ( W ) ! Ibox registers. DECLARE LONG CONSTANT PR1701$_VMAR = 208 ! VIC memory address register DECLARE LONG CONSTANT VMAR$M_LW = x'00000004' DECLARE LONG CONSTANT VMAR$M_SUB_BLOCK = x'00000018' DECLARE LONG CONSTANT VMAR$M_ROW_INDEX = x'000007E0' DECLARE LONG CONSTANT VMAR$M_ADDR = x'FFFFF800' DECLARE LONG CONSTANT PR1701$_VTAG = 209 ! VIC tag register DECLARE LONG CONSTANT VTAG$M_V = x'0000000F' DECLARE LONG CONSTANT VTAG$M_DP = x'000000F0' DECLARE LONG CONSTANT VTAG$M_TP = x'00000100' DECLARE LONG CONSTANT VTAG$M_TAG = x'FFFFF800' DECLARE LONG CONSTANT PR1701$_VDATA = 210 ! VIC data register DECLARE LONG CONSTANT PR1701$_ICSR = 211 ! Ibox control and status register ( RW ) DECLARE LONG CONSTANT ICSR$M_ENABLE = x'00000001' DECLARE LONG CONSTANT ICSR$M_LOCK = x'00000004' DECLARE LONG CONSTANT ICSR$M_DPERR = x'00000008' DECLARE LONG CONSTANT ICSR$M_TPERR = x'00000010' DECLARE LONG CONSTANT PR1701$_BPCR = 212 ! Ibox branch prediction control register DECLARE LONG CONSTANT BPCR$M_HISTORY = x'0000000F' DECLARE LONG CONSTANT BPCR$M_MISPREDICT = x'00000020' DECLARE LONG CONSTANT BPCR$M_FLUSH_BHT = x'00000040' DECLARE LONG CONSTANT BPCR$M_FLUSH_CTR = x'00000080' DECLARE LONG CONSTANT BPCR$M_LOAD_HISTORY = x'00000100' DECLARE LONG CONSTANT BPCR$M_BPU_ALGORITHM = x'FFFF0000' DECLARE LONG CONSTANT BPCR$K_BPU_ALGORITHM = 65226 ! default value for BPU_ALGORITHM field DECLARE LONG CONSTANT PR1701$_BPC = 214 ! Ibox Backup PC ( RO ) DECLARE LONG CONSTANT PR1701$_BPCUNW = 215 ! Ibox Backup PC with RLOG unwind ( RO ) ! Mbox internal memory management registers. DECLARE LONG CONSTANT PR1701$_MP0BR = 224 ! Mbox P0 base register ( RW ) DECLARE LONG CONSTANT PR1701$_MP0LR = 225 ! Mbox P0 length register ( RW ) DECLARE LONG CONSTANT PR1701$_MP1BR = 226 ! Mbox P1 base register ( RW ) DECLARE LONG CONSTANT PR1701$_MP1LR = 227 ! Mbox P1 length register ( RW ) DECLARE LONG CONSTANT PR1701$_MSBR = 228 ! Mbox system base register ( RW ) DECLARE LONG CONSTANT PR1701$_MSLR = 229 ! Mbox system length register ( RW ) DECLARE LONG CONSTANT PR1701$_MMAPEN = 230 ! Mbox memory management enable ( RW ) ! Mbox registers. DECLARE LONG CONSTANT PR1701$_PAMODE = 231 ! Mbox physical address mode ( RW ) DECLARE LONG CONSTANT PR1701_PAMODE$M_MODE = x'00000001' DECLARE LONG CONSTANT PR1701_PAMODE$K_PA_30 = 0 ! 30-bit PA mode DECLARE LONG CONSTANT PR1701_PAMODE$K_PA_32 = 1 ! 32-bit PA mode DECLARE LONG CONSTANT PR1701$_MMEADR = 232 ! Mbox memory management fault address ( RO ) DECLARE LONG CONSTANT PR1701$_MMEPTE = 233 ! Mbox memory management fault PTE address ( RO ) DECLARE LONG CONSTANT PR1701$_MMESTS = 234 ! Mbox memory management fault status ( RO ) DECLARE LONG CONSTANT MMESTS$M_LV = x'00000001' DECLARE LONG CONSTANT MMESTS$M_PTE_REF = x'00000002' DECLARE LONG CONSTANT MMESTS$M_M = x'00000004' DECLARE LONG CONSTANT MMESTS$M_FAULT = x'0000C000' DECLARE LONG CONSTANT MMESTS$K_FAULT_ACV = 1 ! ACV fault DECLARE LONG CONSTANT MMESTS$K_FAULT_TNV = 2 ! TNV fault DECLARE LONG CONSTANT MMESTS$K_FAULT_M0 = 3 ! M=0 fault DECLARE LONG CONSTANT MMESTS$M_SRC = x'1C000000' DECLARE LONG CONSTANT MMESTS$M_LOCK = x'E0000000' DECLARE LONG CONSTANT PR1701$_TBADR = 236 ! Mbox TB parity error address ( RO ) DECLARE LONG CONSTANT PR1701$_TBSTS = 237 ! Mbox TB parity error status ( RW ) DECLARE LONG CONSTANT TBSTS$M_LOCK = x'00000001' DECLARE LONG CONSTANT TBSTS$M_DPERR = x'00000002' DECLARE LONG CONSTANT TBSTS$M_TPERR = x'00000004' DECLARE LONG CONSTANT TBSTS$M_EM_VAL = x'00000008' DECLARE LONG CONSTANT TBSTS$M_CMD = x'000001F0' DECLARE LONG CONSTANT TBSTS$M_SRC = x'E0000000' DECLARE LONG CONSTANT MSRC$K_IREF_LATCH = 6 ! Source of fault was IREF latch DECLARE LONG CONSTANT MSRC$K_SPEC_QUEUE = 4 ! Source of fault was spec queue DECLARE LONG CONSTANT MSRC$K_EM_LATCH = 0 ! Source of fault was EM latch ! Mbox Pcache registers DECLARE LONG CONSTANT PR1701$_PCADR = 242 ! Mbox Pcache parity error address ( RO ) DECLARE LONG CONSTANT PR1701$_PCSTS = 244 ! Mbox Pcache parity error status ( RW ) DECLARE LONG CONSTANT PCSTS$M_LOCK = x'00000001' DECLARE LONG CONSTANT PCSTS$M_DPERR = x'00000002' DECLARE LONG CONSTANT PCSTS$M_RIGHT_BANK = x'00000004' DECLARE LONG CONSTANT PCSTS$M_LEFT_BANK = x'00000008' DECLARE LONG CONSTANT PCSTS$M_CMD = x'000001F0' DECLARE LONG CONSTANT PCSTS$M_PTE_ER_WR = x'00000200' DECLARE LONG CONSTANT PCSTS$M_PTE_ER = x'00000400' DECLARE LONG CONSTANT PR1701$_PCCTL = 248 ! Mbox Pcache control ( RW ) DECLARE LONG CONSTANT PCCTL$M_D_ENABLE = x'00000001' DECLARE LONG CONSTANT PCCTL$M_I_ENABLE = x'00000002' DECLARE LONG CONSTANT PCCTL$M_FORCE_HIT = x'00000004' DECLARE LONG CONSTANT PCCTL$M_BANK_SEL = x'00000008' DECLARE LONG CONSTANT PCCTL$M_P_ENABLE = x'00000010' DECLARE LONG CONSTANT PCCTL$M_PMM = x'000000E0' DECLARE LONG CONSTANT PCCTL$M_ELEC_DISABLE = x'00000100' DECLARE LONG CONSTANT PCCTL$M_RED_ENABLE = x'00000200' DECLARE LONG CONSTANT PR1701$_PCTAG = 25165824 ! First of 256 Pcache tag IPRs ( RW ) DECLARE LONG CONSTANT PR1701$_PCTAG_MAX = 25173984 ! Last of 256 Pcache tag IPRs DECLARE LONG CONSTANT PCTAG$K_IPR_INCR = 32 ! Increment between Pcache tag IPR numbers DECLARE LONG CONSTANT PR17_PCTAG$M_A = x'00000001' DECLARE LONG CONSTANT PR17_PCTAG$M_V = x'0000001E' DECLARE LONG CONSTANT PR17_PCTAG$M_P = x'00000020' DECLARE LONG CONSTANT PR17_PCTAG$M_TAG = x'01FFF000' DECLARE LONG CONSTANT PCTAGA$M_INDEX = x'00000FE0' DECLARE LONG CONSTANT PCTAGA$M_B = x'00001000' DECLARE LONG CONSTANT PR1701$_PCDAP = 29360128 ! First of 1024 Pcache data parity IPRs ( RW ) DECLARE LONG CONSTANT PR1701$_PCDAP_MAX = 29368312 ! Last of 1024 Pcache data parity IPRs DECLARE LONG CONSTANT PCDAP$K_IPR_INCR = 8 ! Increment between Pcache data parity IPR numbers DECLARE LONG CONSTANT PCDAP$M_DATA_PARITY = x'000000FF' DECLARE LONG CONSTANT PR1701S_PR1701DEF = 32 record PR1701DEF variant ! Architecturally-defined registers which have different characteristics ! on this CPU. case group PR1701R_PR1701SAVPSL_BITS ! Saved PSL bits <7:0> ! Halt code containing one of the following values ! Invalid SAVPSL if = 1 ! MAPEN<0> ! Saved PSL bits <31:16> LONG PSL_LO_bits ! COMMENT ADDED BY SDL - PSL_LO_bits contains bits PSL_LO through PSL_HI end group PR1701R_PR1701SAVPSL_BITS ! These registers are for testability and diagnostics use only. ! They should not be referenced in normal operation. case group PR1701R_PR1701IAK_VECTOR ! Vector returned in response to IAK1x read ! Force IPL 17, independent of actual level ! Passive release ! LW offset in SCB of interrupt vector LONG IPL17_bits ! COMMENT ADDED BY SDL - IPL17_bits contains bits IPL17 through FILL_1 end group PR1701R_PR1701IAK_VECTOR ! Ebox register definition case group PR1701R_PR1701INTSYS_BITS ! ICCS<6> (RO) ! SISR<15:1> (RO) ! ID of highest pending interrupt (RO) ! Interval timer interrupt reset (WC) ! Soft error interrupt reset (WC) ! Performance monitoring interrupt reset (WC) ! Hard error interrupt reset (WC) ! Power fail interrupt reset (WC) ! Halt pin interrupt reset (WC) LONG ICCS6_bits ! COMMENT ADDED BY SDL - ICCS6_bits contains bits ICCS6 through HALT_RESET end group PR1701R_PR1701INTSYS_BITS case group PR1701R_PR1701PMFCNT_BITS ! PMCTR0 word ! PMCTR1 word LONG PMCTR0_bits ! COMMENT ADDED BY SDL - PMCTR0_bits contains bits PMCTR0 through PMCTR1 end group PR1701R_PR1701PMFCNT_BITS case group PR1701R_PR1701PCSCR_BITS ! Disable parallel port control of scan chain ! Enable use of patchable control store ! Write scan chain to patchable control store ! Shift read-write latch scan chain by one bit ! Data to be shifted into the PCS scan chain ! Non-standard patch bit ! Patch revision number LONG FILL_1_bits ! COMMENT ADDED BY SDL - FILL_1_bits contains bits FILL_1 through FILL_3 end group PR1701R_PR1701PCSCR_BITS case group PR1701R_PR1701ECR_BITS ! Vector unit present (RW) ! Fbox enabled (RW) ! Select external timebase for S3 stall timeout timer (RW) ! Fbox stage 4 conditional bypass enable (RW) ! S3 stall timeout occurred (WC) ! Select test mode for S3 stall timeout (RW) ! Clock S3 timeout (RW) ! eliminate -ICCS in external logic- bit ! Enable test of Fbox (RW) ! Performance monitoring facility enable (RW) ! Performance monitoring facility master select (RW) ! Performance monitoring facility Ebox mux select (RW) ! Performance monitoring facility Wbus LFSR enable (RW) ! Clear performance monitoring hardware counters (WO) LONG VECTOR_PRESENT_bits ! COMMENT ADDED BY SDL - VECTOR_PRESENT_bits contains bits VECTOR_PRESENT through & ! PMF_CLEAR end group PR1701R_PR1701ECR_BITS ! Mbox TB registers. ! These registers are for testability and diagnostics use only. ! They should not be referenced in normal operation. case group PR1701R_PR1701MTBTAG_BITS ! Tag parity bit ! Virtual page number of address (VA<31:9>) LONG TP_bits ! COMMENT ADDED BY SDL - TP_bits contains bits TP through VPN end group PR1701R_PR1701MTBTAG_BITS case group PR1701R_PR1701MTBPTE_BITS ! Format is normal PTE format, except for PTE parity bit ! Page frame number (PA<31:9>) ! PTE parity ! Modify bit ! Protection field ! PTE valid bit LONG PFN_bits ! COMMENT ADDED BY SDL - PFN_bits contains bits PFN through fill_104 end group PR1701R_PR1701MTBPTE_BITS ! Vector architecture registers case group PR1701R_PR1701VPSR_BITS ! Vector processor enabled (RW) ! Vector processor state reset (WO) ! Vector arithmetic exception (WC) ! Implementation-specific hardware error (WC) ! Vector processor busy (RO) LONG VEN_bits ! COMMENT ADDED BY SDL - VEN_bits contains bits VEN through BSY end group PR1701R_PR1701VPSR_BITS case group PR1701R_PR1701VAER_BITS ! Floating underflow ! Floating divide-by-zero ! Floating reserved operand ! Floating overflow ! Integer overflow ! Vector destination register mask LONG F_UNDF_bits ! COMMENT ADDED BY SDL - F_UNDF_bits contains bits F_UNDF through REGISTER_MASK end group PR1701R_PR1701VAER_BITS case group PR1701R_PR1701BIU_CTL_BITS ! Enable Bcache (WO) ! ECC/Parity select (WO) ! CE pins not asserted during RAM write cycles (WO) ! Force Bcache hit (WO) ! Bcache speed (WO) ! Bcache size (WO) ! Workstation IO mapping LONG BC_EN_bits ! COMMENT ADDED BY SDL - BC_EN_bits contains bits BC_EN through WS_IO end group PR1701R_PR1701BIU_CTL_BITS ! Cbox registers, continued case group PR1701R_PR1701BC_TAG_BITS ! tag status parity bit ! tag shared bit ! tag dirty bit ! tag valid bit ! tag ! tag parity LONG HIT_bits ! COMMENT ADDED BY SDL - HIT_bits contains bits HIT through fill_105 end group PR1701R_PR1701BC_TAG_BITS ! Cbox registers, continued case group PR1701R_PR1701BIU_STAT_BITS ! Hard_Error on cACK ! Soft_Error on cACK ! Tag Parity error in tag address RAM ! Tag Parity error in tag control RAM ! Cbox cycle type ! second BIU or BC error ! ECC error on Pcache fill data ! ECC error was correctable ! BIU parity error ! error during I stream fill ! Quadword within Pcache FILL hexaword which had a FILL error ! second FILL error ! Read as ZERO ! Cbox cmd which resulted in FILL error ! Lost write error ! reserved bits ! BIU ADDR bits 33:32 ! FILL ADDR bits 33:32 LONG BIU_HERR_bits ! COMMENT ADDED BY SDL - BIU_HERR_bits contains bits BIU_HERR through FILL_ADDR end group PR1701R_PR1701BIU_STAT_BITS case group PR1701R_PR1701FILL_SYN_BITS ! ECC syndrome bits for low longword ! ECC syndrome bits for high longword LONG LO_bits ! COMMENT ADDED BY SDL - LO_bits contains bits LO through FILL_1 end group PR1701R_PR1701FILL_SYN_BITS ! Cbox registers, continued case group PR1701R_PR1701STC_RESULT_BITS ! Store Conditional passed LONG FILL_1_bits ! COMMENT ADDED BY SDL - FILL_1_bits contains bits FILL_1 through FILL_2 end group PR1701R_PR1701STC_RESULT_BITS case group PR1701R_PR1701BEDECC_BITS ! BEDECC bits for low longword ! BEDECC bits for high longword LONG LO_bits ! COMMENT ADDED BY SDL - LO_bits contains bits LO through FILL_1 end group PR1701R_PR1701BEDECC_BITS ! Console dispatch structure case group PR1701R_CONSOLE_DISPATCH ! Console dispatch structure LONG CHALT$L_BRW_CODE ! BRW code LONG CHALT$L_SYS_TYPE ! System Type LONG CHALT$L_CNSL_LOAD_ADR ! Consoles Load address used by SROM LONG CHALT$L_HWRPB_SIZE ! HWRPB size in pages LONG CHALT$L_HWRPB_PHYS_ADR ! HWRPB base physical addrress LONG CHALT$L_MEM_BITMAP_SIZ ! Memory bitmap size ( bits ) LONG CHALT$L_MEM_BITMAP_PHYS_ADR ! Memory bitmap physical address LONG CHALT$L_MEM_BITMAP_CHKSM ! Memory bitmap checksum end group PR1701R_CONSOLE_DISPATCH ! Serial line I/O registers case group PR1701R_PR1701SIO_BITS ! Serial line/SROM input ! Serial line/SROM clock output LONG SIO_IN_bits ! COMMENT ADDED BY SDL - SIO_IN_bits contains bits SIO_IN through FILL_1 end group PR1701R_PR1701SIO_BITS case group PR1701R_PR1701SIO_IE_BITS ! SROM output enable ! Use fast version of SROM LONG SROM_OE_bits ! COMMENT ADDED BY SDL - SROM_OE_bits contains bits SROM_OE through FILL_2 end group PR1701R_PR1701SIO_IE_BITS case group PR1701R_PR1701VMAR_BITS ! longword within quadword ! sub-block indicator ! cache row index ! error address LONG FILL_1_bits ! COMMENT ADDED BY SDL - FILL_1_bits contains bits FILL_1 through ADDR end group PR1701R_PR1701VMAR_BITS case group PR1701R_PR1701VTAG_BITS ! data valid bits ! data parity bits ! tag parity bit ! unused bits (zero) ! tag LONG V_bits ! COMMENT ADDED BY SDL - V_bits contains bits V through TAG end group PR1701R_PR1701VTAG_BITS case group PR1701R_PR1701ICSR_BITS ! VIC enable bit (RW) ! Register is locked due to an error (WC) ! Data parity error (RO) ! Tag parity error (RO) LONG ENABLE_bits ! COMMENT ADDED BY SDL - ENABLE_bits contains bits ENABLE through FILL_2 end group PR1701R_PR1701ICSR_BITS case group PR1701R_PR1701BPCR_BITS ! branch history bits ! history of last branch ! flush branch history table ! flush branch hist addr counter ! write new history to array ! unused bits (must be zero) ! branch prediction algorithm LONG HISTORY_bits ! COMMENT ADDED BY SDL - HISTORY_bits contains bits HISTORY through BPU_ALGORITHM end group PR1701R_PR1701BPCR_BITS ! The following two registers are for testability and diagnostics use only. ! They should not be referenced in normal operation. ! These registers are for testability and diagnostics use only. ! In normal operation, the equivalent architecturally-defined registers ! should be used instead. case group PR1701R_PR1701PAMODE_BITS ! Addressing mode(1 = 32bit addressing) (RW) LONG MODE_bits ! COMMENT ADDED BY SDL - MODE_bits contains bits MODE through FILL_1 end group PR1701R_PR1701PAMODE_BITS case group PR1701R_PR1701MMESTS_BITS ! ACV fault due to length violation ! ACV/TNV fault occurred on PPTE reference ! Reference had write or modify intent ! Fault type, one of the following: ! Shadow copy of LOCK bits (see MSRC$ constants below) ! Lock status (see MSRC$ constant below) LONG LV_bits ! COMMENT ADDED BY SDL - LV_bits contains bits LV through LOCK end group PR1701R_PR1701MMESTS_BITS case group PR1701R_PR1701TBSTS_BITS ! Register is locked due to an error (WC) ! Data parity error (RO) ! Tag parity error (RO) ! EM latch was valid when error occurred (RO) ! S5 command when TB parity error occured (RO) ! Source of original refernce (see MSRC$ constants below) (RO) LONG LOCK_bits ! COMMENT ADDED BY SDL - LOCK_bits contains bits LOCK through SRC end group PR1701R_PR1701TBSTS_BITS case group PR1701R_PR1701PCSTS_BITS ! Register is locked due to an error (WC) ! Data parity error occurred (RO) ! Right bank tag parity error occurred (RO) ! Left bank tag parity error occurred (RO) ! S6 command when Pcache parity error occured (RO) ! Hard error on PTE DREAD occurred (orig ref was WRITE) (WC) ! Hard error on PTE DREAD occurred (WC) LONG LOCK_bits ! COMMENT ADDED BY SDL - LOCK_bits contains bits LOCK through FILL_1 end group PR1701R_PR1701PCSTS_BITS case group PR1701R_PR1701PCCTL_BITS ! Enable for invalidate, D-stream read/write/fill (RW) ! Enable for invalidate, I-stream read/fill (RW) ! Enable force hit on Pcache references (RW) ! Select left bank if 0, right bank if 1 (RW) ! Enable parity checking (RW) ! Mbox performance monitor mode (RW) ! Pcache electrical disable bit (RW) ! Redundancy enable bit (RO) LONG D_ENABLE_bits ! COMMENT ADDED BY SDL - D_ENABLE_bits contains bits D_ENABLE through FILL_1 end group PR1701R_PR1701PCCTL_BITS case group PR1701R_PR1701PCTAG_BITS ! Allocation bit corresponding to index of this tag (RW) ! Valid bits corresponding to the 4 data subblocks (RW) ! Tag parity (RW) ! Tag bits (RW) LONG A_bits ! COMMENT ADDED BY SDL - A_bits contains bits A through fill_106 end group PR1701R_PR1701PCTAG_BITS case group PR1701R_PR1701PCTAGA_BITS ! Address of Pcache tag IPRs - Base = PCTAG ! Index of PCache tag ! Bank of PCache to access: 0=left, 1=right WORD FILL_1_bits ! COMMENT ADDED BY SDL - FILL_1_bits contains bits FILL_1 through fill_107 end group PR1701R_PR1701PCTAGA_BITS case group PR1701R_PR1701PCDAP_BITS ! Even byte parity for the addressed quadword (RW) LONG DATA_PARITY_bits ! COMMENT ADDED BY SDL - DATA_PARITY_bits contains bits DATA_PARITY through FILL_1 end group PR1701R_PR1701PCDAP_BITS end variant end record PR1701DEF