%IF %DECLARED ( %BASIC$QUADWORD_DECLARED ) = 0 %THEN RECORD BASIC$QUADWORD LONG FILL ( 2 ) END RECORD %LET %BASIC$QUADWORD_DECLARED = 1 %END %IF %IF %DECLARED ( %BASIC$OCTAWORD_DECLARED ) = 0 %THEN RECORD BASIC$OCTAWORD LONG FILL ( 4 ) END RECORD %LET %BASIC$OCTAWORD_DECLARED = 1 %END %IF %IF %DECLARED ( %BASIC$F_FLOATING_COMPLEX_DECL ) = 0 %THEN RECORD BASIC$F_FLOATING_COMPLEX SINGLE REAL_PART SINGLE IMAGINARY_PART END RECORD %LET %BASIC$F_FLOATING_COMPLEX_DECL = 1 %END %IF %IF %DECLARED ( %BASIC$D_FLOATING_COMPLEX_DECL ) = 0 %THEN RECORD BASIC$D_FLOATING_COMPLEX DOUBLE REAL_PART DOUBLE IMAGINARY_PART END RECORD %LET %BASIC$D_FLOATING_COMPLEX_DECL = 1 %END %IF %IF %DECLARED ( %BASIC$G_FLOATING_COMPLEX_DECL ) = 0 %THEN RECORD BASIC$G_FLOATING_COMPLEX GFLOAT REAL_PART GFLOAT IMAGINARY_PART END RECORD %LET %BASIC$G_FLOATING_COMPLEX_DECL = 1 %END %IF %IF %DECLARED ( %BASIC$H_FLOATING_COMPLEX_DECL ) = 0 %THEN RECORD BASIC$H_FLOATING_COMPLEX HFLOAT REAL_PART HFLOAT IMAGINARY_PART END RECORD %LET %BASIC$H_FLOATING_COMPLEX_DECL = 1 %END %IF DECLARE LONG CONSTANT PR13$K_REVISION = 30 ! Revision number of this file ! In the definitions below, registers are annotated with one of the following ! symbols: ! ! RW - The register may be read and written ! RO - The register may only be read ! WO - The register may only be written ! ! For RO and WO registers, all bits and fields within the register are also ! read-only or write-only. For RW registers, each bit or field within ! the register is annotated with one of the following: ! ! RW - The bit/field may be read and written ! RO - The bit/field may be read; writes are ignored ! WO - The bit/field may be written; reads return an UNPREDICTABLE result. ! WZ - The bit/field may be written; reads return a 0 ! WC - The bit/field may be read; writes cause state to clear ! RC - The bit/field may be read, which also causes state to clear; writes are ignored DECLARE LONG CONSTANT PR13$_TODR = 27 ! Time Of Year Register ( RW ) DECLARE LONG CONSTANT PR13$_MCESR = 38 ! Machine check error register ( WO ) DECLARE LONG CONSTANT PR13$_SAVPC = 42 ! Console saved PC ( RO ) DECLARE LONG CONSTANT PR13$_SAVPSL = 43 ! Console saved PSL ( RO ) DECLARE LONG CONSTANT PR13_SAVPSL$M_PSL_LO = x'000000FF' DECLARE LONG CONSTANT PR13_SAVPSL$M_HALTCODE = x'00003F00' DECLARE LONG CONSTANT PR13_SAVPSL$K_HALT_HLTPIN = 2 ! HALT_L pin asserted DECLARE LONG CONSTANT PR13_SAVPSL$K_HALT_PWRUP = 3 ! Initial powerup DECLARE LONG CONSTANT PR13_SAVPSL$K_HALT_INTSTK = 4 ! Interrupt stack not valid DECLARE LONG CONSTANT PR13_SAVPSL$K_HALT_DOUBLE = 5 ! Machine check during exception processing DECLARE LONG CONSTANT PR13_SAVPSL$K_HALT_HLTINS = 6 ! Halt instruction in kernel mode DECLARE LONG CONSTANT PR13_SAVPSL$K_HALT_ILLVEC = 7 ! Illegal SCB vector ( bits<1:0>=11 ) DECLARE LONG CONSTANT PR13_SAVPSL$K_HALT_WCSVEC = 8 ! WCS SCB vector ( bits<1:0>=10 ) DECLARE LONG CONSTANT PR13_SAVPSL$K_HALT_CHMFI = 10 ! CHMx on interrupt stack DECLARE LONG CONSTANT PR13_SAVPSL$K_HALT_IE0 = 16 ! ACV/TNV during machine check processing DECLARE LONG CONSTANT PR13_SAVPSL$K_HALT_IE1 = 17 ! ACV/TNV during KSNV processing DECLARE LONG CONSTANT PR13_SAVPSL$K_HALT_IE2 = 18 ! Machine check during machine check processing DECLARE LONG CONSTANT PR13_SAVPSL$K_HALT_IE3 = 19 ! Machine check during KSNV processing DECLARE LONG CONSTANT PR13_SAVPSL$K_HALT_IE_PSL_101 = 25 ! PSL<26:24>=101 during interrupt or exception DECLARE LONG CONSTANT PR13_SAVPSL$K_HALT_IE_PSL_110 = 26 ! PSL<26:24>=110 during interrupt or exception DECLARE LONG CONSTANT PR13_SAVPSL$K_HALT_IE_PSL_111 = 27 ! PSL<26:24>=111 during interrupt or exception DECLARE LONG CONSTANT PR13_SAVPSL$K_HALT_REI_PSL_101 = 29 ! PSL<26:24>=101 during REI DECLARE LONG CONSTANT PR13_SAVPSL$K_HALT_REI_PSL_110 = 30 ! PSL<26:24>=110 during REI DECLARE LONG CONSTANT PR13_SAVPSL$K_HALT_REI_PSL_111 = 31 ! PSL<26:24>=111 during REI DECLARE LONG CONSTANT PR13_SAVPSL$M_INVALID = x'00004000' DECLARE LONG CONSTANT PR13_SAVPSL$M_MAPEN = x'00008000' DECLARE LONG CONSTANT PR13_SAVPSL$M_PSL_HI = x'FFFF0000' DECLARE LONG CONSTANT PR13$_IORESET = 55 ! I/O system reset register ( WO ) DECLARE LONG CONSTANT PR13$_PME = 61 ! Performance monitoring enable ( RW ) DECLARE LONG CONSTANT PR13$_SID = 62 ! System identification register ( RO ) DECLARE LONG CONSTANT PR13_SID$M_UCODE_REV = x'000000FF' DECLARE LONG CONSTANT PR13_SID$M_NONSTANDARD_PATCH = x'00000100' DECLARE LONG CONSTANT PR13_SID$M_PATCH_REV = x'00003E00' DECLARE LONG CONSTANT PR13_SID$M_TYPE = x'FF000000' DECLARE LONG CONSTANT PR13$_IAK14 = 64 ! Level 14 interrupt acknowledge ( RO ) DECLARE LONG CONSTANT PR13$_IAK15 = 65 ! Level 15 interrupt acknowledge ( RO ) DECLARE LONG CONSTANT PR13$_IAK16 = 66 ! Level 16 interrupt acknowledge ( RO ) DECLARE LONG CONSTANT PR13$_IAK17 = 67 ! Level 17 interrupt acknowledge ( RO ) DECLARE LONG CONSTANT PR13_IAK$M_IPL17 = x'00000001' DECLARE LONG CONSTANT PR13_IAK$M_PR = x'00000002' DECLARE LONG CONSTANT PR13_IAK$M_SCB_OFFSET = x'0000FFFC' DECLARE LONG CONSTANT PR13$_CWB = 68 ! Clear write buffers ( RW ) ! Ebox registers. DECLARE LONG CONSTANT PR13$_INTSYS = 122 ! Interrupt system status register ( RW ) DECLARE LONG CONSTANT PR13_INTSYS$M_ICCS6 = x'00000001' DECLARE LONG CONSTANT PR13_INTSYS$M_SISR = x'0000FFFE' DECLARE LONG CONSTANT PR13_INTSYS$M_INT_ID = x'001F0000' DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_HALT = 31 ! Halt pin DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_PWRFL = 30 ! Power fail DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_H_ERR = 29 ! Hard error DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_INT_TIM = 28 ! Interval timer DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_PMON = 27 ! Performance monitor DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_S_ERR = 26 ! Soft error DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_IRQ3 = 23 ! IPL 17 device interrupt DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_IRQ2 = 22 ! IPL 16 device interrupt DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_IRQ1 = 21 ! IPL 15 device interrupt DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_IRQ0 = 20 ! IPL 14 device interrupt DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_SISR15 = 15 ! SISR<15> DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_SISR14 = 14 ! SISR<14> DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_SISR13 = 13 ! SISR<13> DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_SISR12 = 12 ! SISR<12> DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_SISR11 = 11 ! SISR<11> DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_SISR10 = 10 ! SISR<10> DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_SISR9 = 9 ! SISR<9> DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_SISR8 = 8 ! SISR<8> DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_SISR7 = 7 ! SISR<7> DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_SISR6 = 6 ! SISR<6> DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_SISR5 = 5 ! SISR<5> DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_SISR4 = 4 ! SISR<4> DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_SISR3 = 3 ! SISR<3> DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_SISR2 = 2 ! SISR<2> DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_SISR1 = 1 ! SISR<1> DECLARE LONG CONSTANT PR13_INTSYS$K_INT_ID_NO_INT = 0 ! No interrupt DECLARE LONG CONSTANT PR13_INTSYS$M_INT_TIM_RESET = x'01000000' DECLARE LONG CONSTANT PR13_INTSYS$M_S_ERR_RESET = x'08000000' DECLARE LONG CONSTANT PR13_INTSYS$M_PMON_RESET = x'10000000' DECLARE LONG CONSTANT PR13_INTSYS$M_H_ERR_RESET = x'20000000' DECLARE LONG CONSTANT PR13_INTSYS$M_PWRFL_RESET = x'40000000' DECLARE LONG CONSTANT PR13_INTSYS$M_HALT_RESET = x'80000000' DECLARE LONG CONSTANT PR13$_PMFCNT = 123 ! Performance monitoring facility count register ( RW ) DECLARE LONG CONSTANT PR13_PMFCNT$M_PMCTR0 = x'0000FFFF' DECLARE LONG CONSTANT PR13_PMFCNT$M_PMCTR1 = x'FFFF0000' DECLARE LONG CONSTANT PR13$_PCSCR = 124 ! Patchable control store control register ( RW ) DECLARE LONG CONSTANT PR13_PCSCR$M_PAR_PORT_DIS = x'00000100' DECLARE LONG CONSTANT PR13_PCSCR$M_PCS_ENB = x'00000200' DECLARE LONG CONSTANT PR13_PCSCR$M_PCS_WRITE = x'00000400' DECLARE LONG CONSTANT PR13_PCSCR$M_RWL_SHIFT = x'00000800' DECLARE LONG CONSTANT PR13_PCSCR$M_DATA = x'00001000' DECLARE LONG CONSTANT PR13_PCSCR$M_NONSTANDARD_PATCH = x'00800000' DECLARE LONG CONSTANT PR13_PCSCR$M_PATCH_REV = x'1F000000' DECLARE LONG CONSTANT PR13$_ECR = 125 ! Ebox control register ( RW ) DECLARE LONG CONSTANT PR13_ECR$M_VECTOR_PRESENT = x'00000001' DECLARE LONG CONSTANT PR13_ECR$M_FBOX_ENABLE = x'00000002' DECLARE LONG CONSTANT PR13_ECR$M_TIMEOUT_EXT = x'00000004' DECLARE LONG CONSTANT PR13_ECR$M_FBOX_ST4_BYPASS_ENA = x'00000008' DECLARE LONG CONSTANT PR13_ECR$M_TIMEOUT_OCCURRED = x'00000010' DECLARE LONG CONSTANT PR13_ECR$M_TIMEOUT_TEST = x'00000020' DECLARE LONG CONSTANT PR13_ECR$M_TIMEOUT_CLOCK = x'00000040' DECLARE LONG CONSTANT PR13_ECR$M_ICCS_EXT = x'00000080' DECLARE LONG CONSTANT PR13_ECR$M_FBOX_TEST_ENABLE = x'00002000' DECLARE LONG CONSTANT PR13_ECR$M_PMF_ENABLE = x'00010000' DECLARE LONG CONSTANT PR13_ECR$M_PMF_PMUX = x'00060000' DECLARE LONG CONSTANT PR13_ECR$K_PMUX_IBOX = 0 ! Select Ibox DECLARE LONG CONSTANT PR13_ECR$K_PMUX_EBOX = 1 ! Select Ebox DECLARE LONG CONSTANT PR13_ECR$K_PMUX_MBOX = 2 ! Select Mbox DECLARE LONG CONSTANT PR13_ECR$K_PMUX_CBOX = 3 ! Select Cbox DECLARE LONG CONSTANT PR13_ECR$M_PMF_EMUX = x'00380000' DECLARE LONG CONSTANT PR13_ECR$K_EMUX_S3_STALL = 0 ! Measure S3 stall against total cycles DECLARE LONG CONSTANT PR13_ECR$K_EMUX_EM_PA_STALL = 1 ! Measure EM+PA queue stall against total cycles DECLARE LONG CONSTANT PR13_ECR$K_EMUX_CPI = 2 ! Measure instructions retired against total cycles DECLARE LONG CONSTANT PR13_ECR$K_EMUX_STALL = 3 ! Measure total stalls against total cycles DECLARE LONG CONSTANT PR13_ECR$K_EMUX_S3_STALL_PCT = 4 ! Measure S3 stall against total stalls DECLARE LONG CONSTANT PR13_ECR$K_EMUX_EM_PA_STALL_PCT = 5 ! Measure EM+PA queue stall against total stalls DECLARE LONG CONSTANT PR13_ECR$K_EMUX_UWORD = 7 ! Count microword increments DECLARE LONG CONSTANT PR13_ECR$M_PMF_LFSR = x'00400000' DECLARE LONG CONSTANT PR13_ECR$M_PMF_CLEAR = x'80000000' DECLARE LONG CONSTANT PR13$_MTBTAG = 126 ! Mbox TB tag fill ( WO ) DECLARE LONG CONSTANT PR13_MTBTAG$M_TP = x'00000001' DECLARE LONG CONSTANT PR13_MTBTAG$M_VPN = x'FFFFFE00' DECLARE LONG CONSTANT PR13$_MTBPTE = 127 ! Mbox TB PTE fill ( WO ) DECLARE LONG CONSTANT PR13_MTBPTE$M_PFN = x'007FFFFF' DECLARE LONG CONSTANT PR13_MTBPTE$M_P = x'01000000' DECLARE LONG CONSTANT PR13_MTBPTE$M_M = x'04000000' DECLARE LONG CONSTANT PR13_MTBPTE$M_PROT = x'18000000' DECLARE LONG CONSTANT PR13_MTBPTE$M_V = x'20000000' DECLARE LONG CONSTANT PR13$_VPSR = 144 ! Vector processor status register ( RW ) DECLARE LONG CONSTANT PR13_VPSR$M_VEN = x'00000001' DECLARE LONG CONSTANT PR13_VPSR$M_RST = x'00000002' DECLARE LONG CONSTANT PR13_VPSR$M_AEX = x'00000080' DECLARE LONG CONSTANT PR13_VPSR$M_IMP = x'01000000' DECLARE LONG CONSTANT PR13_VPSR$M_BSY = x'80000000' DECLARE LONG CONSTANT PR13$_VAER = 145 ! Vector arithmetic exception register ( RO ) DECLARE LONG CONSTANT PR13_VAER$M_F_UNDF = x'00000001' DECLARE LONG CONSTANT PR13_VAER$M_F_DIVZ = x'00000002' DECLARE LONG CONSTANT PR13_VAER$M_F_ROPR = x'00000004' DECLARE LONG CONSTANT PR13_VAER$M_F_OVFL = x'00000008' DECLARE LONG CONSTANT PR13_VAER$M_I_OVFL = x'00000020' DECLARE LONG CONSTANT PR13_VAER$M_REGISTER_MASK = x'FFFF0000' DECLARE LONG CONSTANT PR13$_VMAC = 146 ! Vector memory activity register ( RO ) DECLARE LONG CONSTANT PR13$_VTBIA = 147 ! Vector translation buffer invalidate all ( WO ) ! Cbox registers. DECLARE LONG CONSTANT PR13$_CCTL = 160 ! Cbox control register ( RW ) DECLARE LONG CONSTANT PR13_CCTL$M_ENABLE = x'00000001' DECLARE LONG CONSTANT PR13_CCTL$M_TAG_SPEED = x'00000002' DECLARE LONG CONSTANT PR13_CCTL$K_TAG_3_CYCLES = 0 ! Select tag RAM speed: 3-cycle read rep/3-cycle write rep DECLARE LONG CONSTANT PR13_CCTL$K_TAG_4_CYCLES = 1 ! Select tag RAM speed: 4-cycle read rep/4-cycle write rep DECLARE LONG CONSTANT PR13_CCTL$M_DATA_SPEED = x'0000000C' DECLARE LONG CONSTANT PR13_CCTL$K_DATA_2_CYCLES = 0 ! Select data RAM speed: 2-cycle read rep/3-cycle write rep DECLARE LONG CONSTANT PR13_CCTL$K_DATA_3_CYCLES = 1 ! Select data RAM speed: 3-cycle read rep/4-cycle write rep DECLARE LONG CONSTANT PR13_CCTL$K_DATA_4_CYCLES = 2 ! Select data RAM speed: 4-cycle read rep/5-cycle write rep DECLARE LONG CONSTANT PR13_CCTL$M_SIZE = x'00000030' DECLARE LONG CONSTANT PR13_CCTL$K_SIZE_128KB = 0 ! Select 128KB Bcache DECLARE LONG CONSTANT PR13_CCTL$K_SIZE_256KB = 1 ! Select 256KB Bcache DECLARE LONG CONSTANT PR13_CCTL$K_SIZE_512KB = 2 ! Select 512KB Bcache DECLARE LONG CONSTANT PR13_CCTL$K_SIZE_2MB = 3 ! Select 2MB Bcache DECLARE LONG CONSTANT PR13_CCTL$M_FORCE_HIT = x'00000040' DECLARE LONG CONSTANT PR13_CCTL$M_DISABLE_ERRORS = x'00000080' DECLARE LONG CONSTANT PR13_CCTL$M_SW_ECC = x'00000100' DECLARE LONG CONSTANT PR13_CCTL$M_TIMEOUT_TEST = x'00000200' DECLARE LONG CONSTANT PR13_CCTL$M_DISABLE_PACK = x'00000400' DECLARE LONG CONSTANT PR13_CCTL$M_PM_ACCESS_TYPE = x'00003800' DECLARE LONG CONSTANT PR13_CCTL$K_PMAT_COH = 0 ! Coherency access of either type DECLARE LONG CONSTANT PR13_CCTL$K_PMAT_COH_READ = 1 ! Coherency access for READ DECLARE LONG CONSTANT PR13_CCTL$K_PMAT_COH_OREAD = 2 ! Coherency access for OREAD DECLARE LONG CONSTANT PR13_CCTL$K_PMAT_CPU = 4 ! CPU access of any type DECLARE LONG CONSTANT PR13_CCTL$K_PMAT_CPU_IREAD = 5 ! CPU access for IREAD DECLARE LONG CONSTANT PR13_CCTL$K_PMAT_CPU_DREAD = 6 ! CPU access for DREAD DECLARE LONG CONSTANT PR13_CCTL$K_PMAT_CPU_OREAD = 7 ! CPU access for OREAD DECLARE LONG CONSTANT PR13_CCTL$M_PM_HIT_TYPE = x'0000C000' DECLARE LONG CONSTANT PR13_CCTL$K_PMHT_HIT = 0 ! Hit DECLARE LONG CONSTANT PR13_CCTL$K_PMHT_HIT_OWNED = 1 ! Hit on owned block DECLARE LONG CONSTANT PR13_CCTL$K_PMHT_HIT_VALID = 2 ! Hit on valid block DECLARE LONG CONSTANT PR13_CCTL$K_PMHT_MISS_OWNED = 3 ! Miss on owned block ( causes writeback ) DECLARE LONG CONSTANT PR13_CCTL$M_FORCE_NDAL_PERR = x'00010000' DECLARE LONG CONSTANT PR13_CCTL$M_SW_ETM = x'40000000' DECLARE LONG CONSTANT PR13_CCTL$M_HW_ETM = x'80000000' DECLARE LONG CONSTANT PR13$_BCDECC = 162 ! Bcache data ram ECC ( WO ) DECLARE LONG CONSTANT PR13_BCDECC$M_ECCLO = x'000003C0' DECLARE LONG CONSTANT PR13_BCDECC$M_ECCHI = x'03C00000' DECLARE LONG CONSTANT PR13$_BCETSTS = 163 ! Bcache error tag status ( RW ) DECLARE LONG CONSTANT PR13_BCETSTS$M_LOCK = x'00000001' DECLARE LONG CONSTANT PR13_BCETSTS$M_CORR = x'00000002' DECLARE LONG CONSTANT PR13_BCETSTS$M_UNCORR = x'00000004' DECLARE LONG CONSTANT PR13_BCETSTS$M_BAD_ADDR = x'00000008' DECLARE LONG CONSTANT PR13_BCETSTS$M_LOST_ERR = x'00000010' DECLARE LONG CONSTANT PR13_BCETSTS$M_TS_CMD = x'000003E0' DECLARE LONG CONSTANT PR13_BCETSTS$K_CMD_DREAD = 7 ! Command was D-stream tag lookup DECLARE LONG CONSTANT PR13_BCETSTS$K_CMD_IREAD = 3 ! Command was I-stream tag lookup DECLARE LONG CONSTANT PR13_BCETSTS$K_CMD_OREAD = 2 ! Command was OREAD tag lookup for write or read lock DECLARE LONG CONSTANT PR13_BCETSTS$K_CMD_WUNLOCK = 8 ! Command was write unlock tag lookup ( done only under ETM ) DECLARE LONG CONSTANT PR13_BCETSTS$K_CMD_R_INVAL = 13 ! Command was inval tag lookup for NDAL DREAD or IREAD DECLARE LONG CONSTANT PR13_BCETSTS$K_CMD_O_INVAL = 9 ! Command was inval tag lookup for NDAL OREAD or WRITE DECLARE LONG CONSTANT PR13_BCETSTS$K_CMD_IPR_DEALLOC = 10 ! Command was tag lookup for IPR deallocate DECLARE LONG CONSTANT PR13$_BCETIDX = 164 ! Bcache error tag index ( RO ) DECLARE LONG CONSTANT PR13$_BCETAG = 165 ! Bcache error tag ( RO ) DECLARE LONG CONSTANT PR13_BCETAG$M_VALID = x'00000200' DECLARE LONG CONSTANT PR13_BCETAG$M_OWNED = x'00000400' DECLARE LONG CONSTANT PR13_BCETAG$M_ECC = x'0001F800' DECLARE LONG CONSTANT PR13_BCETAG$M_TAG = x'FFFE0000' DECLARE LONG CONSTANT PR13$_BCEDSTS = 166 ! Bcache error data status ( RW ) DECLARE LONG CONSTANT PR13_BCEDSTS$M_LOCK = x'00000001' DECLARE LONG CONSTANT PR13_BCEDSTS$M_CORR = x'00000002' DECLARE LONG CONSTANT PR13_BCEDSTS$M_UNCORR = x'00000004' DECLARE LONG CONSTANT PR13_BCEDSTS$M_BAD_ADDR = x'00000008' DECLARE LONG CONSTANT PR13_BCEDSTS$M_LOST_ERR = x'00000010' DECLARE LONG CONSTANT PR13_BCEDSTS$M_DR_CMD = x'00000F00' DECLARE LONG CONSTANT PR13_BCEDSTS$K_CMD_DREAD = 7 ! Command was D-stream data lookup DECLARE LONG CONSTANT PR13_BCEDSTS$K_CMD_IREAD = 3 ! Command was I-stream data lookup DECLARE LONG CONSTANT PR13_BCEDSTS$K_CMD_WBACK = 4 ! Command was writeback data lookup DECLARE LONG CONSTANT PR13_BCEDSTS$K_CMD_RMW = 2 ! Command was read-modify-write data lookup DECLARE LONG CONSTANT PR13$_BCEDIDX = 167 ! Bcache error data index ( RO ) DECLARE LONG CONSTANT PR13$_BCEDECC = 168 ! Bcache error ECC ( RO ) DECLARE LONG CONSTANT PR13_BCEDECC$M_ECCLO = x'000003C0' DECLARE LONG CONSTANT PR13_BCEDECC$M_ECCHI = x'03C00000' DECLARE LONG CONSTANT PR13$_CEFADR = 171 ! Fill error address ( RO ) DECLARE LONG CONSTANT PR13$_CEFSTS = 172 ! Fill error status ( RW ) DECLARE LONG CONSTANT PR13_CEFSTS$M_RDLK = x'00000001' DECLARE LONG CONSTANT PR13_CEFSTS$M_LOCK = x'00000002' DECLARE LONG CONSTANT PR13_CEFSTS$M_TIMEOUT = x'00000004' DECLARE LONG CONSTANT PR13_CEFSTS$M_RDE = x'00000008' DECLARE LONG CONSTANT PR13_CEFSTS$M_LOST_ERR = x'00000010' DECLARE LONG CONSTANT PR13_CEFSTS$M_ID0 = x'00000020' DECLARE LONG CONSTANT PR13_CEFSTS$M_IREAD = x'00000040' DECLARE LONG CONSTANT PR13_CEFSTS$M_OREAD = x'00000080' DECLARE LONG CONSTANT PR13_CEFSTS$M_WRITE = x'00000100' DECLARE LONG CONSTANT PR13_CEFSTS$M_TO_MBOX = x'00000200' DECLARE LONG CONSTANT PR13_CEFSTS$M_RIP = x'00000400' DECLARE LONG CONSTANT PR13_CEFSTS$M_OIP = x'00000800' DECLARE LONG CONSTANT PR13_CEFSTS$M_DNF = x'00001000' DECLARE LONG CONSTANT PR13_CEFSTS$M_RDLK_FL_DONE = x'00002000' DECLARE LONG CONSTANT PR13_CEFSTS$M_REQ_FILL_DONE = x'00004000' DECLARE LONG CONSTANT PR13_CEFSTS$M_COUNT = x'00018000' DECLARE LONG CONSTANT PR13_CEFSTS$M_UNEXPECTED_FILL = x'00200000' DECLARE LONG CONSTANT PR13$_NESTS = 174 ! NDAL error status ( RW ) DECLARE LONG CONSTANT PR13_NESTS$M_NOACK = x'00000001' DECLARE LONG CONSTANT PR13_NESTS$M_BADWDATA = x'00000002' DECLARE LONG CONSTANT PR13_NESTS$M_LOST_OERR = x'00000004' DECLARE LONG CONSTANT PR13_NESTS$M_PERR = x'00000008' DECLARE LONG CONSTANT PR13_NESTS$M_INCON_PERR = x'00000010' DECLARE LONG CONSTANT PR13_NESTS$M_LOST_PERR = x'00000020' DECLARE LONG CONSTANT PR13$_NEOADR = 176 ! NDAL error output address ( RO ) DECLARE LONG CONSTANT PR13$_NEOCMD = 178 ! NDAL error output command ( RO ) DECLARE LONG CONSTANT PR13_NEOCMD$M_CMD = x'0000000F' DECLARE LONG CONSTANT PR13_NEOCMD$M_ID = x'00000070' DECLARE LONG CONSTANT PR13_NEOCMD$M_BYTE_EN = x'0000FF00' DECLARE LONG CONSTANT PR13_NEOCMD$M_LEN = x'C0000000' DECLARE LONG CONSTANT PR13$_NEDATHI = 180 ! NDAL error data high ( RO ) DECLARE LONG CONSTANT PR13$_NEDATLO = 182 ! NDAL error data low ( RO ) DECLARE LONG CONSTANT PR13$_NEICMD = 184 ! NDAL error input command ( RO ) DECLARE LONG CONSTANT PR13_NEICMD$M_CMD = x'0000000F' DECLARE LONG CONSTANT PR13_NEICMD$M_ID = x'00000070' DECLARE LONG CONSTANT PR13_NEICMD$M_PARITY = x'00000380' DECLARE LONG CONSTANT PR13_NDAL$K_LEN_HW = 0 ! Length = hexaword DECLARE LONG CONSTANT PR13_NDAL$K_LEN_QW = 2 ! Length = quadword DECLARE LONG CONSTANT PR13_NDAL$K_LEN_OW = 3 ! Length = octaword ! encoded NDAL command values DECLARE LONG CONSTANT PR13_NDAL$K_CMD_NOP = 0 ! Command = NOP DECLARE LONG CONSTANT PR13_NDAL$K_CMD_WRITE = 2 ! Command = Write DECLARE LONG CONSTANT PR13_NDAL$K_CMD_WDISOWN = 3 ! Command = Write disown DECLARE LONG CONSTANT PR13_NDAL$K_CMD_IREAD = 4 ! Command = I-read DECLARE LONG CONSTANT PR13_NDAL$K_CMD_DREAD = 5 ! Command = D-read DECLARE LONG CONSTANT PR13_NDAL$K_CMD_OREAD = 6 ! Command = O-read DECLARE LONG CONSTANT PR13_NDAL$K_CMD_RDE = 9 ! Command = Read data error DECLARE LONG CONSTANT PR13_NDAL$K_CMD_WDATA = 10 ! Command = Write data DECLARE LONG CONSTANT PR13_NDAL$K_CMD_BADWDATA = 11 ! Command = Bad write data DECLARE LONG CONSTANT PR13_NDAL$K_CMD_RDR0 = 12 ! Command = Read data return 0 DECLARE LONG CONSTANT PR13_NDAL$K_CMD_RDR1 = 13 ! Command = Read data return 1 DECLARE LONG CONSTANT PR13_NDAL$K_CMD_RDR2 = 14 ! Command = Read data return 2 DECLARE LONG CONSTANT PR13_NDAL$K_CMD_RDR3 = 15 ! Command = Read data return 3 ! Cbox registers, continued DECLARE LONG CONSTANT PR13$_BCTAG = 16777216 ! First of 64K Bcache tag IPRs ( RW ) DECLARE LONG CONSTANT PR13$_BCTAG_128KB_MAX = 16908256 ! Last tag IPR for 128KB Bcache DECLARE LONG CONSTANT PR13$_BCTAG_256KB_MAX = 17039328 ! Last tag IPR for 256KB Bcache DECLARE LONG CONSTANT PR13$_BCTAG_512KB_MAX = 17301472 ! Last tag IPR for 512KB Bcache DECLARE LONG CONSTANT PR13$_BCTAG_2MB_MAX = 18874336 ! Last tag IPR for 2MB Bcache DECLARE LONG CONSTANT PR13_BCTAG$K_IPR_INCR = 32 ! Increment between Bcache tag IPR numbers DECLARE LONG CONSTANT PR13_BCTAG$M_VALID = x'00000200' DECLARE LONG CONSTANT PR13_BCTAG$M_OWNED = x'00000400' DECLARE LONG CONSTANT PR13_BCTAG$M_ECC = x'0001F800' DECLARE LONG CONSTANT PR13_BCTAG$M_TAG = x'FFFE0000' DECLARE LONG CONSTANT PR13$_BCFLUSH = 20971520 ! First of 64K Bcache tag deallocate IPRs ( WO ) DECLARE LONG CONSTANT PR13$_BCFLUSH_128KB_MAX = 21102560 ! Last deallocate IPR for 128KB Bcache DECLARE LONG CONSTANT PR13$_BCFLUSH_256KB_MAX = 21233632 ! Last deallocate IPR for 256KB Bcache DECLARE LONG CONSTANT PR13$_BCFLUSH_512KB_MAX = 21495776 ! Last deallocate IPR for 512KB Bcache DECLARE LONG CONSTANT PR13$_BCFLUSH_2MB_MAX = 23068640 ! Last deallocate IPR for 2MB Bcache DECLARE LONG CONSTANT PR13_BCFLUSH$K_IPR_INCR = 32 ! Increment between Bcache deallocate IPR numbers ! Ibox registers. DECLARE LONG CONSTANT PR13$_VMAR = 208 ! VIC memory address register DECLARE LONG CONSTANT PR13_VMAR$M_LW = x'00000004' DECLARE LONG CONSTANT PR13_VMAR$M_SUB_BLOCK = x'00000018' DECLARE LONG CONSTANT PR13_VMAR$M_ROW_INDEX = x'000007E0' DECLARE LONG CONSTANT PR13_VMAR$M_ADDR = x'FFFFF800' DECLARE LONG CONSTANT PR13$_VTAG = 209 ! VIC tag register DECLARE LONG CONSTANT PR13_VTAG$M_V = x'0000000F' DECLARE LONG CONSTANT PR13_VTAG$M_DP = x'000000F0' DECLARE LONG CONSTANT PR13_VTAG$M_TP = x'00000100' DECLARE LONG CONSTANT PR13_VTAG$M_TAG = x'FFFFF800' DECLARE LONG CONSTANT PR13$_VDATA = 210 ! VIC data register DECLARE LONG CONSTANT PR13$_ICSR = 211 ! Ibox control and status register ( RW ) DECLARE LONG CONSTANT PR13_ICSR$M_ENABLE = x'00000001' DECLARE LONG CONSTANT PR13_ICSR$M_LOCK = x'00000004' DECLARE LONG CONSTANT PR13_ICSR$M_DPERR = x'00000008' DECLARE LONG CONSTANT PR13_ICSR$M_TPERR = x'00000010' DECLARE LONG CONSTANT PR13$_BPCR = 212 ! Ibox branch prediction control register DECLARE LONG CONSTANT PR13_BPCR$M_HISTORY = x'0000000F' DECLARE LONG CONSTANT PR13_BPCR$M_MISPREDICT = x'00000020' DECLARE LONG CONSTANT PR13_BPCR$M_FLUSH_BHT = x'00000040' DECLARE LONG CONSTANT PR13_BPCR$M_FLUSH_CTR = x'00000080' DECLARE LONG CONSTANT PR13_BPCR$M_LOAD_HISTORY = x'00000100' DECLARE LONG CONSTANT PR13_BPCR$M_BPU_ALGORITHM = x'FFFF0000' DECLARE LONG CONSTANT PR13_BPCR$K_BPU_ALGORITHM = 65226 ! default value for BPU_ALGORITHM field DECLARE LONG CONSTANT PR13$_BPC = 214 ! Ibox Backup PC ( RO ) DECLARE LONG CONSTANT PR13$_BPCUNW = 215 ! Ibox Backup PC with RLOG unwind ( RO ) ! Mbox internal memory management registers. DECLARE LONG CONSTANT PR13$_MP0BR = 224 ! Mbox P0 base register ( RW ) DECLARE LONG CONSTANT PR13$_MP0LR = 225 ! Mbox P0 length register ( RW ) DECLARE LONG CONSTANT PR13$_MP1BR = 226 ! Mbox P1 base register ( RW ) DECLARE LONG CONSTANT PR13$_MP1LR = 227 ! Mbox P1 length register ( RW ) DECLARE LONG CONSTANT PR13$_MSBR = 228 ! Mbox system base register ( RW ) DECLARE LONG CONSTANT PR13$_MSLR = 229 ! Mbox system length register ( RW ) DECLARE LONG CONSTANT PR13$_MMAPEN = 230 ! Mbox memory management enable ( RW ) ! Mbox registers. DECLARE LONG CONSTANT PR13$_PAMODE = 231 ! Mbox physical address mode ( RW ) DECLARE LONG CONSTANT PR13_PAMODE$M_MODE = x'00000001' DECLARE LONG CONSTANT PR13_PAMODE$K_PA_30 = 0 ! 30-bit PA mode DECLARE LONG CONSTANT PR13_PAMODE$K_PA_32 = 1 ! 32-bit PA mode DECLARE LONG CONSTANT PR13$_MMEADR = 232 ! Mbox memory management fault address ( RO ) DECLARE LONG CONSTANT PR13$_MMEPTE = 233 ! Mbox memory management fault PTE address ( RO ) DECLARE LONG CONSTANT PR13$_MMESTS = 234 ! Mbox memory management fault status ( RO ) DECLARE LONG CONSTANT PR13_MMESTS$M_LV = x'00000001' DECLARE LONG CONSTANT PR13_MMESTS$M_PTE_REF = x'00000002' DECLARE LONG CONSTANT PR13_MMESTS$M_M = x'00000004' DECLARE LONG CONSTANT PR13_MMESTS$M_FAULT = x'0000C000' DECLARE LONG CONSTANT PR13_MMESTS$K_FAULT_ACV = 1 ! ACV fault DECLARE LONG CONSTANT PR13_MMESTS$K_FAULT_TNV = 2 ! TNV fault DECLARE LONG CONSTANT PR13_MMESTS$K_FAULT_M0 = 3 ! M=0 fault DECLARE LONG CONSTANT PR13_MMESTS$M_SRC = x'1C000000' DECLARE LONG CONSTANT PR13_MMESTS$M_LOCK = x'E0000000' DECLARE LONG CONSTANT PR13$_TBADR = 236 ! Mbox TB parity error address ( RO ) DECLARE LONG CONSTANT PR13$_TBSTS = 237 ! Mbox TB parity error status ( RW ) DECLARE LONG CONSTANT PR13_TBSTS$M_LOCK = x'00000001' DECLARE LONG CONSTANT PR13_TBSTS$M_DPERR = x'00000002' DECLARE LONG CONSTANT PR13_TBSTS$M_TPERR = x'00000004' DECLARE LONG CONSTANT PR13_TBSTS$M_EM_VAL = x'00000008' DECLARE LONG CONSTANT PR13_TBSTS$M_CMD = x'000001F0' DECLARE LONG CONSTANT PR13_TBSTS$M_SRC = x'E0000000' DECLARE LONG CONSTANT PR13_MSRC$K_IREF_LATCH = 6 ! Source of fault was IREF latch DECLARE LONG CONSTANT PR13_MSRC$K_SPEC_QUEUE = 4 ! Source of fault was spec queue DECLARE LONG CONSTANT PR13_MSRC$K_EM_LATCH = 0 ! Source of fault was EM latch ! Mbox Pcache registers DECLARE LONG CONSTANT PR13$_PCADR = 242 ! Mbox Pcache parity error address ( RO ) DECLARE LONG CONSTANT PR13$_PCSTS = 244 ! Mbox Pcache parity error status ( RW ) DECLARE LONG CONSTANT PR13_PCSTS$M_LOCK = x'00000001' DECLARE LONG CONSTANT PR13_PCSTS$M_DPERR = x'00000002' DECLARE LONG CONSTANT PR13_PCSTS$M_RIGHT_BANK = x'00000004' DECLARE LONG CONSTANT PR13_PCSTS$M_LEFT_BANK = x'00000008' DECLARE LONG CONSTANT PR13_PCSTS$M_CMD = x'000001F0' DECLARE LONG CONSTANT PR13_PCSTS$M_PTE_ER_WR = x'00000200' DECLARE LONG CONSTANT PR13_PCSTS$M_PTE_ER = x'00000400' DECLARE LONG CONSTANT PR13$_PCCTL = 248 ! Mbox Pcache control ( RW ) DECLARE LONG CONSTANT PR13_PCCTL$M_D_ENABLE = x'00000001' DECLARE LONG CONSTANT PR13_PCCTL$M_I_ENABLE = x'00000002' DECLARE LONG CONSTANT PR13_PCCTL$M_FORCE_HIT = x'00000004' DECLARE LONG CONSTANT PR13_PCCTL$M_BANK_SEL = x'00000008' DECLARE LONG CONSTANT PR13_PCCTL$M_P_ENABLE = x'00000010' DECLARE LONG CONSTANT PR13_PCCTL$M_PMM = x'000000E0' DECLARE LONG CONSTANT PR13_PCCTL$M_ELEC_DISABLE = x'00000100' DECLARE LONG CONSTANT PR13_PCCTL$M_RED_ENABLE = x'00000200' DECLARE LONG CONSTANT PR13$_PCTAG = 25165824 ! First of 256 Pcache tag IPRs ( RW ) DECLARE LONG CONSTANT PR13$_PCTAG_MAX = 25173984 ! Last of 256 Pcache tag IPRs DECLARE LONG CONSTANT PR13_PCTAG$K_IPR_INCR = 32 ! Increment between Pcache tag IPR numbers DECLARE LONG CONSTANT PR13_PCTAG$M_A = x'00000001' DECLARE LONG CONSTANT PR13_PCTAG$M_V = x'0000001E' DECLARE LONG CONSTANT PR13_PCTAG$M_P = x'00000020' DECLARE LONG CONSTANT PR13_PCTAG$M_TAG = x'FFFFF000' DECLARE LONG CONSTANT PR13$_PCDAP = 29360128 ! First of 1024 Pcache data parity IPRs ( RW ) DECLARE LONG CONSTANT PR13$_PCDAP_MAX = 29368312 ! Last of 1024 Pcache data parity IPRs DECLARE LONG CONSTANT PR13_PCDAP$K_IPR_INCR = 8 ! Increment between Pcache data parity IPR numbers DECLARE LONG CONSTANT PR13_PCDAP$M_DATA_PARITY = x'000000FF' DECLARE LONG CONSTANT PR13S_PR13DEF = 4 record PR13DEF variant ! Architecturally-defined registers which have different characteristics ! on this CPU. case group PR13R_PR13SAVPSL_BITS ! Saved PSL bits <7:0> ! Halt code containing one of the following values ! Invalid SAVPSL if = 1 ! MAPEN<0> ! Saved PSL bits <31:16> LONG PSL_LO_bits ! COMMENT ADDED BY SDL - PSL_LO_bits contains bits PSL_LO through PSL_HI end group PR13R_PR13SAVPSL_BITS case group PR13R_PR13SID_BITS ! Microcode (chip) revision number ! PCS loaded with a non-standard patch ! Patch revision number ! CPU type code (19 decimal for NVAX) LONG UCODE_REV_bits ! COMMENT ADDED BY SDL - UCODE_REV_bits contains bits UCODE_REV through TYPE end group PR13R_PR13SID_BITS ! System-level required registers. ! These registers are for testability and diagnostics use only. ! They should not be referenced in normal operation. case group PR13R_PR13IAK_VECTOR ! Vector returned in response to IAK1x read ! Force IPL 17, independent of actual level ! Passive release ! LW offset in SCB of interrupt vector LONG IPL17_bits ! COMMENT ADDED BY SDL - IPL17_bits contains bits IPL17 through FILL_1 end group PR13R_PR13IAK_VECTOR ! Ebox register definition case group PR13R_PR13INTSYS_BITS ! ICCS<6> (RO) ! SISR<15:1> (RO) ! ID of highest pending interrupt (RO) ! Interval timer interrupt reset (WC) ! Soft error interrupt reset (WC) ! Performance monitoring interrupt reset (WC) ! Hard error interrupt reset (WC) ! Power fail interrupt reset (WC) ! Halt pin interrupt reset (WC) LONG ICCS6_bits ! COMMENT ADDED BY SDL - ICCS6_bits contains bits ICCS6 through HALT_RESET end group PR13R_PR13INTSYS_BITS case group PR13R_PR13PMFCNT_BITS ! PMCTR0 word ! PMCTR1 word LONG PMCTR0_bits ! COMMENT ADDED BY SDL - PMCTR0_bits contains bits PMCTR0 through PMCTR1 end group PR13R_PR13PMFCNT_BITS case group PR13R_PR13PCSCR_BITS ! Disable parallel port control of scan chain (RW) ! Enable use of patchable control store (RW) ! Write scan chain to patchable control store (WO) ! Shift read-write latch scan chain by one bit (WO) ! Data to be shifted into the PCS scan chain (RW) ! PCS loaded with a non-standard patch (RW) ! Patch revision number (RW) LONG FILL_1_bits ! COMMENT ADDED BY SDL - FILL_1_bits contains bits FILL_1 through FILL_3 end group PR13R_PR13PCSCR_BITS case group PR13R_PR13ECR_BITS ! Vector unit present (RW) ! Fbox enabled (RW) ! Select external timebase for S3 stall timeout timer (RW) ! Fbox stage 4 conditional bypass enable (RW) ! S3 stall timeout occurred (WC) ! Select test mode for S3 stall timeout (RW) ! Clock S3 timeout (RW) ! Full ICCS implemented in external logic (RW) ! Enable test of Fbox (RW) ! Performance monitoring facility enable (RW) ! Performance monitoring facility master select (RW) ! Performance monitoring facility Ebox mux select (RW) ! Performance monitoring facility Wbus LFSR enable (RW) ! Clear performance monitoring hardware counters (WO) LONG VECTOR_PRESENT_bits ! COMMENT ADDED BY SDL - VECTOR_PRESENT_bits contains bits VECTOR_PRESENT through & ! PMF_CLEAR end group PR13R_PR13ECR_BITS ! Mbox TB registers. ! These registers are for testability and diagnostics use only. ! They should not be referenced in normal operation. case group PR13R_PR13MTBTAG_BITS ! Tag parity bit ! Virtual page number of address (VA<31:9>) LONG TP_bits ! COMMENT ADDED BY SDL - TP_bits contains bits TP through VPN end group PR13R_PR13MTBTAG_BITS case group PR13R_PR13MTBPTE_BITS ! Format is normal PTE format, except for PTE parity bit ! Page frame number (PA<31:9>) ! PTE parity ! Modify bit ! Protection field ! PTE valid bit LONG PFN_bits ! COMMENT ADDED BY SDL - PFN_bits contains bits PFN through fill_103 end group PR13R_PR13MTBPTE_BITS ! Vector architecture registers case group PR13R_PR13VPSR_BITS ! Vector processor enabled (RW) ! Vector processor state reset (WO) ! Vector arithmetic exception (WC) ! Implementation-specific hardware error (WC) ! Vector processor busy (RO) LONG VEN_bits ! COMMENT ADDED BY SDL - VEN_bits contains bits VEN through BSY end group PR13R_PR13VPSR_BITS case group PR13R_PR13VAER_BITS ! Floating underflow ! Floating divide-by-zero ! Floating reserved operand ! Floating overflow ! Integer overflow ! Vector destination register mask LONG F_UNDF_bits ! COMMENT ADDED BY SDL - F_UNDF_bits contains bits F_UNDF through REGISTER_MASK end group PR13R_PR13VAER_BITS case group PR13R_PR13CCTL_BITS ! Enable Bcache (RW) ! Tag RAM speed (RW) ! Data RAM speed (RW) ! Bcache size (RW) ! Force Bcache hit (RW) ! Disable Bcache ECC errors (RW) ! Enable use of software ECC (RW) ! Enable test of Cbox read timeout counters (RW) ! Disable write packing (RW) ! Performance monitoring access type (RW) ! Performance monitoring hit type (RW) ! Forces 1 parity error on the NDAL, on next outgoing transaction ! Enter software error transition mode (RW) ! Error transition mode entered due to error (WC) LONG ENABLE_bits ! COMMENT ADDED BY SDL - ENABLE_bits contains bits ENABLE through HW_ETM end group PR13R_PR13CCTL_BITS case group PR13R_PR13BCDECC_BITS ! ECC check bits <3:0> ! ECC check bits <7:4> LONG FILL_1_bits ! COMMENT ADDED BY SDL - FILL_1_bits contains bits FILL_1 through FILL_3 end group PR13R_PR13BCDECC_BITS ! Cbox registers, continued case group PR13R_PR13BCETSTS_BITS ! Tag store registers are locked due to an error (WC) ! Correctable error occurred (WC) ! Uncorrectable error occurred (WC) ! Addressing error occurred (WC) ! Error occured while register was locked (WC) ! Tag store command which caused error (RO) LONG LOCK_bits ! COMMENT ADDED BY SDL - LOCK_bits contains bits LOCK through FILL_1 end group PR13R_PR13BCETSTS_BITS case group PR13R_PR13BCETAG_BITS ! Valid bit ! Ownership bit ! ECC bits ! tag data LONG FILL_1_bits ! COMMENT ADDED BY SDL - FILL_1_bits contains bits FILL_1 through TAG end group PR13R_PR13BCETAG_BITS ! Cbox registers, continued case group PR13R_PR13BCEDSTS_BITS ! Data RAM registers are locked due to an error (WC) ! Correctable ECC error occurred (WC) ! Uncorrectable ECC error occurred (WC) ! Addressing error occurred (WC) ! Error occurred while register was locked (WC) ! Data RAM command which caused error (RO) LONG LOCK_bits ! COMMENT ADDED BY SDL - LOCK_bits contains bits LOCK through FILL_2 end group PR13R_PR13BCEDSTS_BITS case group PR13R_PR13BCEDECC_BITS ! Bcache data ECC syndrome bits <3:0> ! Bcache data ECC syndrome bits <7:4> LONG FILL_1_bits ! COMMENT ADDED BY SDL - FILL_1_bits contains bits FILL_1 through FILL_3 end group PR13R_PR13BCEDECC_BITS ! Cbox registers, continued case group PR13R_PR13CEFSTS_BITS ! Error occurred during a read lock (WC) ! CEFSTS ? CEFADR registers are locked due to an error (WC) ! Fill failed due to transaction timeout (WC) ! Fill failed due to Read Data Error (WC) ! Error occurred while register was locked (WC) ! NDAL id<0> for failed read (RO) ! Error occured during an IREAD (RO) ! Error occurred during an OREAD (RO) ! Error occurred during a write (RO) ! Data was destined for the Mbox (RO) ! READ invalidate was pending (RO) ! OREAD invalidate was pending (RO) ! Data was not to be validated when fill completed (RO) ! Last fill for read lock received (RO) ! Requested fill quadword was received for this read. ! Number of requested QW of fill received (RO) ! RDE or RDR was received from the NDAL when fill_cam not valid (WC) LONG RDLK_bits ! COMMENT ADDED BY SDL - RDLK_bits contains bits RDLK through FILL_2 end group PR13R_PR13CEFSTS_BITS ! Cbox registers, continued case group PR13R_PR13NESTS_BITS ! Outgoing command was NACKed (WC) ! BADWDATA cycle transmitted (WC) ! Outgoing error was lost while register was locked (WC) ! NDAL parity error detected (WC) ! Inconsistent parity error (parity error detected on ! NDAL parity error detected while register was locked (WC) ! ACKed transaction) (WC) LONG NOACK_bits ! COMMENT ADDED BY SDL - NOACK_bits contains bits NOACK through FILL_1 end group PR13R_PR13NESTS_BITS case group PR13R_PR13NEOCMD_BITS ! NDAL command on outgoing error transaction (see below) ! NDAL ID on outgoing error transaction ! Byte enables on outgoing error transaction ! Length on outgoing error transaction (see below) LONG CMD_bits ! COMMENT ADDED BY SDL - CMD_bits contains bits CMD through LEN end group PR13R_PR13NEOCMD_BITS case group PR13R_PR13NEICMD_BITS ! NDAL command received on error transaction (see below) ! NDAL ID received error on transaction ! NDAL parity bits received error on transaction LONG CMD_bits ! COMMENT ADDED BY SDL - CMD_bits contains bits CMD through FILL_1 end group PR13R_PR13NEICMD_BITS ! Encoded NDAL length values case group PR13R_PR13BCTAG_BITS ! Valid bit (RW) ! Ownership bit (RW) ! ECC bits (RW) ! tag data (RW) LONG FILL_1_bits ! COMMENT ADDED BY SDL - FILL_1_bits contains bits FILL_1 through TAG end group PR13R_PR13BCTAG_BITS case group PR13R_PR13VMAR_BITS ! longword within quadword ! sub-block indicator ! cache row index ! error address LONG FILL_1_bits ! COMMENT ADDED BY SDL - FILL_1_bits contains bits FILL_1 through ADDR end group PR13R_PR13VMAR_BITS case group PR13R_PR13VTAG_BITS ! data valid bits ! data parity bits ! tag parity bit ! unused bits (zero) ! tag LONG V_bits ! COMMENT ADDED BY SDL - V_bits contains bits V through TAG end group PR13R_PR13VTAG_BITS case group PR13R_PR13ICSR_BITS ! VIC enable bit (RW) ! Register is locked due to an error (WC) ! Data parity error (RO) ! Tag parity error (RO) LONG ENABLE_bits ! COMMENT ADDED BY SDL - ENABLE_bits contains bits ENABLE through FILL_2 end group PR13R_PR13ICSR_BITS case group PR13R_PR13BPCR_BITS ! branch history bits ! history of last branch ! flush branch history table ! flush branch hist addr counter ! write new history to array ! unused bits (must be zero) ! branch prediction algorithm LONG HISTORY_bits ! COMMENT ADDED BY SDL - HISTORY_bits contains bits HISTORY through BPU_ALGORITHM end group PR13R_PR13BPCR_BITS ! The following two registers are for testability and diagnostics use only. ! They should not be referenced in normal operation. ! These registers are for testability and diagnostics use only. ! In normal operation, the equivalent architecturally-defined registers ! should be used instead. case group PR13R_PR13PAMODE_BITS ! Addressing mode(1 = 32bit addressing) (RW) LONG MODE_bits ! COMMENT ADDED BY SDL - MODE_bits contains bits MODE through FILL_1 end group PR13R_PR13PAMODE_BITS case group PR13R_PR13MMESTS_BITS ! ACV fault due to length violation ! ACV/TNV fault occurred on PPTE reference ! Reference had write or modify intent ! Fault type, one of the following: ! Shadow copy of LOCK bits (see MSRC$ constants below) ! Lock status (see MSRC$ constant below) LONG LV_bits ! COMMENT ADDED BY SDL - LV_bits contains bits LV through LOCK end group PR13R_PR13MMESTS_BITS case group PR13R_PR13TBSTS_BITS ! Register is locked due to an error (WC) ! Data parity error (RO) ! Tag parity error (RO) ! EM latch was valid when error occurred (RO) ! S5 command when TB parity error occured (RO) ! Source of original refernce (see MSRC$ constants below) (RO) LONG LOCK_bits ! COMMENT ADDED BY SDL - LOCK_bits contains bits LOCK through SRC end group PR13R_PR13TBSTS_BITS case group PR13R_PR13PCSTS_BITS ! Register is locked due to an error (WC) ! Data parity error occurred (RO) ! Right bank tag parity error occurred (RO) ! Left bank tag parity error occurred (RO) ! S6 command when Pcache parity error occured (RO) ! Hard error on PTE DREAD occurred (orig ref was WRITE) (WC) ! Hard error on PTE DREAD occurred (WC) LONG LOCK_bits ! COMMENT ADDED BY SDL - LOCK_bits contains bits LOCK through FILL_1 end group PR13R_PR13PCSTS_BITS case group PR13R_PR13PCCTL_BITS ! Enable for invalidate, D-stream read/write/fill (RW) ! Enable for invalidate, I-stream read/fill (RW) ! Enable force hit on Pcache references (RW) ! Select left bank if 0, right bank if 1 (RW) ! Enable parity checking (RW) ! Mbox performance monitor mode (RW) ! Pcache electrical disable bit (RW) ! Redundancy enable bit (RO) LONG D_ENABLE_bits ! COMMENT ADDED BY SDL - D_ENABLE_bits contains bits D_ENABLE through FILL_1 end group PR13R_PR13PCCTL_BITS case group PR13R_PR13PCTAG_BITS ! Allocation bit corresponding to index of this tag (RW) ! Valid bits corresponding to the 4 data subblocks (RW) ! Tag parity (RW) ! Tag bits (RW) LONG A_bits ! COMMENT ADDED BY SDL - A_bits contains bits A through TAG end group PR13R_PR13PCTAG_BITS case group PR13R_PR13PCDAP_BITS ! Even byte parity for the addressed quadword (RW) LONG DATA_PARITY_bits ! COMMENT ADDED BY SDL - DATA_PARITY_bits contains bits DATA_PARITY through FILL_1 end group PR13R_PR13PCDAP_BITS end variant end record PR13DEF