/sys$common/syshlp/helplib.hlb MACRO, VAX MACRO Assembler, Vector Instructions, VLD  *Conan The Librarian (sorry for the slow response - running on an old VAX)

    Load Memory Data into Vector Register

    Format:

      VLDL   [/M[0|1]]   base, stride, Vc

      VLDQ   [/M[0|1]]   base, stride, Vc

    Architecture

    Format
    opcode   cntrl.rw, base.ab, stride.rl
    opcodes

    34FD    VLDL      Load Longword Vector from Memory to Vector
                      Register

    36FD    VLDQ      Load Quadword Vector from Memory to Vector
                      Register

    vector control word

             1 1 1 1 1
             5 4 3 2 1     8 7     4 3     0
            +-+-+-+-+-------+-------+-------+
            |M|M|M| |       |       |       |
            |O|T|I|0|   0   |   0   |  Vc   |
            |E|F| | |       |       |       |
            +-+-+-+-+-------+-------+-------+
    exceptions

       access control violation
       translation not valid
       vector alignment

    operation
      addr <- base

      FOR i <- 0 TO VLR-1
        BEGIN
          IF {{MOE EQL 0} OR {{MOE EQL 1} AND {VMR<i> EQL MTF}}} THEN
            BEGIN
              IF {addr unaligned} THEN
                 {Vector Alignment Exception}

              IF VLDL THEN
                 Vc[i] <- (addr)<31:0>
              IF VLDQ THEN
                 Vc[i] <- (addr)<63:0>
            END
          addr <- addr + stride               !Increment by stride
        END