/sys$common/syshlp/helplib.hlb MACRO, VAX MACRO Assembler, Vector Instructions, VDIV  *Conan The Librarian (sorry for the slow response - running on an old VAX)

      Vector Floating Divide

    Format:

      vector/vector:

       { VVDIVF }
       { VVDIVD }    [/U[0|1]]    Va, Vb, Vc
       { VVDIVG }
       {        }

      scalar/vector:

       { VSDIVF }

       { VSDIVD }    [/U[0|1]]    scalar, Vb, Vc
       { VSDIVG }
       {        }

    Architecture

    Format
    vector/vector:

       opcode   cntrl.rw

    scalar/vector (F_floating):

       opcode   cntrl.rw, divd.rl

    scalar/vector (D_ and G_floating):

       opcode   cntrl.rw, divd.rq
    opcodes

    ACFD    VVDIVF    Vector Vector Divide F_floating

    ADFD    VSDIVF    Vector Scalar Divide F_floating

    AEFD    VVDIVD    Vector Vector Divide D_floating

    AFFD    VSDIVD    Vector Scalar Divide D_floating

    AAFD    VVDIVG    Vector Vector Divide G_floating

    ABFD    VSDIVG    Vector Scalar Divide G_floating

    vector_control_word

             1 1 1 1 1
             5 4 3 2 1     8 7     4 3     0
            +-+-+-+-+-------+-------+-------+
            |M|M|E| |  Va   |       |       |
            |O|T|X|0|  or   |  Vb   |  Vc   |
            |E|F|C| |  0    |       |       |
            +-+-+-+-+-------+-------+-------+
    exceptions

       floating divide by zero
       floating overflow
       floating reserved operand
       floating underflow

    operation
      FOR i <- 0 TO VLR-1
        IF {{MOE EQL 0} OR {{MOE EQL 1} AND {VMR<i> EQL MTF}}} THEN
          BEGIN
            IF VVDIVF THEN
               Vc[i]<31:0> <- Va[i]<31:0> / Vb[i]<31:0>

            IF VSDIVF THEN
               Vc[i]<31:0> <- divd / Vb[i]<31:0>

            IF VVDIVD OR VVDIVG THEN
               Vc[i] <- Va[i] / Vb[i]
            IF VSDIVD OR VSDIVG THEN
               Vc[i] <- divd / Vb[i]
          END