/sys$common/syshlp/helplib.hlb MACRO, /MIGRATION, Alpha Instruction Built-Ins  *Conan The Librarian (sorry for the slow response - running on an old VAX)

    Ported VAX MACRO code sometimes requires access to Alpha
    native instructions to deal directly with a 64-bit quantity
    or to include an Alpha instruction that has no VAX equivalent.
    The compiler provides built-ins to allow you access to these
    instructions.

                                   NOTE

       Be careful when mixing built-ins with VAX MACRO instructions
       on the same registers. The code generated by the compiler
       expects registers to contain 32-bit sign extended values,
       but it is possible to create 64-bit register values that are
       not in this format. Subsequent longword operations on these
       registers could produce incorrect results.

       Therefore, make sure to return registers to 32-bit sign
       extended format before using them in VAX MACRO instructions
       as source operands. (Loading the register with a new value
       using a VAX MACRO instruction (such as MOVL) returns it to
       this format.)

    You use these built-ins in the same way that you use native VAX
    instructions, using any VAX operand mode. For example, EVAX_
    ADDQ 8(R0),(SP)+,R1 is legal. The only exception is that the
    first operand of any Alpha load/store built-in (EVAX_LD*, EVAX_
    ST*) must be a register.

    It is recommended that you place any built-in within an
    ".IF DF,EVAX"  conditional code block unless the module is Alpha
    specific.

    The following byte and word built-ins are included in the MACRO-
    32 compiler, starting with OpenVMS Alpha Version 7.1:

    o  EVAX_LDBU

    o  EVAX_LDWU

    o  EVAX_STB

    o  EVAX_STW

    o  EVAX_SEXTB

    o  EVAX_SEXTW

    The best environment in which to run code that contains the byte
    and word built-ins is on an Alpha computer that implements these
    instructions in hardware. If you run such code on an OpenVMS
    Alpha system that implements them by software emulation, the
    following limitations exist:

    o  Significant performance loss

       The overhead of handling the exception to trigger the software
       emulation causes a significant performance loss. If software
       emulation is in effect, you will see the following message:

       %SYSTEM-I-EMULATED, an instruction not implemented on this
                           processor was emulated

    o  Some capabilities not present in the software emulation

       The software emulation is not capable of providing all
       the capabilities that would be present on a system that
       implemented the the instructions in hardware. Code that
       executes in inner access modes and at elevated IPL is allowed
       to use these instructions. For example, activation of the
       software emulator above IPL 2 will not cause a bugcheck.
       However, certain applications where these instructions
       might be useful, such as direct writes to hardware control
       registers, will be impossible, because such applications
       require the presence of address lines whose function cannot
       be emulated.

    Furthermore, if the code with these built-ins executes on a
    system without either the byte and word software emulator or
    a processor that implements the byte and word instructions in
    hardware, it will incur a fatal exception, such as the following:

    %SYSTEM-F-OPCDEC, opcode reserved to Digital fault at
    PC=00000000000020068,PS=0000001B

    The following table summarizes the Alpha built-ins supported by
    the compiler.

                                   NOTE

       Memory references in the MACRO-32 compiler built-ins are
       always assumed to be quadword aligned except in EVAX_SEXTB,
       EVAX_SEXTW, EVAX_LDBU, EVAX_LDWU, EVAX_STB, EVAX_STW, EVAX_
       LDQU, and EVAX_STQU.

    Built-in      Operands      Description

    EVAX_SEXTB    <RQ,WB>       Sign extend byte
    EVAX_SEXTW    <RQ,WW>       Sign extend word
    EVAX_SEXTL    <RQ,WL>       Sign extend longword

    EVAX_LDBU     <WQ,AB>       Load zero-extended byte from memory
    EVAX_LDWU     <WQ,AQ>       Load zero-extended word from memory
    EVAX_LDLL     <WL,AL>       Load longword locked
    EVAX_LDAQ     <WQ,AQ>       Load address of quadword
    EVAX_LDQ      <WQ,AQ>       Load quadword
    EVAX_LDQL     <WQ,AQ>       Load quadword locked
    EVAX_LDQU     <WQ,AQ>       Load unaligned quadword

    EVAX_STB      <RQ,AB>       Store byte from register to memory
    EVAX_STW      <RQ,AW>       Store word from register to memory
    EVAX_STLC     <ML,AL>       Store longword conditional
    EVAX_STQ      <RQ,AQ>       Store quadword
    EVAX_STQC     <MQ,AQ>       Store quadword conditional
    EVAX_STQU     <RQ,AQ>       Store unaligned quadword

    EVAX_ADDQ     <RQ,RQ,WQ>    Quadword add
    EVAX_SUBQ     <RQ,RQ,WQ>    Quadword subtract
    EVAX_MULQ     <RQ,RQ,WQ>    Quadword multiply
    EVAX_UMULH    <RQ,RQ,WQ>    Unsigned quadword multiply high

    EVAX_AND      <RQ,RQ,WQ>    Logical product
    EVAX_OR       <RQ,RQ,WQ>    Logical sum
    EVAX_XOR      <RQ,RQ,WQ>    Logical difference
    EVAX_BIC      <RQ,RQ,WQ>    Bit clear
    EVAX_ORNOT    <RQ,RQ,WQ>    Logical sum with complement
    EVAX_EQV      <RQ,RQ,WQ>    Logical equivalence
    EVAX_SLL      <RQ,RQ,WQ>    Shift left logical
    EVAX_SRL      <RQ,RQ,WQ>    Shift right logical
    EVAX_SRA      <RQ,RQ,WQ>    Shift right arithmetic

    EVAX_EXTBL    <RQ,RQ,WQ>    Extract byte low
    EVAX_EXTWL    <RQ,RQ,WQ>    Extract word low
    EVAX_EXTLL    <RQ,RQ,WQ>    Extract longword low
    EVAX_EXTQL    <RQ,RQ,WQ>    Extract quadword low
    EVAX_EXTBH    <RQ,RQ,WQ>    Extract byte high
    EVAX_EXTWH    <RQ,RQ,WQ>    Extract word high
    EVAX_EXTLH    <RQ,RQ,WQ>    Extract longword high
    EVAX_EXTQH    <RQ,RQ,WQ>    Extract quadword high

    EVAX_INSBL    <RQ,RQ,WQ>    Insert byte low
    EVAX_INSWL    <RQ,RQ,WQ>    Insert word low
    EVAX_INSLL    <RQ,RQ,WQ>    Insert longword low
    EVAX_INSQL    <RQ,RQ,WQ>    Insert quadword low
    EVAX_INSBH    <RQ,RQ,WQ>    Insert byte high
    EVAX_INSWH    <RQ,RQ,WQ>    Insert word high
    EVAX_INSLH    <RQ,RQ,WQ>    Insert longword high
    EVAX_INSQH    <RQ,RQ,WQ>    Insert quadword high

    EVAX_TRAPB    <>            Trap barrier
    EVAX_MB       <>            Memory barrier
    EVAX_RPCC     <WQ>          Read process cycle counter

    EVAX_CMPEQ    <RQ,RQ,WQ>    Integer signed compare, equal
    EVAX_CMPLT    <RQ,RQ,WQ>    Integer signed compare, less than
    EVAX_CMPLE    <RQ,RQ,WQ>    Integer signed compare, less equal
    EVAX_CMPULT   <RQ,RQ,WQ>    Integer unsigned compare, less than
    EVAX_CMPULE   <RQ,RQ,WQ>    Integer unsigned compare, less equal

    EVAX_BEQ      <RQ,AQ>       Branch equal
    EVAX_BLT      <RQ,AQ>       Branch less than
    EVAX_BNE      <RQ,AQ>       Branch not equal

    EVAX_CMOVEQ   <RQ,RQ,WQ>    Conditional move/equal
    EVAX_CMOVNE   <RQ,RQ,WQ>    Conditional move/not equal
    EVAX_CMOVLT   <RQ,RQ,WQ>    Conditional move/less than
    EVAX_CMOVLE   <RQ,RQ,WQ>    Conditional move/less or equal
    EVAX_CMOVGT   <RQ,RQ,WQ>    Conditional move/greater than
    EVAX_CMOVGE   <RQ,RQ,WQ>    Conditional move/greater or equal
    EVAX_CMOVLBC  <RQ,RQ,WQ>    Conditional move/low bit clear
    EVAX_CMOVLBS  <RQ,RQ,WQ>    Conditional move/low bit set

    EVAX_MF_FPCR  <WQ>          Move from floating-point control
                                register
    EVAX_MT_FPCR  <WQ,RQ>       Move to floating-point control
                                register
    EVAX_ZAP      <RQ,RQ,WQ>    Zero bytes
    EVAX_ZAPNOT   <RQ,RQ,WQ>    Zero bytes with NOT mask